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Component Implementation
1 - GateDrv0Ctrl_IntegrationManual
Integration Manual
For
Gate Drive 0 Control
VERSION: 3
DATE: 11-Sep-2017
Prepared By:
Shruthi Raghavan,
Nexteer Automotive,
Saginaw, MI, USA
Location: The official version of this document is stored in the Nexteer Configuration Management System.
Revision History
| Version | Description | Author | Date |
| 1 | Initial version | Rijvi Ahmed | 08-July-2016 |
| 2 | Updated for SPI MCAL update in FDD v2.2.0 | Shruthi Raghavan | 15-Mar-2017 |
| 3 | Details of new config parameter added. | Shruthi Raghavan | 11-Sep-2017 |
Table of Contents
3.2 Global Functions(Non RTE) to be provided to Integration Project 6
4 Configuration REQUIREMeNTS 7
4.2 Configuration Files to be provided by Integration Project 7
4.3 Da Vinci Parameter Configuration Changes 7
4.4 DaVinci Interrupt Configuration Changes 7
4.5 Manual Configuration Changes 7
5 Integration DATAFLOW REQUIREMENTS 8
5.1 Required Global Data Inputs 8
5.2 Required Global Data Outputs 8
5.3 Specific Include Path present 8
Abbrevations And Acronyms
| Abbreviation | Description |
| DFD | Design functional diagram |
| MDD | Module design Document |
References
This section lists the title & version of all the documents that are referred for development of this document
| Sr. No. | Title | Version |
| 1 | Software Naming Conventions | Process 04.04.02 |
| 2 | Software Coding Standards | Process 04.04.02 |
| 3 | FDD – ES311A GateDrv0Ctrl | See synergy sub project version |
Dependencies
SWCs
| Module | Required Feature |
| Spi_Renesas_Ar4.0.3_01.06.05_HF |
Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.
Global Functions(Non RTE) to be provided to Integration Project
None
Configuration REQUIREMeNTS
Build Time Config
| Modules | Notes | |
| None |
Configuration Files to be provided by Integration Project
None
Da Vinci Parameter Configuration Changes
| Parameter | Notes | SWC |
/Nexteer/GateDrv0Ctrl/GateDrv0CtrlGenCfg/ GateDrv0FetFltMtgtnEna | GATEDRV0FETFLTMTGTNENA_ULS_LOGL: Field effect transistor fault mitigation enable. If TRUE, the gate drive component will notify the system when a FET fault is detected. | GateDrv0Ctrl |
DaVinci Interrupt Configuration Changes
| ISR Name | VIM # | Priority Dependency | Notes |
| None |
Manual Configuration Changes
| Constant | Notes | SWC |
| None |
Integration DATAFLOW REQUIREMENTS
Required Global Data Inputs
See FDD DataDict.m.
Required Global Data Outputs
See FDD DataDict.m.
Specific Include Path present
No
Runnable Scheduling
This section specifies the required runnable scheduling.
| Init | Scheduling Requirements | Trigger |
| GateDrv0CtrlInit1 | None | RTE (Init) |
| Runnable | Scheduling Requirements | Trigger |
| GateDrv0CtrlPer1 | At the beginning of all 2ms Tasks as close as possible | RTE (2 ms) |
| GateDrv0CtrlPer2 | At the end of all 2ms Tasks as close as possible | RTE (2 ms) |
Memory Map REQUIREMENTS
Mapping
| Memory Section * | Contents | Notes |
| None |
* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.
Usage
| Feature | RAM | ROM |
| None |
Non RTE NvM Blocks
| Block Name |
| None |
Note : Size of the NVM block if configured in configurator
RTE NvM Blocks
| Block Name |
| None |
Note : Size of the NVM block if configured in developer
Compiler Settings
Preprocessor MACRO
None
Optimization Settings
None
2 - GateDrv0Ctrl_MDD
Module Design Document
For
Gate Drive 0 Control
VERSION: 9
DATE: 12-Jan-2018
Prepared By:
Shawn Penning,
Nexteer Automotive,
Saginaw, MI, USA
Location: The official version of this document is stored in the Nexteer Configuration Management System.
Revision History
| Version | Description | Author | Date |
| 1 | Initial version | Rijvi Ahmed | 07-July-2016 |
| 2 | Updated to design revision 1.8.0 | Avinash James | 21-Jan-2017 |
| 3 | Updated to design revision 2.0.0 | Shruthi Raghavan | 17-Feb-2017 |
| 4 | Updated to design revision 2.1.0 | Shruthi Raghavan | 27-Feb-2017 |
| 5 | Updated to design revision 2.3.0 | Shruthi Raghavan | 14-Mar-2017 |
| 6 | Updated to design revision 2.4.0 – Fix for phase reasonableness issues found during integration | Shruthi Raghavan | 24-Mar-2017 |
| 7 | Removed unused inputs from OperFltMonSt function. Added UT considerations per anomaly EA4#11845 | Shruthi Raghavan | 26-May-2017 |
| 8 | Updated graphical representation for the new outputs and client call. Added details for changed & new local functions Added new enum type and local constant | Shruthi Raghavan | 11-Sep-2017 |
| 9 | Updated design rationale for the state machine in Configuration State of gate drive. Added UT considerations per test corrections required in anomaly corrective action. | Shawn Penning | 12-Jan-2018 |
Table of Contents
3 GATEDRV0CTRL & High-Level Description 7
4 Design details of software module 8
4.1 Graphical representation of GATEDRV0CTRL 8
5.1 User defined typedef definition/declaration 9
5.2 Variable definition for enumerated types 9
6.1 Program(fixed) Constants 10
6.1.2 Module specific Lookup Tables Constants 10
7 Software Module Implementation 11
7.2 Initialization Functions 11
7.2.1 Per: GateDrv0CtrlInit1 11
7.3.1 Per: GateDrv0CtrlPer1 11
7.3.1.2 Processing of Function 11
7.3.2 Per: GateDrv0CtrlPer2 11
7.3.2.2 Processing of Function 11
7.5 Serial Communication Functions 11
7.6 Local Function/Macro Definitions 12
7.7 GLObAL Function/Macro Definitions 14
8 Known Limitations With Design 15
Abbrevations And Acronyms
| Abbreviation | Description |
| DFD | Design functional diagram |
| MDD | Module design Document |
References
This section lists the title & version of all the documents that are referred for development of this document
| Sr. No. | Title | Version |
| 1 | MDD Guidelines | 1.02 |
| 2 | Software Naming Conventions | 1.02 |
| 3 | Software Coding Standards | 1.01 |
| 4 | FDD – ES311A_GateDrv0Ctrl_Design | See synergy sub project version |
GATEDRV0CTRL & High-Level Description
This module configures the GateDrive0 connected with SPI channel CSIH2. It also does the diagnostics for GateDrive0 using SPI interface.
It also performs phase reasonable diagnostics when the inverter 0 fault input is active. Detects FET fault and indicates the type of fault and also in the case of single fet fault it indicates the phase faulted as well. Phase reasonableness is disabled on a phase with shorted FET
Design details of software module
Graphical representation of GATEDRV0CTRL
Variable Data Dictionary
User defined typedef definition/declaration
| Typedef Name | Element Name | User Defined Type | Legal Range (min) | Legal Range (max) |
| GateDrvCfgSt | - | Enumeration | 0 | 4 |
Variable definition for enumerated types
| Enum Name | Element Name | Value |
| GateDrvCfgSt | GATEDRVCFGST_RSTGATEDRVST | 0 |
| GATEDRVCFGST_WAIT2MS | 1 | |
| GATEDRVCFGST_CFGREG | 2 | |
| GATEDRVCFGST_SETUPSPIREGREAD | 3 | |
| GATEDRVCFGST_READBACKREGS | 4 |
Constant Data Dictionary
Program(fixed) Constants
Embedded Constants
Local
| Constant Name | Resolution | Units | Value |
| GATEDRVOFFSTCHKSIZE_CNT_U08 | 1U | Cnt | ((TblSize_m(ELECGLBPRM_GATEDRVOFFSTCHKDATA_CNT_U16)/8U) - 1U) |
| BITMASK0_CNT_U08 | 1 | Cnt | 0x01U |
| BITMASK2_CNT_U08 | 1 | Cnt | 0x04U |
| BITMASK4_CNT_U08 | 1 | Cnt | 0x10U |
| MOTDRVERRMIN_NANOSEC_F32 | Single precision float | NanoSec | 0.0F |
| MOTDRVERRMAX_NANOSEC_F32 | Single precision float | NanoSec | 40000000.0F |
| DIAG2REGBOOTSTRPSPLYFLTSTRTPOS_CNT_U08 | 1 | Cnt | 5U |
Global
| Constant Name |
| Refer to the FDD |
Module specific Lookup Tables Constants
| Constant Name | Resolution | Value | Software Segment |
| Refer to the design |
Software Module Implementation
Sub-Module Functions
None
Initialization Functions
Per: GateDrv0CtrlInit1
PERIODIC FUNCTIONS
Per: GateDrv0CtrlPer1
Design Rationale
None
Processing of Function
See design model for details.
Per: GateDrv0CtrlPer2
Design Rationale
It is the intent of this design to hold the value of
MotDrvr0IninTestCmpl between iterations of GateDrv0CtrlPer2.
There was an inexplicable model issue in which MotDrvr0IninTestCmpl
was being reset to 0 when MotDrvr0IninTestCmpl was not being
written in the IF branch of model (refer model notes)
Implementation Considerations:
No need to use a PIM or a static variable as this signal is an RTE
output. Since RTE signals work like a static variable, the
implementation always holds the last value.
Processing of Function
See design model for details.
Interrupt Functions
None
Serial Communication Functions
None
Local Function/Macro Definitions
Local Function #1
| Function Name | SpiAsyncTx | Type | Min | Max |
| Arguments Passed | Channel_Cnt_T_u08 | Spi_ChannelType | 0 | Full |
| TxData_Cnt_T_u16 | Spi_DataType | 0 | Full | |
| Sequence_Cnt_T_u08 | Spi_SequenceType | 0 | Full | |
| Return Value | None |
Description
(void) Spi_WriteIB( Channel_Cnt_T_u08, &TxData_Cnt_T_u16 );
(void) Call_Spi_AsyncTransmit( Sequence_Cnt_T_u08 );
Local Function #2
| Function Name | OffStVrfySt | Type | Min | Max |
| Arguments Passed | None | |||
| Return Value | None |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/OffState Verification Stateblock in design model.
Local Function #3
| Function Name | OffStVrfyData | Type | Min | Max |
| Arguments Passed | None | |||
| Return Value | Flt_Cnt_T_logl | Boolean | FALSE | TRUE |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/OffState Verification State/OffSt Verification Chk and Transition to Config State/OffStChk Incomplete/Offstate Verification /OffState Verification Check block in design model.
*It is optimized in the implementation to reduce the high static path count.
Local Function #4
| Function Name | CfgSt | Type | Min | Max |
| Arguments Passed | None | |||
| Return Value | None |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Configuration State block in design model.
The state machine is implemented slightly differently in code vs the model, but they are functionally equivalent.
The model adds 1 to the GateDrv0CfgCnt Pim to change to the next state in Configuration,but the code assigns values from a local enumeration (see section 5.2) instead of performing arithmetic on the Pim. The enumerated state assigned to GateDrv0CfgCnt Pim will match with the resulting state in the model.
Local Function #5
| Function Name | ReadBackRegs | Type | Min | Max |
| Arguments Passed | None | |||
| Return Value | None |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Configuration State/Read back Registers block in design model.
Local Function #6
| Function Name | OperFltMonrSt | Type | Min | Max |
| Arguments Passed | PhaOnTiMeasdA_NanoSec_T_u32 | Uint32 | 0 | 4294967295 |
| PhaOnTiMeasdB_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| PhaOnTiMeasdC_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| PhaOnTiSumAExp_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| PhaOnTiSumBExp_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| PhaOnTiSumCExp_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| *MotDrvErrA_NanoSec_T_f32 | Single precision float | 0.0F | 40000000.0F | |
| *MotDrvErrB_NanoSec_T_f32 | Single precision float | 0.0F | 40000000.0F | |
| *MotDrvErrC_NanoSec_T_f32 | Single precision float | 0.0F | 40000000.0F | |
| Return Value | None |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State block in design model.
Local Function #7
| Function Name | GateDrvDetermineOnStSngFETFlt | Type | Min | Max |
| Arguments Passed | *SpclSnpshtData0_Cnt_T_u32 | Uint32 | 0U | 4294967295U |
| *SpclSnpshtData1_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| *SpclSnpshtData2_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| Return Value | GenGateDrvFlt_Cnt_T_logl | Boolean | FALSE | TRUE |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/Status Register indicates Fault/Determine OnState Single FET Fault block in design model.
Local Function #8
| Function Name | GateDrvDetermineVltgFlt | Type | Min | Max |
| Arguments Passed | *SpclSnpshtData0_Cnt_T_u32 | Uint32 | 0U | 4294967295U |
| *SpclSnpshtData1_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| *SpclSnpshtData2_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| Return Value | GenGateDrvFlt_Cnt_T_logl | Boolean | FALSE | TRUE |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/Status Register indicates Fault/Determine VREG/Bootstrap Voltage Fault block in design model.
Local Function #9
| Function Name | GateDrvDetermineGenericFlt | Type | Min | Max |
| Arguments Passed | GateDrvAllSts_Cnt_T_u16 | Uint16 | 0 | 0xFFFF |
| *SpclSnpshtData0_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| *SpclSnpshtData1_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| *SpclSnpshtData2_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| Return Value | GenGateDrvFlt_Cnt_T_logl | Boolean | FALSE | TRUE |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/Status Register indicates Fault/Determine Generic Gate Drive Fault block in design model.
Local Function #10
| Function Name | SetNtcStInfo | Type | Min | Max |
| Arguments Passed | PhaOnTiMeasd_NanoSec_T_u32 | Uint32 | 0 | 4294967295 |
| PhaOnTiSumExp_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| AbsltErr_NanoSec_T_f32 | Single precision float | 0 | 3.4E+38 | |
| BitMask_Cnt_u08 | Uint8 | 0 | 127 | |
| NtcStInfo_Uls_T_u08 | Uint8 | 0 | 255 | |
| Return Value | Flt_Uls_T_lgc | Boolean | False | True |
Description
See ES311A_GateDrv0Ctrl/GateDrv0Ctrl/GateDrv0CtrlPer2/GateDrv Enable/Disable/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/No Faults/GateDrvPhaReasbnChk/MeasdPhaFltChkABC block in design model. This function implements NtcStInfoPhaA, NtcStInfoPhaB and NtcStInfoPhaC common functionality.
Local Function #11
| Function Name | ChkResVrfyRegs | Type | Min | Max |
| Arguments Passed | PrmByte_Cnt_T_u08 | Uint8 | 128 | 138 |
| Return Value | None | - | - | - |
Description
Check Results of Verify GateDrive0 Registers based on calculated parameter byte and take appropriate action
Local Function #12
| Function Name | WriteOutput | Type | Min | Max |
| Arguments Passed | None | - | - | - |
| Return Value | None | - | - | - |
Description
Implements the ‘ES311A_GateDrv0Ctrl_new/GateDrv0Ctrl/GateDrv0CtrlPer2/Write Output’ block in simulink model.
GLObAL Function/Macro Definitions
None
Known Limitations With Design
Note: The PIM Ivtr0InactvSts is written in Per2 and used in Per1 as well as Per2. Data consistency is not an issue because of explicit scheduling requirements given in the integration manual.
Note:
At multiple places, the implementation does not reset the error counter PIM when rollover to zero happens but the model does. This is because in the code the rollover is automatic (and marked intentional ), whereas in the model it isn’t that way and requires a manual reset.
In all the cases where (1) is applicable, the model comments say 65535 rather than 4294967295 as the value at which reset should occur. Upon discussion with FDD owner, the comment is wrong and will be changed with the next update.
UNIT TEST CONSIDERATION
Overflow is intentional and acceptable on PhaOnTiSumAExp_NanoSec_T_u32, PhaOnTiSumBExp_NanoSec_T_u32 and PhaOnTiSumCExp_NanoSec_T_u32 in Per2 function.
Rollover is intentional on Rte_Pim_GateDrv0SpiTrsmErrCntr. The code has comments that also mention this consideration.
Note: While the code and model do not exactly match on the implementation (because the model manually resets this error counter, while the code lets it auto-reset due to rollover), the output should be the same for the PIM because functionally they are same.The model is designed such that the table ELECGLBPRM_GATEDRVOFFSTCHKDATA_CNT_U16 is never indexed with a value of greater than its size in real life. However, in code we need an explicit check for safety. For this reason, when Rte_Pim_GateDrv0OffStChkIdx is given a value greater than or equal to the size of this table, the model and code will behave differently (this is expected , because it is an impossible scenario in the real world).
->
For PIL testing, the consideration is that the input values given to Rte_Pim_GateDrv0OffStChkIdx when MIL vectors are not available should be less than or equal to (GATEDRVOFFSTCHKSIZE_CNT_U08).This component has a config parameter. Use the file from local/include folder and NOT the one from local/generate folder for testing so that Tessy can vary the value of the configuration parameter in the range that it is given in the data dictionary.
Please rectify wrong expected values of tests as part of anomaly corrective action. See PDF attached here (refer to both root cause and corrective action).
3 - GateDrv0Ctrl_PeerReviewChecklist
Overview
Summary SheetSynergy Project
Davinci Files
Source Code
PolySpace
help
Version History
Sheet 1: Summary Sheet
| Rev 2.01 | 21-Feb-18 | |||||||||||||||||||||||||||||
| Nexteer EA4 SWC Implementation Peer Review Summary Sheet | ||||||||||||||||||||||||||||||
| Component Short Name: | GateDrv0Ctrl | Revision / Baseline: | ES311A_GateDrv0Ctrl_Impl_3.2.0 | |||||||||||||||||||||||||||
| Change Owner: | Shruthi Raghavan | Work CR ID: | EA4#20591, EA4#20770 | |||||||||||||||||||||||||||
| Modified File Types: | ||||||||||||||||||||||||||||||
| Check the file types that needed modification for the Work CR(s); macros for the check boxes will populate the appropriate checklist tabs for the review. | ||||||||||||||||||||||||||||||
| Review Checklist Summary: | ||||||||||||||||||||||||||||||
| Reviewed: | ||||||||||||||||||||||||||||||
| At start of review, all items below should be marked "No". At the end of the review, all items should be marked "Yes" or "N/A" where N/A indicates the reviewers have reviewed the existing (unchanged) item and confirmed no updates were needed for the Work CR(s). | ||||||||||||||||||||||||||||||
| N/A | MDD | Yes | Source Code | Yes | PolySpace | |||||||||||||||||||||||||
| N/A | Integration Manual | Yes | Davinci Files | |||||||||||||||||||||||||||
| All required reviewers participated | Yes | |||||||||||||||||||||||||||||
| Comments: | ||||||||||||||||||||||||||||||
| Time spent ( to the nearest half hour) | review preparation | review meeting | review follow-up | |||||||||||||||||||||||||||
| Change owner: | 0.5 | 0.75 | 0.5 | |||||||||||||||||||||||||||
| Component developer reviewers: | 0 | 0.75 | 0.5 | 3 | ||||||||||||||||||||||||||
| Other reviewers: | 0 | 1 | 0.5 | |||||||||||||||||||||||||||
| Total hours | 0.5 | 2.5 | 1.5 | 4.5 | ||||||||||||||||||||||||||
| Content reviewed | ||||||||||||||||||||||||||||||
| Lines of code: | 4 | Elements of .arxml content: | 3 | Pages of documentation: | 0 | |||||||||||||||||||||||||
| General Guidelines: - The reviews shall be performed over the portions of the component that were modified as a result of the Change Request. - New components should include SWC Owner and/or SWC Design author and Integrator and/or SW Lead as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files) - Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed. - To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file. - .h file should be reviewed with the source file as part of the source file. Each peer review shall start with a clean copy of the latest peer review checklist template. Save in the doc folder of the component implementation, with the file name in the format SWCShortName_Review.xlsx. If the existing review in Synergy has a different name, the name must be changed IN SYNERGY (rather than by syncing in a new file with the new name) so that the file history will be properly maintained. Before the peer review, the change owner shall: (NOTE - time for completing these items is to be counted as the Change Owner Review Prep Time) o Review the previous component peer review and copy any relevant comments to the new review sheet. o Review all checklist items and make all corrections needed, so that the component is ready for peer review. The expectation is that peer review should find very few issues, because the change owner has already used the checklist to ensure the component changes are complete and correct. o Fill in all file name and version information as needed on peer review checklist tabs (file names may be copied from the previous peer review where appropriate) o Fill in checklist answers (Yes/No/NA pulldowns) ONLY on those items which are NA for the current change. All other checklist items should be blank going into the review meeting. During the peer review meeting: o For each page of the review, first review the items already marked as N/A for this change, to confirm that reviewers agree with this assessment; change the checklist box to blank if it is found that the item does apply. o Then review the items with the checklist box blank. After reviewing each of these items, the checklist box will be marked as "Yes", or the checklist box will be marked as "No" with needed rework indicated or with rationale indicated. o If any items are marked "No" with rationale indicated, this must be approved by a software supervisor or the software manager; there is a line in the "Review Board" section of each tab to indicate who approved the "No" items on that tab. | ||||||||||||||||||||||||||||||
Sheet 2: Synergy Project
| Rev 2.01 | 21-Feb-18 | |||||||||||||||||||||||
| Peer Review Meeting Log (Component Synergy Project Review) | ||||||||||||||||||||||||
| Quality Check Items: | ||||||||||||||||||||||||
| Rationale is required for all answers of No | ||||||||||||||||||||||||
| New baseline version name from Summary Sheet follows | Yes | Comments: | ||||||||||||||||||||||
| naming convention | ||||||||||||||||||||||||
| Project contains necessary subprojects | Yes | Comments: | ||||||||||||||||||||||
| Project contains the correct version of subprojects | Yes | Comments: | ||||||||||||||||||||||
| Design subproject is correct version | Yes | Comments: | ||||||||||||||||||||||
| .gpj file in tools folder matches .gpj generated by TL109 script | Yes | Comments: | ||||||||||||||||||||||
| File/folder structure is correct per documentation in | Yes | Comments: | ||||||||||||||||||||||
| TL109A_SwcSuprt | ||||||||||||||||||||||||
| General Notes / Comments: | ||||||||||||||||||||||||
| Add TL105 subproject : Done 2/28/2018 | ||||||||||||||||||||||||
| Review Board: | ||||||||||||||||||||||||
| Change Owner: | Shruthi Raghavan | Review Date : | 02/28/18 | |||||||||||||||||||||
| Lead Peer Reviewer: | Avinash James | Approved by Reviewer(s): | Yes | |||||||||||||||||||||
| Other Reviewer(s): | Steven Horwath | |||||||||||||||||||||||
| Rationale/justification for items marked "No" approved by: | ||||||||||||||||||||||||
Sheet 3: Davinci Files
| Rev 2.01 | 21-Feb-18 | ||||||||||||||||||||||||
| Nexteer SWC Implementation Peer Review Meeting Log (Davinci Review) | |||||||||||||||||||||||||
| Quality Check Items: | |||||||||||||||||||||||||
| Rationale is required for all answers of No | |||||||||||||||||||||||||
| Only StdDef Port interfaces and datatypes are used | N/A | Comments: | |||||||||||||||||||||||
| (compare against TL107B to ensure only implementation | |||||||||||||||||||||||||
| data types are used) | |||||||||||||||||||||||||
| OBSOLETE/OBSELETE doesn’t appear in any arxml file | N/A | Comments: | |||||||||||||||||||||||
| Do all port interface names end in PortIf and a sequence | N/A | Comments: | |||||||||||||||||||||||
| number | |||||||||||||||||||||||||
| Non-program-specific components saved | Yes | Comments: | |||||||||||||||||||||||
| in Autosar 4.0.3 format | |||||||||||||||||||||||||
| For components with generated configurable content: | N/A | Comments: | |||||||||||||||||||||||
| *Cfg.arxml.TT: Verfied Davinci Configurator imported the | |||||||||||||||||||||||||
| change correctly | |||||||||||||||||||||||||
| *Cfg.h.TT: Verfied Davinci Configurator generates | N/A | Comments: | |||||||||||||||||||||||
| the configuration header file(s) correctly | |||||||||||||||||||||||||
| All changed files have been compared against previous | Yes | Comments: | |||||||||||||||||||||||
| versions (If available) and changes match changes | |||||||||||||||||||||||||
| needed as described by the work CR(s), all parent CRs | |||||||||||||||||||||||||
| and parent anomalies, and the SWC Design change log. | |||||||||||||||||||||||||
| Davinci files accurately implement SWC Design (DataDict.m | Yes | Comments: | |||||||||||||||||||||||
| file) in all areas where arxml was changed and/or the | |||||||||||||||||||||||||
| DataDict.m file was changed as shown by | |||||||||||||||||||||||||
| comparing the DataDict.m from the current SWC Design | |||||||||||||||||||||||||
| with the DataDict.m used in the previous implementation. | |||||||||||||||||||||||||
| (This is NOT always the predecessor.) | |||||||||||||||||||||||||
Automated validation check is performed with no issues found | Yes | Comments: | |||||||||||||||||||||||
| Naming conventions followed. All names should | Yes | Comments: | |||||||||||||||||||||||
| match DataDict.m | |||||||||||||||||||||||||
| Sender/Receiver port properties match DataDict.m file | N/A | Comments: | |||||||||||||||||||||||
| (name, data type, direction) | |||||||||||||||||||||||||
| Calibration port properties match DataDict.m file | N/A | Comments: | |||||||||||||||||||||||
| (name, data type) | |||||||||||||||||||||||||
| Sender/Receiver port initialization values match | N/A | Comments: | |||||||||||||||||||||||
| DataDict.m file and have been converted to counts | |||||||||||||||||||||||||
| for fixed point types | |||||||||||||||||||||||||
| Calibration port initialization values match | N/A | Comments: | |||||||||||||||||||||||
| DataDict.m file and have been converted to counts | |||||||||||||||||||||||||
| for fixed point types | |||||||||||||||||||||||||
| Mapping set and all unused items have been | N/A | Comments: | |||||||||||||||||||||||
| removed | |||||||||||||||||||||||||
| All sender/receiver port read/writes using "Write (explicit)" | N/A | Comments: | |||||||||||||||||||||||
| and "Read (explicit by argument)"(List justification if not) | |||||||||||||||||||||||||
| Runnable calling frequencies match DataDict.m file | N/A | Comments: | |||||||||||||||||||||||
| Runnable port access matches the DataDict.m file | N/A | Comments: | |||||||||||||||||||||||
| DataDict.m display variables: created as | Yes | Comments: | |||||||||||||||||||||||
| PerInstanceMemory. Name and data type match DataDict.m file. | |||||||||||||||||||||||||
| Per Instance Memory names and data types | N/A | Comments: | |||||||||||||||||||||||
| match DataDict.m file | |||||||||||||||||||||||||
| NVM blocks match DataDict.m file | N/A | Comments: | |||||||||||||||||||||||
| (Named per naming convention. Default block | |||||||||||||||||||||||||
| used if specified in DataDict.m file. Data type | |||||||||||||||||||||||||
| matches DatatDict.m file) | |||||||||||||||||||||||||
| Component is correct component type | N/A | Comments: | |||||||||||||||||||||||
| No change | |||||||||||||||||||||||||
| General Notes / Comments: | |||||||||||||||||||||||||
| Review Board: | |||||||||||||||||||||||||
| Change Owner: | Shruthi Raghavan | Review Date : | 02/28/18 | Component Type : | Application | ||||||||||||||||||||
| Lead Peer Reviewer: | Avinash James | Approved by Reviewer(s): | Yes | ||||||||||||||||||||||
| Integrator and or SW lead: | Hari Mattupalli | Comments: | |||||||||||||||||||||||
| Other Reviewer(s): | Gerald Mccann | ||||||||||||||||||||||||
| Steven Horwath | |||||||||||||||||||||||||
| Rationale/justification for items marked "No" approved by: | |||||||||||||||||||||||||
Sheet 4: Source Code
| Rev 2.01 | 21-Feb-18 | |||||||||||||||||||||||
| Nexteer SWC Implementation Peer Review Meeting Log (Source Code Review) | ||||||||||||||||||||||||
| Source File Name: | GateDrv0Ctrl.c | Source File Revision: | 12 | |||||||||||||||||||||
| Header File Name: | GateDrv0Ctrl_Cfg_private.h.tt | Header File Revision: | ||||||||||||||||||||||
| MDD Name: | GateDrv0Ctrl_MDD.doc | Revision: | 9 | |||||||||||||||||||||
| SWC Design Name: | ES311A_GateDrv0Ctrl_Design | Revision: | 3.4.0 | |||||||||||||||||||||
| Quality Check Items: | ||||||||||||||||||||||||
| Rationale is required for all answers of No | ||||||||||||||||||||||||
| EA4 Common Naming Convention followed: | Version: 1.01 | |||||||||||||||||||||||
| EA4 Software Naming Convention followed: | Version: 1.02 | |||||||||||||||||||||||
| for variable names | Yes | Comments: | ||||||||||||||||||||||
| for constant names | N/A | Comments: | ||||||||||||||||||||||
| for function names | N/A | Comments: | ||||||||||||||||||||||
| for other names (component, memory | N/A | Comments: | ||||||||||||||||||||||
| mapping handles, typedefs, etc.) | ||||||||||||||||||||||||
| Verified no possibility of uninitialized variables being | N/A | Comments: | ||||||||||||||||||||||
| written to component outputs or IRVs | ||||||||||||||||||||||||
| Any requirements traceability tags have been removed | N/A | Comments: | ||||||||||||||||||||||
| from at least the changed areas of code | ||||||||||||||||||||||||
| All variables are declared at the function level. | N/A | Comments: | ||||||||||||||||||||||
| Synergy version matches change history | Yes | Comments: | ||||||||||||||||||||||
| and Version Control version in file comment block | ||||||||||||||||||||||||
| Change log contains detailed description of changes | Yes | Comments: | ||||||||||||||||||||||
| (including any anomaly number(s) being fixed) and | ||||||||||||||||||||||||
| Work CR number | ||||||||||||||||||||||||
| Code accurately implements SWC Design (Document | Yes | Comments: | ||||||||||||||||||||||
| or Model) in all areas where code was changed and/or | ||||||||||||||||||||||||
| Simulink model was color-coded as changed and/or | ||||||||||||||||||||||||
| mentioned in SWC Design change log. | ||||||||||||||||||||||||
| Code comparison against previous version matches | Yes | Comments: | ||||||||||||||||||||||
| changes needed as described by the work CR(s), all | ||||||||||||||||||||||||
| parent CRs and parent anomalies, and the SWC | ||||||||||||||||||||||||
| Design change log. | ||||||||||||||||||||||||
| Verified no Compiler Errors or Warnings | Yes | Comments: | ||||||||||||||||||||||
| (and verified for all possible combinations | ||||||||||||||||||||||||
| of any conditionally compiled code) | ||||||||||||||||||||||||
| Component.h is included | N/A | Comments: | ||||||||||||||||||||||
| All other includes are actually needed. (System includes | N/A | Comments: | ||||||||||||||||||||||
| only allowed in Nexteer library components) | ||||||||||||||||||||||||
| Software Design and Coding Standards followed: | Version: 2.01 | |||||||||||||||||||||||
| Code comments are clear, correct, and adequate | N/A | Comments: | ||||||||||||||||||||||
| and have been updated for the change: [N40] and | ||||||||||||||||||||||||
| all other rules in the same section as rule [N40], | ||||||||||||||||||||||||
| plus [N75], [N12], [N23], [N33], [N37], [N38], | ||||||||||||||||||||||||
| [N48], [N54], [N77], [N79], [N72] | ||||||||||||||||||||||||
| Source file (.c and .h) comment blocks are per | Yes | Comments: | ||||||||||||||||||||||
| standards and contain correct information: [N41], [N42] | ||||||||||||||||||||||||
| Function comment blocks are per standards and | N/A | Comments: | ||||||||||||||||||||||
| contain correct information: [N43] | ||||||||||||||||||||||||
| Code formatting (indentation, placement of | Yes | Comments: | ||||||||||||||||||||||
| braces, etc.) is per standards: [N5], [N55], [N56], | ||||||||||||||||||||||||
| [N57], [N58], [N59] | ||||||||||||||||||||||||
| Embedded constants used per standards; no | N/A | Comments: | ||||||||||||||||||||||
| "magic numbers": [N12] | ||||||||||||||||||||||||
| Memory mapping for non-RTE code | N/A | Comments: | ||||||||||||||||||||||
| is per standard | ||||||||||||||||||||||||
| All access of motor control loop data uses macros | N/A | Comments: | ||||||||||||||||||||||
| generated by the motor control manager | ||||||||||||||||||||||||
| All loops have termination conditions that ensure | N/A | Comments: | ||||||||||||||||||||||
| finite loop iterations: [N63] | ||||||||||||||||||||||||
| All divides protect against divide by zero | N/A | Comments: | ||||||||||||||||||||||
| if needed: [N65] | ||||||||||||||||||||||||
| All integer division and modulus operations | N/A | Comments: | ||||||||||||||||||||||
| handle negative numbers correctly: [N76] | ||||||||||||||||||||||||
| All typecasting and fixed point arithmetic, | N/A | Comments: | ||||||||||||||||||||||
| including all use of fixed point macros and | ||||||||||||||||||||||||
| timer functions, is correct and has no possibility | ||||||||||||||||||||||||
| of unintended overflow or underflow: [N66] | ||||||||||||||||||||||||
| All float-to-unsigned conversions ensure the. | N/A | Comments: | ||||||||||||||||||||||
| float value is non-negative: [N67] | ||||||||||||||||||||||||
| All conversions between signed and unsigned | N/A | Comments: | ||||||||||||||||||||||
| types handle msb==1 as intended: [N78] | ||||||||||||||||||||||||
| All pointer dereferencing protects against | N/A | Comments: | ||||||||||||||||||||||
| null pointer if needed: [N70] | ||||||||||||||||||||||||
| Component outputs are limited to the legal range | N/A | Comments: | ||||||||||||||||||||||
| defined in the SWC Design DataDict.m file : [N53] | ||||||||||||||||||||||||
| All code is mapped with SWC Design (all SWC | N/A | Comments: | ||||||||||||||||||||||
| Design subfunctions and/or model blocks identified | ||||||||||||||||||||||||
| with code comments; all code corresponds to | ||||||||||||||||||||||||
| some SWC Design subfunction and/or model block): | ||||||||||||||||||||||||
| [N40] | ||||||||||||||||||||||||
| Any other violations of design and coding | N/A | Comments: | ||||||||||||||||||||||
| standards noticed during the review are noted in the | ||||||||||||||||||||||||
| comments section for rework. | ||||||||||||||||||||||||
| Anomaly or Design Work CR created | No | Comments: List Anomaly or CR numbers | ||||||||||||||||||||||
| for any SWC Design corrections needed | Display variable units do not affect software | |||||||||||||||||||||||
| General Notes / Comments: | ||||||||||||||||||||||||
| Review Board: | ||||||||||||||||||||||||
| Change Owner: | Shruthi Raghavan | Review Date : | 02/28/18 | |||||||||||||||||||||
| Lead Peer Reviewer: | Avinash James | Approved by Reviewer(s): | Yes | |||||||||||||||||||||
| SWC owner and/or SWC Design author: | Gerald Mccann | Comments: | ||||||||||||||||||||||
| Integrator and or SW lead: | Hari Mattupalli | Comments: | ||||||||||||||||||||||
| Unit test co-ordinator: | Comments: | |||||||||||||||||||||||
| Other Reviewer(s): | Steven Horwath | |||||||||||||||||||||||
| Rationale/justification for items marked "No" approved by: | Steven Horwath | |||||||||||||||||||||||
Sheet 5: PolySpace
| Rev 2.01 | 21-Feb-18 | |||||||||||||||||||||||||
| Nexteer SWC Implementation Peer Review Meeting Log (PolySpace Review) | ||||||||||||||||||||||||||
| Source File Name: | GateDrv0Ctrl.c | Source File Revision: | 12 | |||||||||||||||||||||||
| EA4 Static Analysis Compliance Guideline version: | 1.04 | |||||||||||||||||||||||||
| Poly Space version: | 2013b | TL109A sub project version: | 2.3.0 | |||||||||||||||||||||||
| Quality Check Items: | ||||||||||||||||||||||||||
| Rationale is required for all answers of No | ||||||||||||||||||||||||||
| tools/local folders' header files are appropriate and | N/A | Comments: | ||||||||||||||||||||||||
| function prototypes match the latest component version | generated content only changes | |||||||||||||||||||||||||
| 100% Compliance to the EA4 Static Analysis | Yes | Comments: | ||||||||||||||||||||||||
| Compliance Guideline | ||||||||||||||||||||||||||
| Are previously added justification and deviation | Yes | Comments: | ||||||||||||||||||||||||
| comments still appropriate | changed 13.7 comment | |||||||||||||||||||||||||
| Do all MISRA deviation comments use approved | Yes | Comments: | ||||||||||||||||||||||||
| deviation tags | ||||||||||||||||||||||||||
| For any component source files (.c, .h, generated Cfg.c and Cfg.h) | Yes | Comments: | ||||||||||||||||||||||||
| with conditional compilation, has Polyspace been run with all | Archived results are with config param set to TRUE | |||||||||||||||||||||||||
| combinations of build constants that can be used together in a build? | ||||||||||||||||||||||||||
| (Note which conditional compilation results have been archived) | ||||||||||||||||||||||||||
| Codemetrics count OK | Yes | Comments: | ||||||||||||||||||||||||
| for all functions in the component per Design | ||||||||||||||||||||||||||
| and Coding Standards rule [N47] | ||||||||||||||||||||||||||
| General Notes / Comments: | ||||||||||||||||||||||||||
| Run the Polyspace with config param set to FALSE. : Ran Polyspace with config param as variable in [0,1] range :Done 3/1/2018 | ||||||||||||||||||||||||||
| Deviation Comment for 13.7 has default explanation - change to the explanation relevant to ES311A : Done 2/27/2018 | ||||||||||||||||||||||||||
| 13.7 MISRA violation is reviewed and is OK. Static analysis is run with the config param set up as a variable to verify that the 13.7 violation did not occur. | ||||||||||||||||||||||||||
| Data Flow orange checks and MISRA Rule 9.1 deviations are caused by Polyspace unable to get the range of values returned by address from client calls. | ||||||||||||||||||||||||||
| Overflow warnings are in filter library because Polyspace considers full range for library function arguments. Its not a ES311A code issue | ||||||||||||||||||||||||||
| Pim GateDrv0OffStChkIdx range is [0,255] in the m file but is checked to be <= (size-1) of ELECGLBPRM_GATEDRVOFFSTCHKDATA_CNT_U16 in OffStVrfySt function. So the out of bounds array access issue reported by Polyspace will never actually occur | ||||||||||||||||||||||||||
| Cyclomatic complexity of 17 is because of the SinCos_f32 function. This code has max cyclomatic complexity of 14 only. | ||||||||||||||||||||||||||
| Review Board: | ||||||||||||||||||||||||||
| Change Owner: | Shruthi Raghavan | Review Date : | 03/01/18 | |||||||||||||||||||||||
| Lead Peer Reviewer: | Avinash James | Approved by Reviewer(s): | Yes | |||||||||||||||||||||||
| Other Reviewer(s): | Steven Horwath | Anu K | ||||||||||||||||||||||||
| Rationale/justification for items marked "No" approved by: | ||||||||||||||||||||||||||
Sheet 6: help
| Summary sheet: | |||||||||||||||
Intended Use: Identify which component is being reviewed. This should match the component short name from the DataDict.m fileand the middle part of the Synergy project name, e.g. Assi for the SF001A_Assi_Impl Synergy project | |||||||||||||||
Intended Use: Identify the implementation baseline name intended to be used for the changed component when changes are approved E.g. SF001A_Assi_Impl_1.2.0 | |||||||||||||||
Intended Use: Identify the developer who made the change(s) being reviewed | |||||||||||||||
Intended Use: Identify the Implementation Work CR whose work is being reviewed (may be more than one) | |||||||||||||||
Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. | |||||||||||||||
| Source code: | |||||||||||||||
| This item includes looking at all layers of Simulink model for possible color coding not reflected at a higher level, and includes looking at any intermediate SWC Design versions between the version being implemented and the version that was included as a subproject in the previous implementation. | |||||||||||||||
| Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) | |||||||||||||||
| Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) | |||||||||||||||
| Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) | |||||||||||||||
| Intended Use: For SWC Designs, list the Synergy baseline number (just the number part of the Synergy baseline name) of the SWC Design baseline being implemented. E.g., for SF001A_Assi_Design_1.3.1, this field would say "1.3.1" | |||||||||||||||
| Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). | |||||||||||||||
| Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). | |||||||||||||||
| Intended Use: list version/revision of latest released Software Design and Coding Standards document. | |||||||||||||||
| Davinci Files | |||||||||||||||
| Intended Use: Identify if previous version was compared and only the expected change(s) was present. This is for text files only, not binary or GUIs | |||||||||||||||
| Polyspace | |||||||||||||||
| eg. 2013b | |||||||||||||||
| Integration manual | |||||||||||||||
| Intended Use: Identify which file is being reviewed | |||||||||||||||
| Intended Use: Identify which version of the integration manual has been reviewed. | |||||||||||||||
| Synergy | |||||||||||||||
| Refer to EA4 Common Naming Conventions document, section “Synergy Baseline Names for core components” | |||||||||||||||
| The following subprojects should be included for all component implementations: • AR200A_ArSuprt_Impl • AR201A_ArCplrSuprt_Impl • TL101A_CptRteGen • TL103A_CplrSuprt • TL109A_SwcSuprt • Corresponding _Design project used for the implementation The following subprojects should be included as needed by each component: • AR10xx_Nxtr*_Impl library components as needed by each component • AR202x_MicroCtrlrSuprt_Impl as needed (for register header files for components making direct register access)[add notes about when to add a stub header file] • Xx999x_xxxxGlbPrm_Impl as needed by each component • TL105A_Artt for components with generated content The following should NOT be included as subprojects: • TL107x_DavinciSuprt (aka StdDef) • TL100A_QACSuprt (QAC subproject was previously included but should be removed going forward) • Any other component (not mentioned anywhere above) whose .h file is needed. For these components, a “stub” .h file should be created, containing only the multiple include protection and the definitions and function prototypes actually needed by the component with the #include, and placed in the “including” component’s local\include folder. | |||||||||||||||
| misc in Summary sheet | |||||||||||||||
| (integrator, designer, unit test coordinator, etc.) | |||||||||||||||
| For a new component, use number of lines in all source files reviewed, including files in the src and include folders and any generated cfg.h and cfg.c files. For a changed component, try to add up how many lines, including comments and blank lines, were in the changed areas that were reviewed. Not just the actual changed lines, but the number of lines in the blocks of code you had to look at to review the change. | |||||||||||||||
| add up the number of ports, number of PIM variables, number if IRVs, number of runnables, number of NVM blocks in the component (all of them for review of a new component, the new and modified ones for review of a change) | |||||||||||||||
| add the number of pages in the MDD and integration manual for a new component; for a modified component, count the number of pages that contained a change. | |||||||||||||||
| Reviewer | Required attendance for this type of change | Review spreadsheet tab(s) | |||||||||||||
| Component group peer | All | All | |||||||||||||
| Component owner and/or SWC Design author | *Initial creation of any new component *Simulink model changes (any change to the model other than just updating the change log) | Source | |||||||||||||
| Integrator and/or SW lead of first program planning to use the component | *Initial creation of any new component *new or changed NVM blocks, NVM datatypes, or NVM usage (added or removed or changed NVM API calls in any runnable) *Major rev (X changed in the X.Y.X design baseline number; means there was a component interface change) *new or changed config params *all MM component changes | Davinci files, Integration manual, source for NVM changes and for all MM component changes. | |||||||||||||
| Unit test coordinator | Fixes for coverage issues | Source | |||||||||||||
| SQA | None | None | |||||||||||||
For each reviewer category listed on each tab, there should either be • the name of the reviewer who attended or • a comment indicating o why that reviewer was not required for this change or o who approved holding the review without that required reviewer (approval must be from the software manager or a software supervisor) | |||||||||||||||
Sheet 7: Version History
| File Version History | ||||||
| Version | Description | Author(s) | Revision Date | Approved By | Approved Date | Status |
| Draft/ Released | ||||||
| Template Version History | ||||||
| Version | Description | Author(s) | Revision Date | Approved By | Approved Date | Status |
| 1.0 | Initial Version | SW Engineering team | 24-May-15 | NA | NA | Released |
| 1.01 | Changed name to be EA4 specific | SW Engineering team | 25-Jun-15 | NA | NA | Released |
| 1.02 | Modified Summary Sheet General Guidelines, Clarified wording on first item in Synergy project sheet. | SW Engineering team | 30-Jul-15 | NA | NA | Released |
| 1.02 | Made corrections and clarifications to Source Code check list. | SW Engineering team | 30-Jul-15 | NA | NA | Released |
| 1.02 | updated Davinci, MDD, and Polyspace/QAC tabs | SW Engineering team | 30-Jul-15 | NA | NA | Released |
| 1.03 | Aligned to portal version guidelines | Umesh Sambhari | 21-Nov-17 | NA | NA | Released |
| 2.00 | Summary sheet template: Changed title to indicate Implementation Peer Review Corrected and/or clarified mouse hover comments, added instructions, renamed some fields. Changed the default setting to "No" on the items reviewed | SW Engineering team | 29-Nov-17 | Lonnie Newton, Steven Horwath, Kevin Smith, Lucas Wendling, Vinod Shankar | NA | Released |
| Source code template: Removed hyperlink for naming conventions, corrected name of naming conventions document, added version field for naming conventions document. Changed item about requirements tags to reflect that they should be removed Added clarification that all combinations of conditionally compiled code must be checked Item about accurately implementing SWC Design is modified and a new item added, both to clarify where to look when determining needed changes. Added point for version of common naming conventions Reworded multiple items for clarity | SW Engineering team | 29-Nov-17 | ||||
| Synergy project template: added items for file/folder structure added point on .gpj file in tools folder | SW Engineering team | 29-Nov-17 | ||||
| Davinci files template: Clarified the StdDef item Added new item for OBSOLETE Clarified item on datadict.m comparison Removed the references to .m file helper tool Updated to reflect that all component should now use only implementation data types Added points on PIMs and NVMs | SW Engineering team | 29-Nov-17 | ||||
| All template tabs: Added/clarified/removed mouse hover comments. Updated Review Board section Removed the gridlines from all tabs Updated titles to say "Nexteer SWC Implementation Peer Review" Changed all occurences of "FDD" to "SWC Design" | SW Engineering team | 29-Nov-17 | ||||
| 2.01 | Added a help tab and appropriate links Added field on Summary sheet to report hours spent and content reviewed Changed wording in an item in Polyspace tab and Source code tab | SW Engineering team | 21-Feb-18 | Lonnie Newton, Steven Horwath, Kevin Smith, Lucas Wendling, Vinod Shankar | 21-Feb-18 | Released |
