1 - SysFricLrng_IntegrationManual

Integration Manual

For

SysFricLrng

VERSION: 5.0

DATE: 04-Oct-2017

Prepared By:

Matthew Leser

Nexteer Automotive,

Saginaw, MI, USA

Location: The official version of this document is stored in the Nexteer Configuration Management System.

Revision History

Sl. NoDescriptionAuthorVersionDate
1Initial versionBasavaraja Ganeshappa1.030-Mar-2016
2Updated to design version 2.2.0TATA2.005-Dec-16
3Updated to design version 2.4.0KK3.028-Feb-17
4Remove notes for Integrator SettingsKK4.028-Mar-17
5Added new Non Rte Server RunnableML5.004-Oct-17

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

AbbreviationDescription
DFDDesign functional diagram
FDDFunctional Design Document
MDDModule design Document

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.TitleVersion
1MDD GuidelineProcess 4.02.01
2EA4 Software Naming ConventionsProcess 4.02.01
3Software Design and Coding StandardsProcess 4.02.01
4FDD: SF007A_SysFricLrng_DesignSee Synergy sub project version

Dependencies

SWCs

ModuleRequired Feature
None

Global Functions(Non RTE) to be provided to Integration Project

FricLrngShtDwn

Configuration REQUIREMeNTS

Build Time Config

ModulesNotes
None

Configuration Files to be provided by Integration Project

None

Da Vinci Parameter Configuration Changes

ParameterNotesSWC
None

DaVinci Interrupt Configuration Changes

ISR NameVIM #Priority DependencyNotes
None

Manual Configuration Changes

ConstantNotesSWC
None

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer SF007A_SysFricLrng_DataDict.m

Required Global Data Outputs

Refer SF007A_SysFricLrng_DataDict.m

Specific Include Path present

Yes

Runnable Scheduling

This section specifies the required runnable scheduling.

InitScheduling RequirementsTrigger
StOutpCtrlInit1NoneRTE – Init
RunnableScheduling RequirementsTrigger
StOutpCtrlPer1NoneRTE – 10ms
Server RunnableScheduling RequirementsTrigger
ClrFricLrngOperModNoneOn server invocation call
GetFricLrngDataNoneOn server invocation call
GetFricOffsOutpDiNoneOn server invocation call
InitFricLrngTblNoneOn server invocation call
SetFricLrngDataNoneOn server invocation call
SetFricOffsOutpDiNoneOn server invocation call
GetFricDataNoneOn server invocation call
SetFricDataNoneOn server invocation call
FricLrngShtDwn

Non Rte Server Runnable. This should be called before

the Nvm WriteAll and Shutdown.

On server invocation call

Memory Map REQUIREMENTS

Mapping

Memory SectionContentsNotes

Usage

FeatureRAMROM
None

Table 1: ARM Cortex R4 Memory Usage

NvM Blocks

  • Refer Data Dict

Compiler Settings

Preprocessor MACRO

FLTINJENA is used for coditionaly injecting fault

Optimization Settings

None

Appendix

None

2 - SysFricLrng_MDD

Module Design Document

For

SysFricLrng

Oct 04, 2017

Prepared By:

Matthew Leser

Nexteer Automotive,

Saginaw, MI, USA

Change History

DescriptionAuthorVersionDate
Initial VersionBasavaraja Ganeshappa1.024th Mar 2016
Re base lined by pulling 1.3.1Basavaraja Ganeshappa2.025th Jul 2016
Implementation of SF007A v2.0.0 & v2.1.0Krishna Anne3.03rd Oct 2016
Updated to design version 2.2.0TATA4.005-Dec-16
Updated to design version 2.4.0KK5.028-Feb-17
Updated Diagram and added Unit Test ConsiderationML6.004-Oct-17

Table of Contents

1 Introduction 6

1.1 Purpose 6

2 SysFricLrng High-Level Description 7

3 Design details of software module 8

3.1 Graphical representation of SysFricLrng 8

3.2 Data Flow Diagram 9

3.2.1 Component level DFD 9

3.2.2 Function level DFD 9

4 Constant Data Dictionary 10

4.1 Program (fixed) Constants 10

4.1.1 Embedded Constants 10

5 Software Component Implementation 11

5.1 Sub-Module Functions 11

5.1.1 Init: SysFricLrngInit1 11

5.1.1.1 Design Rationale 11

5.1.1.2 Module Outputs 11

5.1.2 Per: SysFricLrngPer1 11

5.1.2.1 Design Rationale 11

5.1.2.2 Store Module Inputs to Local copies 11

5.1.2.3 (Processing of function)……… 11

5.1.2.4 Store Local copy of outputs into Module Outputs 11

5.2 Server Runnables 11

5.2.1 Server Runnable Name 11

5.2.1.1 Design Rationale 11

5.2.1.2 (Processing of function)……… 11

5.3 Server Runnables 12

5.3.1 Server Runnable Name 12

5.3.1.1 Design Rationale 12

5.3.1.2 (Processing of function)……… 12

5.3.2 Server Runnable Name 12

5.3.2.1 Design Rationale 12

5.3.2.2 (Processing of function)……… 12

5.3.3 Server Runnable Name 12

5.3.3.1 Design Rationale 12

5.3.3.2 (Processing of function)……… 12

5.3.4 Server Runnable Name 12

5.3.4.1 Design Rationale 12

5.3.4.2 (Processing of function)……… 12

5.3.5 Server Runnable Name 13

5.3.5.1 Design Rationale 13

5.3.5.2 (Processing of function)……… 13

5.3.6 Server Runnable Name 13

5.3.6.2 (Processing of function)……… 13

5.3.7 Server Runnable Name 13

5.3.7.2 (Processing of function)……… 13

5.4 Interrupt Functions 13

5.4.1 Interrupt Function Name 13

5.4.1.1 Design Rationale 13

5.4.1.2 (Processing of the ISR function)….. 13

5.5 Module Internal (Local) Functions 14

5.5.1 Local Function #1 14

5.5.1.1 Design Rationale 14

5.5.1.2 Processing 14

5.5.2 Local Function #2 14

5.5.2.1 Design Rationale 14

5.5.2.2 Processing 14

5.5.3 Local Function #3 15

5.5.3.1 Design Rationale 15

5.5.3.2 Processing 15

5.5.4 Local Function #4 15

5.5.4.1 Design Rationale 15

5.5.4.2 Processing 15

5.5.5 Local Function #5 16

5.5.5.1 Design Rationale 16

5.5.5.2 Processing 16

5.5.6 Local Function #6 16

5.5.6.1 Design Rationale 16

5.5.6.2 Processing 16

5.5.7 Local Function #7 16

5.5.7.1 Design Rationale 17

5.5.7.2 Processing 17

5.5.8 Local Function #8 17

5.5.8.1 Design Rationale 17

5.5.8.2 Processing 17

5.5.8.3 17

5.5.9 Local Function #9 17

5.5.9.1 Design Rationale 18

5.5.9.2 Processing 18

5.5.10 Local Function #10 18

5.5.10.1 Design Rationale 18

5.5.10.2 Processing 18

5.5.11 Local Function #11 18

5.5.11.1 Design Rationale 18

5.5.11.2 Processing 19

5.5.12 Local Function #12 19

5.5.12.1 Design Rationale 19

5.5.12.2 Processing 19

5.6 GLOBAL Function/Macro Definitions 19

6 Known Limitations with Design 20

7 UNIT TEST CONSIDERATION 21

Appendix A Abbreviations and Acronyms 22

Appendix B Glossary 23

Appendix C References 24

Introduction

Purpose

MDD for System Friction Learning

SysFricLrng High-Level Description

Refer FDD

Design details of software module

Refer FDD

Graphical representation of SysFricLrng

Data Flow Diagram

Refer FDD

Component level DFD

Refer FDD

Function level DFD

Refer FDD

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Constant NameResolutionUnitsValue
INDEX0_CNT_U081CNT0U
INDEX1_CNT_U081CNT1U
INDEX2_CNT_U081CNT2U
INDEX3_CNT_U081CNT3U
SYSSATNFRICESTIMDMIN_HWNWMTR_F321HwNwMtr0.0F
SYSSATNFRICESTIMDMAX_HWNWMTR_F32 21HwNwMtr20.0F
SYSFRICESTIMDMIN_HWNWMTR_F321HwNwMtr0.0F
SYSFRICESTIMDMAX_HWNWMTR_F321HwNwMtr20.0F
SYSFRICOFFSMIN_HWNWMTR_F321HwNwMtr-5.0F
SYSFRICOFFSMAX_HWNWMTR_F321HwNwMtr5.0F

For rest of the constants, please refer Data Dictionary

Software Component Implementation

The detailed design of the function is provided in the FDD.

Sub-Module Functions

Init: SysFricLrngInit1

Design Rationale

In MDD, filters are initialized inside the for loop using switch case but in code filters are initialized one by one without any conditions.

In model, filters are initialized twice as it is not possible to use a variable for the filter initialization in the model. This is redundancy is not present in the code as variables are used for initializing the filters.

Module Outputs

Refer FDD

Per: SysFricLrngPer1

Design Rationale

Refer FDD

Store Module Inputs to Local copies

Refer FDD

(Processing of function)………

Refer FDD

Store Local copy of outputs into Module Outputs

Refer FDD

Server Runnables

Server Runnable Name

ClrFricLrngOperMod

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnables

Server Runnable Name

GetFricLrngData

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnable Name

GetFricOffsOutpDi

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnable Name

InitFricLrngTbl

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnable Name

SetFricLrngDatal

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnable Name

SetFricOffsOutpDi

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnable Name

GetFricData

Design Rationale

Refer FDD

To avoid calculating array indexing for updating PIMs Rte_Pim_FricLrngData()->Hys and Rte_Pim_FricLrngData()->RngCntr, performed casting the array argument back to it's actual type (similar to what we do with cal arrays) so we can use normal indexing.

(Processing of function)………

On server invocation call

Server Runnable Name

SetFricData

Design Rationale

Refer FDD

To avoid calculating array indexing for updating from PIMs Rte_Pim_FricLrngData()->Hys and Rte_Pim_FricLrngData()->RngCntr, performed casting the array argument back to it's actual type (similar to what we do with cal arrays) so we can use normal indexing.

(Processing of function)………

On server invocation call

Server Runnable Name

FricLrngShtDwn

Design Rationale

Refer FDD

(Processing of function)………

Interrupt Functions

None

Interrupt Function Name

None

Design Rationale

NA

(Processing of the ISR function)…..

NA

Module Internal (Local) Functions

Local Function #1

Function NameFricLearningTypeMinMax
Arguments PassedSelHwAg_HwDeg_T_f32Float32-1440.01440.0
SelColTq_HwNwtMtr_T_f32Float32-1010
VehSpdIdx_Cnt_T_u16Uint1603
HwVelDir_Cnt_T_u08Uint801
LrngEna_Cnt_T_LoglBooleanFALSETRUE
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘FricLearning’ subsystem in FDD.

Following per instance data is updated.

*Rte_Pim_RawAvrg() (Min:0, Max:20)
Rte_Pim_SatnAvrgFric()[VehSpdIdx_Cnt_T_u16] (Min:0, Max:20)

Also writes the outputs SysFricEstimd and SysSatnFricEstimd

Local Function #2

Function NameRunningAndCalibrationModesTypeMinMax
Arguments Passed*FricOffs_HwNwtMtr_T_f32Float32-5.0+5.0
*LrngEna_Cnt_T_LoglBooleanFALSETRUE
Return ValueNoneNANANA

Design Rationale

Processing

Following PIMs are updated; refer to ‘RunningAndCalibrationModes’ subsystem in the FDD. FricOffs_HwNwtMtr_T_f32 is the output of this function

Rte_Pim_FricLrngData()->FricOffs (Min:-5, Max:5)
*Rte_Pim_RawAvrg() (Min:0, Max:20)
Rte_Pim_SatnAvrgFric()[VehSpdIdx_Cnt_T_u16] (Min:0, Max:20)

Also updates the input argument, *FricOffs_HwNwtMtr_T_f32.

Local Function #3

Function NameRawAvrgCalcTypeMinMax
Arguments PassedVehSpdIdx_Cnt_T_u16Uint1605
DeltaIdxOffsDec_Cnt_T_u16Uint16012
DeltaIdxOffsInc_Cnt_T_u16Uint16013
TotalCounter_Cnt_T_u32Uint32065535
LrngEna_Cnt_T_LoglBooleanFALSETRUE
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘Raw Average Calculation’ subsystem in FDD.

Following per instance data is updated.

*Rte_Pim_RawAvrg() (Min:0, Max:20)
Rte_Pim_SatnAvrgFric()[VehSpdIdx_Cnt_T_u16] (Min:0, Max:20)

Local Function #4

Function NamePhiCalcTypeMinMax
Arguments PassedSelHwAg_HwDeg_T_f32Float32-14401440
Gate_Cnt_T_u16Uint16065535
DeltaIdxOffs_Cnt_T_u16Uint16010
SelColTq_HwNwtMtr_T_f32Float32-1010
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘Raw Average Calculation’ subsystem in FDD.

Following per instance data is updated.

Rte_Pim_FricLrngData()->Hys[DeltaIdxOffs_Cnt_T_u16][Gate_Cnt_T_u16 + 1U] (Min:-127, Max:127)
Rte_Pim_FricLrngData()->Hys[DeltaIdxOffs_Cnt_T_u16][Gate_Cnt_T_u16] (Min:-127, Max:127)

Local Function #5

Function NameRangeCounterManagerTypeMinMax
Arguments PassedDeltaIdxOffs_Cnt_T_u16Uint16010
DeltaIdxOffsDec_Cnt_T_u16Uint16012
DeltaIdxOffsInc_Cnt_T_u16Uint16013
Gate_Cnt_T_u16Uint16065535
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘Range counter manager’ subsystem in FDD.

Following per instance data is updated.

*Rte_Pim_ RngCntrThdExcdd() (Min:0, Max:1)
Rte_Pim_FricLrngData->RngCntr (:,:) (Min:0, Max:65535)

Local Function #6

Function NameNTCSetResetTypeMinMax
Arguments PassedMaxRawAvrgFric_Cnt_T_f32Float32-127254
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘NTC_Pass’ and ‘NTC_Fail’ subsystem in FDD

Sets or resets the NTCNR_0X0A2

Local Function #7

Function NameClearingModeTypeMinMax
Arguments PassednoneNANANA
Return ValuenoneNANANA

Design Rationale

Processing

Refer to ‘Clearing Mode’ subsystem in FDD.

Following per instance data is updated.

*Rte_Pim_FricOffs()(Min:-5, Max:5)

Local Function #8

Function NameResettingModeTypeMinMax
Arguments Passed*FricOffs_HwNwtMtr_T_f32NANANA
Return ValueNoneNANANA

Design Rationale

Processing

Refer to ‘ResettingMode’ subsystem in FDD.

Following per instance data is updated. Also updates the input argument ‘*FricOffs_HwNwtMtr_T_f32’.

Rte_Pim_FricLrngData()->RngCntr(;)
Rte_Pim_AvrgFricLpFilX()->FilSt (X: 1 to 4)
Rte_Pim_FricLrngData()->Hys(;)
Rte_Pim_FricOffs()(Min:-5, Max:5)

Rte_Pim_VehBasLineFric()[] (Min:-0, Max:127)

Rte_Pim_RawAvrgFric()[] (Min:--127, Max:254)

Rte_Pim_FilAvrgFric()[] (Min:--10 , Max: 10)

Rte_Pim_SatnAvrgFric()[](Min:--127, Max:254)

Rte_Pim_FricLrngData()->VehLrndFric[] (0-127)

Local Function #9

Function NameHwAngConstraintTypeMinMax
Arguments PassedFilHwAg_HwDeg_T_f32Float32-14401440
*HwAgOK_Cnt_T_Loglboolean01
*SelHwAg_HwDeg_T_f32Float32-14401440
Return ValueNANANANA

Design Rationale

 IDXSELN2_ULS_U08 is not used in the code because it is not required instead IDXSELN1_ULS_U08 serves the purpose.

Processing

Refer to ‘HwAngConstraint‘ subsystem in FDD. Updates the input arguments, *HwAgOK_Cnt_T_Logl and *SelHwAg_HwDeg_T_f32

Local Function #10

Function NameHwVelConstraintTypeMinMax
Arguments PassedHwVel_HwRadPerSec_T_f32Float32-4242
HwVelOK_Cnt_T_LoglBoolean01
HwVelDir_Cnt_T_u08Uint801
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘HwVelConstraint’ subsystem in FDD.

Local Function #11

Function NameVehSpdConstraintTypeMinMax
Arguments PassedVehSpd_Kph_T_f32Float320511
*VehSpdOK_Cnt_T_LoglBoolean01
*VehSpdIdx_Cnt_T_u16Uint1605
Return ValueNoneNANANA

Design Rationale

Code is optimized due to limitation with the model; hence code completely won’t match the model. There won’t be any impact on the functionality.

In the model as it is not possible to break the for loop until the loop iterator reaches the configured constant threshold value, index corresponding to the position in ‘SysFricLrngVehSpd’ which breaches the conditions mentioned in ‘VehSpdIdxCalcn’ subsystem is calculated by successively adding the index value after multiplying it with either the condition true or false based on whether the vehicle speed value breaches the threshold mentioned in the FDD. In code as it is possible to exit the for loop as soon as a value in ‘VehSpdIdxCalcn’ breaches thresholds as mentioned in FDD, no such successive addition of loop counter is required.

Processing

Refer to ‘VehSpdConstraint’ subsystem in FDD.

Local Function #12

Function NameColTqconstraintTypeMinMax
Arguments PassedFilColTq_HwNwtMtr_T_f32Float32-1010
*SelColTq_HwNwtMtr_T_f32Boolean-1010
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘ColTqconstraint’ subsystem in FDD. Updates the *SelColTq_HwNwtMtr_T_f32.

GLOBAL Function/Macro Definitions

NA

Known Limitations with Design

None

UNIT TEST CONSIDERATION

  1. In model, one based indexing is used but in code 0 based indexing is used.

  2. In the NVM block needs area of Developer tool, the options of "Restore at Startup" and "Store at Shutdown" are disabled as the newer version (3.13.22 SP2) of this tool throws warnings while doing a DCF check.

  3. There will be a source model mismatch that occurs because of a logic change that happened for a PSR. There is limiting that occurs in the new Non Rte Server Runnable. These limits were switched for the PSR but this change was not brought in for the design. An ICR has been submitted to fix the design to match the implementation, EA4#15920.

Abbreviations and Acronyms

Abbreviation or AcronymDescription

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

  • ISO 9000

  • ISO/IEC 12207

  • ISO/IEC 15504

  • Automotive SPICE® Process Reference Model (PRM)

  • Automotive SPICE® Process Assessment Model (PAM)

  • ISO/IEC 15288

  • ISO 26262

  • IEEE Standards

  • SWEBOK

  • PMBOK

  • Existing Nexteer Automotive documentation

TermDefinitionSource
MDDModule Design Document
DFDData Flow Diagram

References

Ref. #TitleVersion
1AUTOSAR Specification of Memory Mapping (Link:AUTOSAR_SWS_MemoryMapping.pdf)Process 4.02.01
2MDD GuidelineProcess 4.02.01
3Software Naming Conventions.doc2.0
4Software Design and Coding Standards.doc2.1
5FDD- SF007A_SysFricLrng_DesignSee Synergy sub project version

3 - SysFricLrng_PeerReviewChecklists


Overview

Summary Sheet
Synergy Project
Source Code
PolySpace
help
Version History


Sheet 1: Summary Sheet
























Rev 2.0121-Feb-18




Nexteer EA4 SWC Implementation Peer Review Summary Sheet

































Component Short Name:



SysFricLrng
Revision / Baseline:


SF007A_SysFricLrng_Impl_3.1.0
































Change Owner:


Matthew Leser
Work CR ID:


EA4#20204


































Modified File Types:






Check the file types that needed modification for the Work CR(s); macros for the check boxes will populate the appropriate checklist tabs for the review.
























































































































































































Review Checklist Summary:





































Reviewed:








At start of review, all items below should be marked "No". At the end of the review, all items should be marked "Yes" or "N/A" where N/A indicates the reviewers have reviewed the existing (unchanged) item and confirmed no updates were needed for the Work CR(s).




























































N/AMDD


YesSource Code


YesPolySpace

















































N/AIntegration Manual


N/ADavinci Files




















































































All required reviewers participated





No





















































Comments:

No other reviews besides Lead Reviewer were present due to timing constraints.










Approved by Steven Horwath - 6/8/2018


































































































Time spent ( to the nearest half hour)








review preparation



review meeting


review follow-up










Change owner:









0.5



0.5


0









Component developer reviewers:









0



0.5


0


1.5





Other reviewers:









0



0


0









Total hours









0.5



1


0


1.5




































Content reviewed





























Lines of code:


7


Elements of .arxml content:




0

Pages of documentation:



0































































































General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include SWC Owner and/or SWC Design author and Integrator and/or SW Lead as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.

Each peer review shall start with a clean copy of the latest peer review checklist template. Save in the doc folder of the component implementation, with the file name in the format SWCShortName_Review.xlsx. If the existing review in Synergy has a different name, the name must be changed IN SYNERGY (rather than by syncing in a new file with the new name) so that the file history will be properly maintained.

Before the peer review, the change owner shall: (NOTE - time for completing these items is to be counted as the Change Owner Review Prep Time)
o Review the previous component peer review and copy any relevant comments to the new review sheet.
o Review all checklist items and make all corrections needed, so that the component is ready for peer review. The expectation is that peer review should find very few issues,
because the change owner has already used the checklist to ensure the component changes are complete and correct.
o Fill in all file name and version information as needed on peer review checklist tabs (file names may be copied from the previous peer review where appropriate)
o Fill in checklist answers (Yes/No/NA pulldowns) ONLY on those items which are NA for the current change. All other checklist items should be blank going into the review
meeting.

During the peer review meeting:
o For each page of the review, first review the items already marked as N/A for this change, to confirm that reviewers agree with this assessment; change the checklist box to
blank if it is found that the item does apply.
o Then review the items with the checklist box blank. After reviewing each of these items, the checklist box will be marked as "Yes", or the checklist box will be marked as
"No" with needed rework indicated or with rationale indicated.
o If any items are marked "No" with rationale indicated, this must be approved by a software supervisor or the software manager; there is a line in the "Review Board" section
of each tab to indicate who approved the "No" items on that tab.





Sheet 2: Synergy Project






















Rev 2.0121-Feb-18

























Peer Review Meeting Log (Component Synergy Project Review)



















































Quality Check Items:




































Rationale is required for all answers of No










New baseline version name from Summary Sheet follows








Yes
Comments:



naming convention





































Project contains necessary subprojects








Yes
Comments:










































Project contains the correct version of subprojects








Yes
Comments:










































Design subproject is correct version








Yes
Comments:












































.gpj file in tools folder matches .gpj generated by TL109 script








Yes
Comments:













































File/folder structure is correct per documentation in









Yes
Comments:




TL109A_SwcSuprt







































General Notes / Comments:
























































Review Board:


























Change Owner:

Matthew Leser


Review Date :

06/04/18
































Lead Peer Reviewer:


Shawn Penning


Approved by Reviewer(s):



Yes































Other Reviewer(s):










































































Rationale/justification for items marked "No" approved by:












































Sheet 3: Source Code






















Rev 2.0121-Feb-18
Nexteer SWC Implementation Peer Review Meeting Log (Source Code Review)

























Source File Name:


SysFricLrng.c

Source File Revision:


10
Header File Name:


SysFricLrng.h

Header File Revision:


2

























MDD Name:


SysFricLrng_MDD.docx
Revision:
6

























SWC Design Name:


SF007A_SysFricLrng_Design
Revision:
3.3.0


























Quality Check Items:



































Rationale is required for all answers of No

































EA4 Common Naming Convention followed:











Version: 01.01.00
























EA4 Software Naming Convention followed:











Version: 01.02.00

























for variable names







Yes
Comments:

















































for constant names







N/A
Comments:

















































for function names







N/A
Comments:

















































for other names (component, memory







N/A
Comments:










mapping handles, typedefs, etc.)




































Verified no possibility of uninitialized variables being








N/A
Comments:









written to component outputs or IRVs





































Any requirements traceability tags have been removed








N/A
Comments:









from at least the changed areas of code





































All variables are declared at the function level.








Yes
Comments:
















































Synergy version matches change history








Yes
Comments:



and Version Control version in file comment block





































Change log contains detailed description of changes








Yes
Comments:



(including any anomaly number(s) being fixed) and













Work CR number














































Code accurately implements SWC Design (Document








Yes
Comments:



or Model) in all areas where code was changed and/or













Simulink model was color-coded as changed and/or






















mentioned in SWC Design change log.













































Code comparison against previous version matches








Yes
Comments:



changes needed as described by the work CR(s), all













parent CRs and parent anomalies, and the SWC






















Design change log.














































Verified no Compiler Errors or Warnings








Yes
Comments:









(and verified for all possible combinations













of any conditionally compiled code)














































Component.h is included








N/A
Comments:
















































All other includes are actually needed. (System includes








N/A
Comments:









only allowed in Nexteer library components)





































Software Design and Coding Standards followed:











Version: 2.1

























Code comments are clear, correct, and adequate







Yes
Comments:










and have been updated for the change: [N40] and













all other rules in the same section as rule [N40],






















plus [N75], [N12], [N23], [N33], [N37], [N38],






















[N48], [N54], [N77], [N79], [N72]














































Source file (.c and .h) comment blocks are per







Yes
Comments:










standards and contain correct information: [N41], [N42]





































Function comment blocks are per standards and







N/A
Comments:










contain correct information: [N43]





































Code formatting (indentation, placement of







Yes
Comments:










braces, etc.) is per standards: [N5], [N55], [N56],













[N57], [N58], [N59]














































Embedded constants used per standards; no







N/A
Comments:










"magic numbers": [N12]





































Memory mapping for non-RTE code







N/A
Comments:










is per standard





































All access of motor control loop data uses macros







N/A
Comments:










generated by the motor control manager





































All loops have termination conditions that ensure







N/A
Comments:










finite loop iterations: [N63]





































All divides protect against divide by zero







N/A
Comments:










if needed: [N65]





































All integer division and modulus operations







N/A
Comments:










handle negative numbers correctly: [N76]





































All typecasting and fixed point arithmetic,







N/A
Comments:










including all use of fixed point macros and













timer functions, is correct and has no possibility






















of unintended overflow or underflow: [N66]














































All float-to-unsigned conversions ensure the.







N/A
Comments:










float value is non-negative: [N67]





































All conversions between signed and unsigned







N/A
Comments:










types handle msb==1 as intended: [N78]





































All pointer dereferencing protects against







N/A
Comments:










null pointer if needed: [N70]





































Component outputs are limited to the legal range







N/A
Comments:










defined in the SWC Design DataDict.m file : [N53]





































All code is mapped with SWC Design (all SWC







Yes
Comments:










Design subfunctions and/or model blocks identified













with code comments; all code corresponds to






















some SWC Design subfunction and/or model block):






















[N40]














































Any other violations of design and coding









N/A
Comments:










standards noticed during the review are noted in the













comments section for rework.













































Anomaly or Design Work CR created








N/A
Comments: List Anomaly or CR numbers









for any SWC Design corrections needed































































General Notes / Comments:

















































































Review Board:


























Change Owner:

Matthew Leser


Review Date :

06/04/18
































Lead Peer Reviewer:


Shawn Penning


Approved by Reviewer(s):



Yes










































































































SWC owner and/or
SWC Design author:









Comments:

See Summary Sheet

















































Integrator and or
SW lead:









Comments:

See Summary Sheet










































































Unit test co-ordinator:











Comments:

See Summary Sheet





















































Other Reviewer(s):









































































Rationale/justification for items marked "No" approved by:





































































Sheet 4: PolySpace






















Rev 2.0121-Feb-18
Nexteer SWC Implementation Peer Review Meeting Log (PolySpace Review)




























Source File Name:


SysFricLrng.c




Source File Revision:


10

Source File Name:

















Source File Revision:





Source File Name:

















Source File Revision:
































EA4 Static Analysis Compliance Guideline version:











01.04.00












Poly Space version:



2013b





TL109A sub project version:

2.5.0



































Quality Check Items:








































Rationale is required for all answers of No





































tools/local folders' header files are appropriate and










Yes
Comments:










function prototypes match the latest component version











































100% Compliance to the EA4 Static Analysis

Yes
Comments:




Compliance Guideline











































Are previously added justification and deviation










Yes
Comments:




comments still appropriate











































Do all MISRA deviation comments use approved










Yes
Comments:




deviation tags











































For any component source files (.c, .h, generated Cfg.c and Cfg.h)












Yes
Comments:




with conditional compilation, has Polyspace been run with all

















combinations of build constants that can be used together in a build?

























(Note which conditional compilation results have been archived)




















































Codemetrics count OK










Yes
Comments:




for all functions in the component per Design
















and Coding Standards rule [N47]










































































































General Notes / Comments:































































Review Board:




























Change Owner:

Matthew Leser




Review Date :

06/04/18


































Lead Peer Reviewer:


Shawn Penning




Approved by Reviewer(s):



Yes

































Other Reviewer(s):


















































































Rationale/justification for items marked "No" approved by:
















































Sheet 5: help

Summary sheet:






Intended Use: Identify which component is being reviewed. This should match the component short name from the DataDict.m fileand the middle part of the Synergy project name, e.g. Assi for the SF001A_Assi_Impl Synergy project







Intended Use: Identify the implementation baseline name intended to be used for the changed component when changes are approved E.g. SF001A_Assi_Impl_1.2.0





Intended Use: Identify the developer who made the change(s) being reviewed




Intended Use: Identify the Implementation Work CR whose work is being reviewed (may be more than one)




Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed.





Source code:





This item includes looking at all layers of Simulink model for possible color coding not reflected at a higher level, and includes looking at any intermediate SWC Design versions between the version being implemented and the version that was included as a subproject in the previous implementation.
Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified
file in the working project)





Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project)



Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project)







Intended Use: For SWC Designs, list the Synergy baseline number (just the number part of the Synergy baseline name) of the SWC Design baseline being implemented. E.g., for SF001A_Assi_Design_1.3.1, this field would say "1.3.1"









Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s).















Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored).













Intended Use: list version/revision of latest released Software Design and Coding Standards document.





Davinci Files





Intended Use: Identify if previous version was compared and only the expected change(s) was present. This is for text files only, not binary or GUIs








Polyspace





eg. 2013b





Integration manual





Intended Use: Identify which file is being reviewed





Intended Use: Identify which version of the integration manual has been reviewed.



Synergy





Refer to EA4 Common Naming Conventions document, section “Synergy Baseline Names for core components”





The following subprojects should be included for all component implementations:
• AR200A_ArSuprt_Impl
• AR201A_ArCplrSuprt_Impl
• TL101A_CptRteGen
• TL103A_CplrSuprt
• TL109A_SwcSuprt
• Corresponding _Design project used for the implementation

The following subprojects should be included as needed by each component:
• AR10xx_Nxtr*_Impl library components as needed by each component
• AR202x_MicroCtrlrSuprt_Impl as needed (for register header files for components making direct register access)[add notes about when to add a stub header file]
• Xx999x_xxxxGlbPrm_Impl as needed by each component
• TL105A_Artt for components with generated content

The following should NOT be included as subprojects:
• TL107x_DavinciSuprt (aka StdDef)
• TL100A_QACSuprt (QAC subproject was previously included but should be removed going forward)
• Any other component (not mentioned anywhere above) whose .h file is needed. For these components, a “stub” .h file should be created, containing only the multiple include protection and the definitions and function prototypes actually needed by the component with the #include, and placed in the “including” component’s local\include folder.

misc in Summary sheet





(integrator, designer, unit test coordinator, etc.)





For a new component, use number of lines in all source files reviewed, including files in the src and include folders and any generated cfg.h and cfg.c files.  For a changed component, try to add up how many lines, including comments and blank lines, were in the changed areas that were reviewed. Not just the actual changed lines, but the number of lines in the blocks of code you had to look at to review the change.
add up the number of ports, number of PIM variables, number if IRVs, number of runnables, number of NVM blocks in the component  (all of them for review of a new component, the new and modified ones for review of a change)
add the number of pages in the MDD and integration manual for a new component; for a modified component, count the number of pages that contained a change.












ReviewerRequired attendance for this type of changeReview spreadsheet tab(s)
Component group peerAllAll
Component owner and/or SWC Design author*Initial creation of any new component
*Simulink model changes (any change to the model other than just updating the change log)
Source
Integrator and/or SW lead of first program planning to use the component*Initial creation of any new component
*new or changed NVM blocks, NVM datatypes, or NVM usage (added or removed or changed NVM API calls in any runnable)
*Major rev (X changed in the X.Y.X design baseline number; means there was a component interface change)
*new or changed config params
*all MM component changes
Davinci files, Integration manual, source for NVM changes and for all MM component changes.
Unit test coordinatorFixes for coverage issuesSource
SQANoneNone








For each reviewer category listed on each tab, there should either be
• the name of the reviewer who attended
or
• a comment indicating
o why that reviewer was not required for this change
or
o who approved holding the review without that required reviewer (approval must
be from the software manager or a software supervisor)


Sheet 6: Version History















File Version History





VersionDescriptionAuthor(s)Revision DateApproved ByApproved DateStatus






Draft/ Released






































































Template Version History





VersionDescriptionAuthor(s)Revision DateApproved ByApproved DateStatus
1.0Initial VersionSW Engineering team24-May-15NANAReleased
1.01Changed name to be EA4 specificSW Engineering team25-Jun-15NANAReleased
1.02Modified Summary Sheet General Guidelines, Clarified wording on first item in Synergy project sheet.SW Engineering team30-Jul-15NANAReleased
1.02Made corrections and clarifications to Source Code check list.SW Engineering team30-Jul-15NANAReleased
1.02updated Davinci, MDD, and Polyspace/QAC tabsSW Engineering team30-Jul-15NANAReleased
1.03Aligned to portal version guidelinesUmesh Sambhari21-Nov-17NANAReleased
2.00Summary sheet template:
Changed title to indicate Implementation Peer Review
Corrected and/or clarified mouse hover comments, added instructions, renamed some fields.
Changed the default setting to "No" on the items reviewed
SW Engineering team29-Nov-17Lonnie Newton, Steven Horwath, Kevin Smith, Lucas Wendling, Vinod ShankarNAReleased
Source code template:
Removed hyperlink for naming conventions, corrected name of naming conventions document, added version field for naming conventions document.
Changed item about requirements tags to reflect that they should be removed
Added clarification that all combinations of conditionally compiled code must be checked
Item about accurately implementing SWC Design is modified and a new item added, both to clarify where to look when determining needed changes.
Added point for version of common naming conventions
Reworded multiple items for clarity
SW Engineering team29-Nov-17
Synergy project template:
added items for file/folder structure
added point on .gpj file in tools folder
SW Engineering team29-Nov-17
Davinci files template:
Clarified the StdDef item
Added new item for OBSOLETE
Clarified item on datadict.m comparison
Removed the references to .m file helper tool
Updated to reflect that all component should now use only implementation data types
Added points on PIMs and NVMs
SW Engineering team29-Nov-17
All template tabs:
Added/clarified/removed mouse hover comments.
Updated Review Board section
Removed the gridlines from all tabs
Updated titles to say "Nexteer SWC Implementation Peer Review"
Changed all occurences of "FDD" to "SWC Design"
SW Engineering team29-Nov-17
2.01Added a help tab and appropriate links
Added field on Summary sheet to report hours spent and content reviewed
Changed wording in an item in Polyspace tab and Source code tab
SW Engineering team21-Feb-18Lonnie Newton, Steven Horwath, Kevin Smith, Lucas Wendling, Vinod Shankar21-Feb-18Released