GateDrv0Ctrl_MDD
Module Design Document
For
Gate Drive 0 Control
VERSION: 9
DATE: 12-Jan-2018
Prepared By:
Shawn Penning,
Nexteer Automotive,
Saginaw, MI, USA
Location: The official version of this document is stored in the Nexteer Configuration Management System.
Revision History
| Version | Description | Author | Date |
| 1 | Initial version | Rijvi Ahmed | 07-July-2016 |
| 2 | Updated to design revision 1.8.0 | Avinash James | 21-Jan-2017 |
| 3 | Updated to design revision 2.0.0 | Shruthi Raghavan | 17-Feb-2017 |
| 4 | Updated to design revision 2.1.0 | Shruthi Raghavan | 27-Feb-2017 |
| 5 | Updated to design revision 2.3.0 | Shruthi Raghavan | 14-Mar-2017 |
| 6 | Updated to design revision 2.4.0 – Fix for phase reasonableness issues found during integration | Shruthi Raghavan | 24-Mar-2017 |
| 7 | Removed unused inputs from OperFltMonSt function. Added UT considerations per anomaly EA4#11845 | Shruthi Raghavan | 26-May-2017 |
| 8 | Updated graphical representation for the new outputs and client call. Added details for changed & new local functions Added new enum type and local constant | Shruthi Raghavan | 11-Sep-2017 |
| 9 | Updated design rationale for the state machine in Configuration State of gate drive. Added UT considerations per test corrections required in anomaly corrective action. | Shawn Penning | 12-Jan-2018 |
Table of Contents
3 GATEDRV0CTRL & High-Level Description 7
4 Design details of software module 8
4.1 Graphical representation of GATEDRV0CTRL 8
5.1 User defined typedef definition/declaration 9
5.2 Variable definition for enumerated types 9
6.1 Program(fixed) Constants 10
6.1.2 Module specific Lookup Tables Constants 10
7 Software Module Implementation 11
7.2 Initialization Functions 11
7.2.1 Per: GateDrv0CtrlInit1 11
7.3.1 Per: GateDrv0CtrlPer1 11
7.3.1.2 Processing of Function 11
7.3.2 Per: GateDrv0CtrlPer2 11
7.3.2.2 Processing of Function 11
7.5 Serial Communication Functions 11
7.6 Local Function/Macro Definitions 12
7.7 GLObAL Function/Macro Definitions 14
8 Known Limitations With Design 15
Abbrevations And Acronyms
| Abbreviation | Description |
| DFD | Design functional diagram |
| MDD | Module design Document |
References
This section lists the title & version of all the documents that are referred for development of this document
| Sr. No. | Title | Version |
| 1 | MDD Guidelines | 1.02 |
| 2 | Software Naming Conventions | 1.02 |
| 3 | Software Coding Standards | 1.01 |
| 4 | FDD – ES311A_GateDrv0Ctrl_Design | See synergy sub project version |
GATEDRV0CTRL & High-Level Description
This module configures the GateDrive0 connected with SPI channel CSIH2. It also does the diagnostics for GateDrive0 using SPI interface.
It also performs phase reasonable diagnostics when the inverter 0 fault input is active. Detects FET fault and indicates the type of fault and also in the case of single fet fault it indicates the phase faulted as well. Phase reasonableness is disabled on a phase with shorted FET
Design details of software module
Graphical representation of GATEDRV0CTRL
Variable Data Dictionary
User defined typedef definition/declaration
| Typedef Name | Element Name | User Defined Type | Legal Range (min) | Legal Range (max) |
| GateDrvCfgSt | - | Enumeration | 0 | 4 |
Variable definition for enumerated types
| Enum Name | Element Name | Value |
| GateDrvCfgSt | GATEDRVCFGST_RSTGATEDRVST | 0 |
| GATEDRVCFGST_WAIT2MS | 1 | |
| GATEDRVCFGST_CFGREG | 2 | |
| GATEDRVCFGST_SETUPSPIREGREAD | 3 | |
| GATEDRVCFGST_READBACKREGS | 4 |
Constant Data Dictionary
Program(fixed) Constants
Embedded Constants
Local
| Constant Name | Resolution | Units | Value |
| GATEDRVOFFSTCHKSIZE_CNT_U08 | 1U | Cnt | ((TblSize_m(ELECGLBPRM_GATEDRVOFFSTCHKDATA_CNT_U16)/8U) - 1U) |
| BITMASK0_CNT_U08 | 1 | Cnt | 0x01U |
| BITMASK2_CNT_U08 | 1 | Cnt | 0x04U |
| BITMASK4_CNT_U08 | 1 | Cnt | 0x10U |
| MOTDRVERRMIN_NANOSEC_F32 | Single precision float | NanoSec | 0.0F |
| MOTDRVERRMAX_NANOSEC_F32 | Single precision float | NanoSec | 40000000.0F |
| DIAG2REGBOOTSTRPSPLYFLTSTRTPOS_CNT_U08 | 1 | Cnt | 5U |
Global
| Constant Name |
| Refer to the FDD |
Module specific Lookup Tables Constants
| Constant Name | Resolution | Value | Software Segment |
| Refer to the design |
Software Module Implementation
Sub-Module Functions
None
Initialization Functions
Per: GateDrv0CtrlInit1
PERIODIC FUNCTIONS
Per: GateDrv0CtrlPer1
Design Rationale
None
Processing of Function
See design model for details.
Per: GateDrv0CtrlPer2
Design Rationale
It is the intent of this design to hold the value of
MotDrvr0IninTestCmpl between iterations of GateDrv0CtrlPer2.
There was an inexplicable model issue in which MotDrvr0IninTestCmpl
was being reset to 0 when MotDrvr0IninTestCmpl was not being
written in the IF branch of model (refer model notes)
Implementation Considerations:
No need to use a PIM or a static variable as this signal is an RTE
output. Since RTE signals work like a static variable, the
implementation always holds the last value.
Processing of Function
See design model for details.
Interrupt Functions
None
Serial Communication Functions
None
Local Function/Macro Definitions
Local Function #1
| Function Name | SpiAsyncTx | Type | Min | Max |
| Arguments Passed | Channel_Cnt_T_u08 | Spi_ChannelType | 0 | Full |
| TxData_Cnt_T_u16 | Spi_DataType | 0 | Full | |
| Sequence_Cnt_T_u08 | Spi_SequenceType | 0 | Full | |
| Return Value | None |
Description
(void) Spi_WriteIB( Channel_Cnt_T_u08, &TxData_Cnt_T_u16 );
(void) Call_Spi_AsyncTransmit( Sequence_Cnt_T_u08 );
Local Function #2
| Function Name | OffStVrfySt | Type | Min | Max |
| Arguments Passed | None | |||
| Return Value | None |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/OffState Verification Stateblock in design model.
Local Function #3
| Function Name | OffStVrfyData | Type | Min | Max |
| Arguments Passed | None | |||
| Return Value | Flt_Cnt_T_logl | Boolean | FALSE | TRUE |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/OffState Verification State/OffSt Verification Chk and Transition to Config State/OffStChk Incomplete/Offstate Verification /OffState Verification Check block in design model.
*It is optimized in the implementation to reduce the high static path count.
Local Function #4
| Function Name | CfgSt | Type | Min | Max |
| Arguments Passed | None | |||
| Return Value | None |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Configuration State block in design model.
The state machine is implemented slightly differently in code vs the model, but they are functionally equivalent.
The model adds 1 to the GateDrv0CfgCnt Pim to change to the next state in Configuration,but the code assigns values from a local enumeration (see section 5.2) instead of performing arithmetic on the Pim. The enumerated state assigned to GateDrv0CfgCnt Pim will match with the resulting state in the model.
Local Function #5
| Function Name | ReadBackRegs | Type | Min | Max |
| Arguments Passed | None | |||
| Return Value | None |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Configuration State/Read back Registers block in design model.
Local Function #6
| Function Name | OperFltMonrSt | Type | Min | Max |
| Arguments Passed | PhaOnTiMeasdA_NanoSec_T_u32 | Uint32 | 0 | 4294967295 |
| PhaOnTiMeasdB_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| PhaOnTiMeasdC_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| PhaOnTiSumAExp_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| PhaOnTiSumBExp_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| PhaOnTiSumCExp_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| *MotDrvErrA_NanoSec_T_f32 | Single precision float | 0.0F | 40000000.0F | |
| *MotDrvErrB_NanoSec_T_f32 | Single precision float | 0.0F | 40000000.0F | |
| *MotDrvErrC_NanoSec_T_f32 | Single precision float | 0.0F | 40000000.0F | |
| Return Value | None |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State block in design model.
Local Function #7
| Function Name | GateDrvDetermineOnStSngFETFlt | Type | Min | Max |
| Arguments Passed | *SpclSnpshtData0_Cnt_T_u32 | Uint32 | 0U | 4294967295U |
| *SpclSnpshtData1_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| *SpclSnpshtData2_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| Return Value | GenGateDrvFlt_Cnt_T_logl | Boolean | FALSE | TRUE |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/Status Register indicates Fault/Determine OnState Single FET Fault block in design model.
Local Function #8
| Function Name | GateDrvDetermineVltgFlt | Type | Min | Max |
| Arguments Passed | *SpclSnpshtData0_Cnt_T_u32 | Uint32 | 0U | 4294967295U |
| *SpclSnpshtData1_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| *SpclSnpshtData2_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| Return Value | GenGateDrvFlt_Cnt_T_logl | Boolean | FALSE | TRUE |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/Status Register indicates Fault/Determine VREG/Bootstrap Voltage Fault block in design model.
Local Function #9
| Function Name | GateDrvDetermineGenericFlt | Type | Min | Max |
| Arguments Passed | GateDrvAllSts_Cnt_T_u16 | Uint16 | 0 | 0xFFFF |
| *SpclSnpshtData0_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| *SpclSnpshtData1_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| *SpclSnpshtData2_Cnt_T_u32 | Uint32 | 0U | 4294967295U | |
| Return Value | GenGateDrvFlt_Cnt_T_logl | Boolean | FALSE | TRUE |
Description
See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/Status Register indicates Fault/Determine Generic Gate Drive Fault block in design model.
Local Function #10
| Function Name | SetNtcStInfo | Type | Min | Max |
| Arguments Passed | PhaOnTiMeasd_NanoSec_T_u32 | Uint32 | 0 | 4294967295 |
| PhaOnTiSumExp_NanoSec_T_u32 | Uint32 | 0 | 4294967295 | |
| AbsltErr_NanoSec_T_f32 | Single precision float | 0 | 3.4E+38 | |
| BitMask_Cnt_u08 | Uint8 | 0 | 127 | |
| NtcStInfo_Uls_T_u08 | Uint8 | 0 | 255 | |
| Return Value | Flt_Uls_T_lgc | Boolean | False | True |
Description
See ES311A_GateDrv0Ctrl/GateDrv0Ctrl/GateDrv0CtrlPer2/GateDrv Enable/Disable/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/No Faults/GateDrvPhaReasbnChk/MeasdPhaFltChkABC block in design model. This function implements NtcStInfoPhaA, NtcStInfoPhaB and NtcStInfoPhaC common functionality.
Local Function #11
| Function Name | ChkResVrfyRegs | Type | Min | Max |
| Arguments Passed | PrmByte_Cnt_T_u08 | Uint8 | 128 | 138 |
| Return Value | None | - | - | - |
Description
Check Results of Verify GateDrive0 Registers based on calculated parameter byte and take appropriate action
Local Function #12
| Function Name | WriteOutput | Type | Min | Max |
| Arguments Passed | None | - | - | - |
| Return Value | None | - | - | - |
Description
Implements the ‘ES311A_GateDrv0Ctrl_new/GateDrv0Ctrl/GateDrv0CtrlPer2/Write Output’ block in simulink model.
GLObAL Function/Macro Definitions
None
Known Limitations With Design
Note: The PIM Ivtr0InactvSts is written in Per2 and used in Per1 as well as Per2. Data consistency is not an issue because of explicit scheduling requirements given in the integration manual.
Note:
At multiple places, the implementation does not reset the error counter PIM when rollover to zero happens but the model does. This is because in the code the rollover is automatic (and marked intentional ), whereas in the model it isn’t that way and requires a manual reset.
In all the cases where (1) is applicable, the model comments say 65535 rather than 4294967295 as the value at which reset should occur. Upon discussion with FDD owner, the comment is wrong and will be changed with the next update.
UNIT TEST CONSIDERATION
Overflow is intentional and acceptable on PhaOnTiSumAExp_NanoSec_T_u32, PhaOnTiSumBExp_NanoSec_T_u32 and PhaOnTiSumCExp_NanoSec_T_u32 in Per2 function.
Rollover is intentional on Rte_Pim_GateDrv0SpiTrsmErrCntr. The code has comments that also mention this consideration.
Note: While the code and model do not exactly match on the implementation (because the model manually resets this error counter, while the code lets it auto-reset due to rollover), the output should be the same for the PIM because functionally they are same.The model is designed such that the table ELECGLBPRM_GATEDRVOFFSTCHKDATA_CNT_U16 is never indexed with a value of greater than its size in real life. However, in code we need an explicit check for safety. For this reason, when Rte_Pim_GateDrv0OffStChkIdx is given a value greater than or equal to the size of this table, the model and code will behave differently (this is expected , because it is an impossible scenario in the real world).
->
For PIL testing, the consideration is that the input values given to Rte_Pim_GateDrv0OffStChkIdx when MIL vectors are not available should be less than or equal to (GATEDRVOFFSTCHKSIZE_CNT_U08).This component has a config parameter. Use the file from local/include folder and NOT the one from local/generate folder for testing so that Tessy can vary the value of the configuration parameter in the range that it is given in the data dictionary.
Please rectify wrong expected values of tests as part of anomaly corrective action. See PDF attached here (refer to both root cause and corrective action).