#	Title	Version
1	EA4 Software Naming Conventions	See Process 04.04.02
2	Software Design and Coding standards	See Process 04.04.02
3	Functional Design Document: CM109B_ClkCfgAndMon_Design	See Synergy SubProject Version

Dependencies

SWCs

Module	Required Feature
Os.h	SuspendAllInterrupts,ResumeAllInterrupts,SuspendOSInterrupts,ResumeOSInterrupts

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

ClkCfgAndMonInit0 : To be called prior to OS initialization.
See StartupSequence FDD for details.

Configuration REQUIREMeNTS

Build Time Config

Modules	Notes
None

Configuration Files to be provided by Integration Project

None.

Da Vinci Parameter Configuration Changes

Following parameters are part of Renesas/EcucDefs_Mcu/Mcu/McuGeneralConfiguration container
Note: Clm4 is not applicable to P1M-c devices.

Parameter	Decription	Value	SWC
McuClm0MonitoringClockAccuracy	This parameter specifies the monitoring clock accuracy of CLMA0 in percentage	6	Mcu
McuClm0Operation	This parameter enables or disables operation of clock monitor fn for CLMA0.	TRUE	Mcu
McuClm0SamplingClockAccuracy	This parameter specifies the sampling clock accuracy of CLMA0 in percentage.	10	Mcu
McuClm1MonitoringClockAccuracy	This parameter specifies the monitoring clock accuracy of CLMA1 in percentage	6	Mcu
McuClm1Operation	This parameter enables or disables operation of clock monitor fn for CLMA1.	TRUE	Mcu
McuClm1SamplingClockAccuracy	This parameter specifies the sampling clock accuracy of CLMA1 in percentage.	6	Mcu
McuClm2MonitoringClockAccuracy	This parameter specifies the monitoring clock accuracy of CLMA2 in percentage	10	Mcu
McuClm2Operation	This parameter enables or disables operation of clock monitor fn for CLMA2.	TRUE	Mcu
McuClm2SamplingClockAccuracy	This parameter specifies the sampling clock accuracy of CLMA2 in percentage.	6	Mcu
McuClm3MonitoringClockAccuracy	This parameter specifies the monitoring clock accuracy of CLMA3 in percentage	6	Mcu
McuClm3Operation	This parameter enables or disables operation of clock monitor fn for CLMA3.	TRUE	Mcu
McuClm3SamplingClockAccuracy	This parameter specifies the sampling clock accuracy of CLMA3 in percentage.	6	Mcu

DaVinci Interrupt Configuration Changes

ISR Name	VIM #	Priority Dependency	Notes
None

Manual Configuration Changes

Constant	Notes	SWC
None

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer FDD.

Required Global Data Outputs

Refer FDD

Specific Include Path present

Yes

Runnable Scheduling

This section specifies the required runnable scheduling.

Init	Scheduling Requirements	Trigger
ClkCfgAndMonInit0	Pre-OS	Non-RTE (Init)
ClkCfgAndMonInit1	None	RTE (Init)

Runnable	Scheduling Requirements	Trigger
-	-	-

Memory Map REQUIREMENTS

Mapping

Memory Section	Contents	Notes
CDD_ClkCfgAndMon_START_SEC_CODE	RTE & Non-RTE code

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Feature	RAM	ROM
-

Table 1: ARM Cortex R4 Memory Usage

NvM Blocks

None.

Compiler Settings

Preprocessor MACRO

None

Optimization Settings

None

Appendix

None

2 - ClkCfgAndMon_MDD

Module Design Document

For

ClkCfgAndMon

21-Nov-2017

Prepared By:

Shruthi Raghavan,

Nexteer Automotive,

Saginaw, MI, USA
Change History

Description	Author	Version	Date
Initial Version	Shruthi Raghavan	1.0	21-Nov-2017

Table of Contents

1 Introduction 4

1.1 Purpose 4

2 ClkCfgAndMon & High-Level Description 5

3 Design details of software module 6

3.1 Graphical representation of <Component Name> 6

3.2 Data Flow Diagram 6

3.2.1 Component level DFD 6

3.2.2 Function level DFD 6

4 Constant Data Dictionary 7

4.1 Program (fixed) Constants 7

4.1.1 Embedded Constants 7

5 Software Component Implementation 8

5.1 Sub-Module Functions 8

5.1.1 Init: ClkCfgAndMonInit0 8

5.1.1.1 Design Rationale 8

5.1.2 Periodic 8

5.2 Server Runables 8

5.3 Interrupt Functions 8

5.4 Module Internal (Local) Functions 8

5.5 GLOBAL Function/Macro Definitions 8

6 Known Limitations with Design 9

7 UNIT TEST CONSIDERATION 10

Appendix A Abbreviations and Acronyms 11

Appendix B Glossary 12

Appendix C References 13

Introduction

Purpose

Module Design Document for CM109B (ClkCfgAndMon) Implementation. See design for details.

ClkCfgAndMon & High-Level Description

Refer FDD document.

Design details of software module

Graphical representation of <Component Name>

Data Flow Diagram

Component level DFD

Refer FDD

Function level DFD

Refer FDD

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Constant Name	Resolution	Units	Value
-	-	-	-

Software Component Implementation

Sub-Module Functions

Init: ClkCfgAndMonInit0

Design Rationale

Non-RTE Init implemented as per FDD document directions.

Init: ClkCfgAndMonInit1

Design Rationale

RTE Init for MemMap – Empty.

Periodic

None

Server Runables

None

Interrupt Functions

None

Module Internal (Local) Functions

Function Name	-	Type	Min	Max
Arguments Passed	-	-	-	-

GLOBAL Function/Macro Definitions

None

Known Limitations with Design

None.

UNIT TEST CONSIDERATION

Register file definitions are in the P1Xc/include folder of AR202A since this component is designed for P1X-c micro.

Abbreviations and Acronyms

Abbreviation or Acronym	Description

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

ISO 9000
ISO/IEC 12207
ISO/IEC 15504
Automotive SPICE® Process Reference Model (PRM)
Automotive SPICE® Process Assessment Model (PAM)
ISO/IEC 15288
ISO 26262
IEEE Standards
SWEBOK
PMBOK
Existing Nexteer Automotive documentation

Term	Definition	Source
MDD	Module Design Document
DFD	Data Flow Diagram

References

#	Title	Version
1	AUTOSAR Specification of Memory Mapping	See Process 04.04.02
2	MDD Guideline	See Process 04.04.02
3	Software Naming Conventions.doc	See Process 04.04.02
4	Software Design and Coding Standards.doc	See Process 04.04.02
5	FDD : CM109B_ClkCfgAndMon_Design	See Synergy Subproject Version

3 - ClkCfgAndMon_PeerReviewChecklist

Overview

Summary Sheet
Synergy Project
Source Code
PolySpace
Version History

Sheet 1: Summary Sheet

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Summary Sheet

Component Short Name:

Windows User: Intended Use: Identify which component is being reviewed. This should match the component short name from the DataDict.m fileand the middle part of the Synergy project name, e.g. Assi for the SF001A_Assi_Impl Synergy project

ClkCfgAndMon

Revision / Baseline:

Windows User: Intended Use: Identify the implementation baseline name intended to be used for the changed component when changes are approved E.g. SF001A_Assi_Impl_1.2.0

CM109B_ClkCfgAndMon_Impl_1.1.0

Change Owner:

Windows User: Intended Use: Identify the developer who made the change(s) being reviewed

Shruthi Raghavan

Work CR ID:

Windows User: Intended Use: Identify the Implementation Work CR whose work is being reviewed (may be more than one)

EA4#16561

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

Check the file types that needed modification for the Work CR(s); macros for the check boxes will populate the appropriate checklist tabs for the review.

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

At start of review, all items below should be marked "No". At the end of the review, all items should be marked "Yes" or "N/A" where N/A indicates the reviewers have reviewed the existing (unchanged) item and confirmed no updates were needed for the Work CR(s).

N/A

MDD

Yes

Source Code

Yes

PolySpace

N/A

Integration Manual

N/A

Davinci Files

Comments:

General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include SWC Owner and/or SWC Design author and Integrator and/or SW Lead as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.

Each peer review shall start with a clean copy of the latest peer review checklist template. Before the peer review, the change owner shall:
o Review the previous component peer review and copy any relevant comments to the new review sheet.
o Review all checklist items and make all corrections needed, so that the component is ready for peer review. The expectation is that peer review should find very few issues,
because the change owner has already used the checklist to ensure the component changes are complete and correct.
o Fill in all file name and version information as needed on peer review checklist tabs (file names may be copied from the previous peer review where appropriate)
o Fill in checklist answers (Yes/No/NA pulldowns) ONLY on those items which are NA for the current change. All other checklist items should be blank going into the review
meeting.

During the peer review meeting:
o For each page of the review, first review the items already marked as N/A for this change, to confirm that reviewers agree with this assessment; change the checklist box to
blank if it is found that the item does apply.
o Then review the items with the checklist box blank. After reviewing each of these items, the checklist box will be marked as "Yes", or the checklist box will be marked as
"No" with needed rework indicated or with rationale indicated.
o If any items are marked "No" with rationale indicated, this must be approved by a software supervisor or the software manager; there is a line in the "Review Board" section
of each tab to indicate who approved the "No" items on that tab.

Sheet 2: Synergy Project

Rev 2.00

29-Nov-17

Peer Review Meeting Log (Component Synergy Project Review)

Quality Check Items:

Rationale is required for all answers of No

New baseline version name from Summary Sheet follows

Yes

Comments:

naming convention

Project contains necessary subprojects

N/A

Comments:

Project contains the correct version of subprojects

N/A

Comments:

Design subproject is correct version

N/A

Comments:

.gpj file in tools folder matches .gpj generated by TL109 script

N/A

Comments:

File/folder structure is correct per documentation in

N/A

Comments:

TL109A_SwcSuprt

General Notes / Comments:

Review Board:

Change Owner:

Shruthi Raghavan

Review Date :

01/04/18

Lead Peer Reviewer:

Avinash James

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Xin Liu

Rationale/justification for items marked "No" approved by:

Sheet 3: Source Code

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Meeting Log (Source Code Review)

Source File Name:

CDD_ClkCfgAndMonNonRte.c

Source File Revision:

Windows User: Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) 2

Header File Name:

CDD_ClkCfgAndMon.h

Header File Revision:

Windows User: Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) 1

MDD Name:

ClkCfgAndMon_MDD.docx

Revision:

Windows User: Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) 1

SWC Design Name:

CM109B_ClkCfgAndMon_Design

Revision:

Windows User: Intended Use: For FDDs, list the Synergy baseline number (just the number part of the Synergy baseline name) of the FDD baseline being implemented. E.g., for SF001A_Assi_Design_1.3.1, this field would say "1.3.1" 1.1.0

Quality Check Items:

Rationale is required for all answers of No

EA4 Common Naming Convention followed:

Version: 1.01

EA4 Software Naming Convention followed:

Version: 1.02

for variable names

N/A

Comments:

for constant names

N/A

Comments:

for function names

N/A

Comments:

for other names (component, memory

Yes

Comments:

mapping handles, typedefs, etc.)

Verified no possibility of uninitialized variables being

N/A

Comments:

written to component outputs or IRVs

Any requirements traceability tags have been removed

N/A

Comments:

from at least the changed areas of code

All variables are declared at the function level.

N/A

Comments:

Synergy version matches change history

kzshz2: Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). Rationale: There have been many occassions where versions were not updated in files and as a result Unit Test were referencing wrong versions. This often time leads to the need to re-run of batch tests.

Yes

Comments:

and Version Control version in file comment block

Change log contains detailed description of changes

Yes

Comments:

(including any anomaly number(s) being fixed) and

Work CR number

Code accurately implements SWC Design (Document or Model)

N/A

Comments:

in all areas where code was changed and/or Simulink

model was color-coded as changed and/or mentioned

in SWC Design change log. (This item includes looking at all

layers of Simulink model for possible color coding not

reflected at a higher level, and includes looking at any

intermediate SWC Design versions between the version being

implemented and the version that was included as a

subproject in the previous implementation.)

Code comparison against previous version matches

Yes

Comments:

changes needed as described by the work CR(s), all

Task has details

parent CRs and parent anomalies, and the SWC

Design change log.

Verified no Compiler Errors or Warnings

KMC: Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). Rationale: This is needed to ensure there will be no errors discovered at the time of integration. A Sandox project should be used.

Yes

Comments:

(and verified for all possible combinations

of any conditionally compiled code)

Component.h is included

N/A

Comments:

All other includes are actually needed. (System includes

N/A

Comments:

only allowed in Nexteer library components)

Software Design and Coding Standards followed:

Windows User: Intended Use: list version/revision of latest released Software Design and Coding Standards document. Version: 2.01

Code comments are clear, correct, and adequate

N/A

Comments:

and have been updated for the change: [N40] and

all other rules in the same section as rule [N40],

plus [N75], [N12], [N23], [N33], [N37], [N38],

[N48], [N54], [N77], [N79], [N72]

Source file (.c and .h) comment blocks are per

Yes

Comments:

standards and contain correct information: [N41], [N42]

Function comment blocks are per standards and

N/A

Comments:

contain correct information: [N43]

Code formatting (indentation, placement of

Yes

Comments:

braces, etc.) is per standards: [N5], [N55], [N56],

[N57], [N58], [N59]

Embedded constants used per standards; no

N/A

Comments:

"magic numbers": [N12]

Memory mapping for non-RTE code

Yes

Comments:

is per standard

corrected placement

All access of motor control loop data uses macros

N/A

Comments:

generated by the motor control manager

All loops have termination conditions that ensure

N/A

Comments:

finite loop iterations: [N63]

All divides protect against divide by zero

N/A

Comments:

if needed: [N65]

All integer division and modulus operations

N/A

Comments:

handle negative numbers correctly: [N76]

All typecasting and fixed point arithmetic,

N/A

Comments:

including all use of fixed point macros and

timer functions, is correct and has no possibility

of unintended overflow or underflow: [N66]

All float-to-unsigned conversions ensure the.

N/A

Comments:

float value is non-negative: [N67]

All conversions between signed and unsigned

N/A

Comments:

types handle msb==1 as intended: [N78]

All pointer dereferencing protects against

N/A

Comments:

null pointer if needed: [N70]

Component outputs are limited to the legal range

N/A

Comments:

defined in the SWC Design DataDict.m file : [N53]

All code is mapped with SWC Design (all SWC

N/A

Comments:

Design subfunctions and/or model blocks identified

with code comments; all code corresponds to

some SWC Design subfunction and/or model block):

[N40]

Any other violations of design and coding

Yes

Comments:

standards noticed during the review are noted in the

comments section for rework.

Anomaly or Design Work CR created

N/A

Comments: List Anomaly or CR numbers

for any SWC Design corrections needed

General Notes / Comments:

same cr used for implementation fixes because it was open and not used yet.

sandbox project file is modified to include th P1Xc registers for local compile : 1/4/2018 approved by Steve

Review Board:

Change Owner:

Shruthi Raghavan

Review Date :

01/04/18

Lead Peer Reviewer:

Avinash James

Approved by Reviewer(s):

Yes

SWC owner and/or
SWC Design author:

Avinash James

Comments:

Integrator and or
SW lead:

Xin Liu

Comments:

Unit test co-ordinator:

Comments:

Other Reviewer(s):

Rationale/justification for items marked "No" approved by:

Sheet 4: PolySpace

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Meeting Log (PolySpace Review)

Source File Name:

CDD_ClkCfgAndMon.c

Source File Revision:

Source File Name:

CDD_ClkCfgAndMonNonRte.c

Source File Revision:

EA4 Static Analysis Compliance Guideline version:

1.04

Poly Space version:

Windows User: eg. 2013b

2013b

TL109A sub project version:

2.2.0

Quality Check Items:

Rationale is required for all answers of No

tools/local folders' header files are appropriate and

N/A

Comments:

function prototypes match the latest component version

100% Compliance to the EA4 Static Analysis

Yes

Comments:

Compliance Guideline

Are previously added justification and deviation

Yes

Comments:

comments still appropriate

Do all MISRA deviation comments use approved

Yes

Comments:

deviation tags

For any component source files (.c, .h, generated Cfg.c and Cfg.h)

N/A

Comments:

with conditional compilation, has Polyspace been run with all

combinations of build constants that can be used together in a build?

(Note which conditional compilation results have been archived)

Cyclomatic complexity and Static path count OK

Yes

Comments:

for all functions in the component per Design

and Coding Standards rule [N47]

General Notes / Comments:

Review Board:

Change Owner:

Shruthi Raghavan

Review Date :

01/04/18

Lead Peer Reviewer:

Avinash James

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Xin Liu

Rationale/justification for items marked "No" approved by:

Sheet 5: Version History



File Version History
Version	Description	Author(s)	Revision Date	Approved By	Approved Date	Status
						Draft/ Released










Template Version History
Version	Description	Author(s)	Revision Date	Approved By	Approved Date	Status
1.0	Initial Version	SW Engineering team	24-May-15	NA	NA	Released
1.01	Changed name to be EA4 specific	SW Engineering team	25-Jun-15	NA	NA	Released
1.02	Modified Summary Sheet General Guidelines, Clarified wording on first item in Synergy project sheet.	SW Engineering team	30-Jul-15	NA	NA	Released
1.02	Made corrections and clarifications to Source Code check list.	SW Engineering team	30-Jul-15	NA	NA	Released
1.02	updated Davinci, MDD, and Polyspace/QAC tabs	SW Engineering team	30-Jul-15	NA	NA	Released
1.03	Aligned to portal version guidelines	Umesh Sambhari	21-Nov-17	NA	NA	Released
2.00	Summary sheet template: Changed title to indicate Implementation Peer Review Corrected and/or clarified mouse hover comments, added instructions, renamed some fields. Changed the default setting to "No" on the items reviewed	SW Engineering team	29-Nov-17	Lonnie Newton, Steven Horwath, Kevin Smith, Lucas Wendling, Vinod Shankar	NA	Released
	Source code template: Removed hyperlink for naming conventions, corrected name of naming conventions document, added version field for naming conventions document. Changed item about requirements tags to reflect that they should be removed Added clarification that all combinations of conditionally compiled code must be checked Item about accurately implementing SWC Design is modified and a new item added, both to clarify where to look when determining needed changes. Added point for version of common naming conventions Reworded multiple items for clarity	SW Engineering team	29-Nov-17
	Synergy project template: added items for file/folder structure added point on .gpj file in tools folder	SW Engineering team	29-Nov-17
	Davinci files template: Clarified the StdDef item Added new item for OBSOLETE Clarified item on datadict.m comparison Removed the references to .m file helper tool Updated to reflect that all component should now use only implementation data types Added points on PIMs and NVMs	SW Engineering team	29-Nov-17
	All template tabs: Added/clarified/removed mouse hover comments. Updated Review Board section Removed the gridlines from all tabs Updated titles to say "Nexteer SWC Implementation Peer Review" Changed all occurences of "FDD" to "SWC Design"	SW Engineering team	29-Nov-17