Component Implementation

• 1: ExcpnHndlg Integration Manual
• 2: ExcpnHndlg Module Design Document
• 3: ExcpnHndlg_PeerReviewChecklist

1 - ExcpnHndlg Integration Manual

Integration Manual

For

ExcpnHndlg

VERSION: 1

DATE: 12/11/17

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA

Location: The official version of this document is stored in the Nexteer Configuration Management System.

Revision History

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 8

4.1 Build Time Config 8

4.2 Configuration Files to be provided by Integration Project 8

4.3 Da Vinci Parameter Configuration Changes 8

4.4 DaVinci Interrupt Configuration Changes 8

4.5 Manual Configuration Changes 8

5 Integration DATAFLOW REQUIREMENTS 9

5.1 Required Global Data Inputs 9

5.2 Required Global Data Outputs 9

5.3 Specific Include Path present 9

6 Runnable Scheduling 10

7 Memory Map REQUIREMENTS 11

7.1 Mapping 11

7.2 Usage 11

7.3 NvM Blocks 11

8 Compiler Settings 12

8.1 Preprocessor MACRO 12

8.2 Optimization Settings 12

9 Appendix 13

Abbrevations And Acronyms

References

This section lists the title & version of all the documents that are referred for development of this document

Dependencies

SWCs

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

SetMcuDiagcIdnData – Non-Rte Server Interface (called as needed)

GetMcuDiagcIdnData – Non-Rte Server Interface (called as needed)

SysErrIrq/Patched_SysErrIrq – Interrupt Handler Routine (triggered by Interrupt)

FpuErrIrq/Patched_FpuErrIrq – Interrupt Handler Routine (triggered by Interrupt)

AlgnErrIrq – Interrupt Handler Routine (triggered by Interrupt)

ResdOperIrq – Interrupt Handler Routine (triggered by Interrupt)

ExcpnHndlgInit1 – Non-RTE initialization function (called during startup before RTE is initialized)

FeNmiPegErr – Callout function for interrupt response handling (to be called by FENMI Interrupt handler)

FeNmiDmaTrfErr – Callout function for interrupt response handling (to be called by FENMI Interrupt handler)

FeNmiEcmMstChkrErr– Callout function for interrupt response handling (to be called by FENMI Interrupt handler)

FeNmiWdgErr– Callout function for interrupt response handling (to be called by FENMI Interrupt handler)

ProcUkwnExcpnErr – Callout function for OS error response handling (to be called by OS error handler)

ProcMpuExcpnErr – Callout function for OS error response handling (to be called by OS error handler)

ProcPrvlgdInstrExcpnErr – Callout function for OS error response handling (to be called by OS error handler)

ProcPrmntOsErr – Callout function for OS error response handling (to be called by OS error handler)

ProcNonCritOsErr – Callout function for OS error response handling (to be called by OS error handler)

ChkForStrtUpTest_Oper – (called as needed from both RTE and non-RTE context))

FeNmiClkMonr0RtLowrLimFlt – Callout function responding to Clock Monitor 0 Runtime Lower Limit Failure(to be called by FENMI Interrupt handler)

FeNmiClkMonr0RtErr – Callout function responding to Clock Monitor 0 Runtime Failure (to be called by FENMI Interrupt handler)

FeNmiClkMonr1RtErr – Callout function responding to Clock Monitor 1 Runtime Failure (to be called by FENMI Interrupt handler)

FeNmiClkMonr2RtErr – Callout function responding to Clock Monitor 2 Runtime Failure (to be called by FENMI Interrupt handler)

FeNmiClkMonr3RtErr – Callout function responding to Clock Monitor 3 Runtime Failure (to be called by FENMI Interrupt handler)

FeNmiClkMonr5RtErr – Callout function responding to Clock Monitor 5 Runtime Failure (to be called by FENMI Interrupt handler)

FeNmiModErrDbgActv – Callout function responding to Debug mode active failure (to be called by FENMI Interrupt handler)

FeNmiModErrProgmModActv – Callout function responding to Programming mode active failure (to be called by FENMI Interrupt handler)

FeNmiModErrUsrModInactv – Callout function responding to user mode being inactive failure (to be called by FENMI Interrupt handler)

FeNmiModErrTestModActv – Callout function responding to Test mode active failure (to be called by FENMI Interrupt handler)

FeNmiBusBrdgErr – Callout function responding to Bus Bridge error (to be called by FENMI Interrupt handler)

FeNmiBusSngBitEccErr – Callout function Single bit ECC error on the data bus (to be called by FENMI Interrupt handler)

FeNmiCodFlsEccAdrOvfErr – Callout function code flash ecc address overflow error (to be called by FENMI Interrupt handler)

FeNmiCodFlsIllglAcsBySysBus – Callout function responding to illegal access of code flash by the system bus (to be called by FENMI Interrupt handler)

FeNmiDmaIllglAcsErr – Callout function responding to illegal access by the DMA (to be called by FENMI Interrupt handler)

FeNmiDmaLockStepErrOrGblRamWrBufErr – Callout function responding to Dma lock step error or Global RAM write buffer error (to be called by FENMI Interrupt handler)

FeNmiDtsRamDblBitEccErr – Callout function responding to Dts Ram ECC double bit failure (to be called by FENMI Interrupt handler)

FeNmiFlsSeqErr – Callout function responding to flash sequencer failure (to be called by FENMI Interrupt handler)

FeNmiGblRamIllglAcsByProcr – Callout function responding to illegal access of global RAM by processor (to be called by FENMI Interrupt handler)

FeNmiGblRamIllglAcsBySysBus – Callout function responding to global RAM illegal access by system bus (to be called by FENMI Interrupt handler)

FeNmiPrphlRamEccAdrOvfErr – Callout function responding to peripheral RAM ECC address overflow error (to be called by FENMI Interrupt handler)

FeNmiGlbRamEccAdrOvfErr – Callout function responding to global ram ecc address overflow error (to be called by FENMI Interrupt handler)

FeNmiGtmRamDblBitEccErr – Callout function responding to GTM RAM ecc double bit error (to be called by FENMI Interrupt handler)

FeNmiLclRamEccAdrOvfErr – Callout function responding to local RAM ecc address overflow error (to be called by FENMI Interrupt handler)

FeNmiProcrLockStepErr – Callout function responding to processor lockstep error (to be called by FENMI Interrupt handler)

FeNmiResdAreaIllglAcsByHiSpdBus – Callout function responding to Reserved area illegal access by High Speed bus (to be called by FENMI Interrupt handler)

Note:- The configuration for the Non RTE server runnables for the FENMI handler is done in the MCU component as per the error source configuration list available in CM104B Design.

The OS errors are configured in the OS component. OS document shall explain the configuration of the OS related errors

Configuration REQUIREMeNTS

Build Time Config

Configuration Files to be provided by Integration Project

N/A

Da Vinci Parameter Configuration Changes

DaVinci Interrupt Configuration Changes

Manual Configuration Changes

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer FDD

Required Global Data Outputs

Refer FDD

Specific Include Path present

Yes

Runnable Scheduling

API usage and scheduling of BSW components expected to be captured at a project architectural level and is beyond the scope of this document. Third party documentation can be referenced as needed.

.

Memory Map REQUIREMENTS

Mapping

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

NvM Blocks

None

Compiler Settings

Preprocessor MACRO

None

Optimization Settings

None

Appendix

None

2 - ExcpnHndlg Module Design Document

Module Design Document

For

ExcpnHndlg

Mar 11, 2018

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA
Change History

Table of Contents

1 Introduction 4

1.1.1 Purpose 4

2 ExcpnHndlg & High-Level Description 5

3 Design details of software module 6

3.1.1 Graphical representation of ExcpnHndlg 6

3.1.2 Data Flow Diagram 6

3.1.3 Component level DFD 6

3.1.4 Function level DFD 6

4 Constant Data Dictionary 7

4.1.1 Program (fixed) Constants 7

4.1.2 Embedded Constants 7

5 Software Component Implementation 11

5.1.1 Sub-Module Functions 11

5.1.2 Per: ExcpnHndlgPer1 11

5.1.3 Server Runables 11

5.1.4 Interrupt Functions 17

5.1.5 Module Internal (Local) Functions 17

5.1.6 GLOBAL Function/Macro Definitions 18

5.1.7 GLOBAL Function #1 18

5.1.8 Design Rationale 18

5.1.9 processing 18

6 Known Limitations with Design 19

7 UNIT TEST CONSIDERATION 20

Appendix A Abbreviations and Acronyms 21

Appendix B Glossary 22

Appendix C References 23

Introduction

Purpose

This document details the design in the FDD and also lists out any deviations which were made from the design for the implementation due to any constraints in development. ExcpnHndlg MDD describes the exception handling / reset cause determination for microcontroller diagnostics

ExcpnHndlg & High-Level Description

Refer FDD

Design details of software module

Graphical representation of ExcpnHndlg

Data Flow Diagram

Component level DFD

N/A

Function level DFD

N/A

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Software Component Implementation

Sub-Module Functions

Init: ExcpnHndlgInit1

Design Rationale

Non-RTE function because it needs to be called before the OS is started - so that floating point exceptions can be enabled before anything uses floating point

Module Outputs

None

Init: ExcpnHndlgInit2

Design Rationale

RTE function to initialize all the NTCs to pass

Module Outputs

None

Per: ExcpnHndlgPer1

Design Rationale

RTE Periodic function called every 2 ms to check for OS errors

Store Module Inputs to Local copies

Refer MDD

(Processing of function)………

Triggered on Timing Event every 2ms

Store Local copy of outputs into Module Outputs

None

Server Runables

ChkForStrtUpTest

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiClkMonr0RtErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiClkMonr1RtErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiClkMonr2RtErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiClkMonr3RtErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiClkMonr5RtErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiModErrDbgActv

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiModErrProgmModActv

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiModErrUsrModInactv

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiModErrTestModActv

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiBusBrdgErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiBusSngBitEccErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiCodFlsEccAdrOvfErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiCodFlsIllglAcsBySysBus

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiDmaIllglAcsErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiDmaLockStepErrOrGblRamWrBufErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiDmaTrfErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiDtsRamDblBitEccErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiEcmMstChkrErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiFlsSeqErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiGblRamIllglAcsByProcr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiGblRamIllglAcsBySysBus

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiPrphlRamEccAdrOvfErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiGlbRamEccAdrOvfErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiGtmRamDblBitEccErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiLclRamEccAdrOvfErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiPegErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiProcrLockStepErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiResdAreaIllglAcsByHiSpdBus

Design Rationale

Refer FDD

Processing of function

Refer FDD

FeNmiWdgErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

ProcUkwnExcpnErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

ProcMpuExcpnErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

ProcPrvlgdInstrExcpnErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

ProcPrmntOsErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

ProcNonCritOsErr

Design Rationale

Refer FDD

Processing of function

Refer FDD

GetMcuDiagcIdnData

Design Rationale

Refer FDD

Processing of function

Refer FDD

SetMcuDiagcIdnData

Design Rationale

Refer FDD

Processing of function

Refer FDD

Interrupt Functions

AlgnErrIrq

Design Rationale

Refer FDD

Processing of function

Refer FDD

FpuErrIrq

Design Rationale

Refer FDD

Processing of function

Refer FDD

SysErrIrq

Design Rationale

Refer FDD

Processing of function

Refer FDD

ResdOperIrq

Design Rationale

Refer FDD

Processing of function

Refer FDD

Module Internal (Local) Functions

ProcStrtUpOrSwRst

Design Rationale

Refer FDD

Processing of function

Refer FDD

McuDiagcRstChk

Design Rationale

Checks if the reset cause is power on/Flash Progamming /Hard Reset /Soft Reset.

Processing

Refer the FDD

GLOBAL Function/Macro Definitions

<If these are numerous and defined in a separate source file then reference the source file only.>

GLOBAL Function #1

Design Rationale

processing

(Place flowchart/design for local function)

Known Limitations with Design

None

UNIT TEST CONSIDERATION

The PIMs listed in the Data dictionary file BackUpRam and ExcpnHndlgOsErrCod are non RTE PIMS which need special memory mapping and are not generated through RTE. Hence use the component level variable name as used in the component for these PIMs

Abbreviations and Acronyms

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

• ISO 9000

• ISO/IEC 12207

• ISO/IEC 15504

• Automotive SPICE® Process Reference Model (PRM)

• Automotive SPICE® Process Assessment Model (PAM)

• ISO/IEC 15288

• ISO 26262

• IEEE Standards

• SWEBOK

• PMBOK

• Existing Nexteer Automotive documentation

References

3 - ExcpnHndlg_PeerReviewChecklist

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Summary Sheet

Component Short Name:

Windows User: Intended Use: Identify which component is being reviewed. This should match the component short name from the DataDict.m fileand the middle part of the Synergy project name, e.g. Assi for the SF001A_Assi_Impl Synergy project

ExcpnHndlg

Revision / Baseline:

Windows User: Intended Use: Identify the implementation baseline name intended to be used for the changed component when changes are approved E.g. SF001A_Assi_Impl_1.2.0

CM101B_ExcpnHndlg_Impl_1.2.0

Change Owner:

Windows User: Intended Use: Identify the developer who made the change(s) being reviewed

Avinash James

Work CR ID:

Windows User: Intended Use: Identify the Implementation Work CR whose work is being reviewed (may be more than one)

EA4#21569

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

Check the file types that needed modification for the Work CR(s); macros for the check boxes will populate the appropriate checklist tabs for the review.

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

At start of review, all items below should be marked "No". At the end of the review, all items should be marked "Yes" or "N/A" where N/A indicates the reviewers have reviewed the existing (unchanged) item and confirmed no updates were needed for the Work CR(s).

N/A

MDD

N/A

Source Code

N/A

PolySpace

N/A

Integration Manual

N/A

Davinci Files

Comments:

Due to timing constraints the formal peer review porocess has been skipped. Approved deviation by

Lonnie Newton

General Guidelines: - The reviews shall be performed over the portions of the component that were modified as a result of the Change Request. - New components should include SWC Owner and/or SWC Design author and Integrator and/or SW Lead as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files) - Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed. - To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file. - .h file should be reviewed with the source file as part of the source file. Each peer review shall start with a clean copy of the latest peer review checklist template. Before the peer review, the change owner shall: o Review the previous component peer review and copy any relevant comments to the new review sheet. o Review all checklist items and make all corrections needed, so that the component is ready for peer review. The expectation is that peer review should find very few issues, because the change owner has already used the checklist to ensure the component changes are complete and correct. o Fill in all file name and version information as needed on peer review checklist tabs (file names may be copied from the previous peer review where appropriate) o Fill in checklist answers (Yes/No/NA pulldowns) ONLY on those items which are NA for the current change. All other checklist items should be blank going into the review meeting. During the peer review meeting: o For each page of the review, first review the items already marked as N/A for this change, to confirm that reviewers agree with this assessment; change the checklist box to blank if it is found that the item does apply. o Then review the items with the checklist box blank. After reviewing each of these items, the checklist box will be marked as "Yes", or the checklist box will be marked as "No" with needed rework indicated or with rationale indicated. o If any items are marked "No" with rationale indicated, this must be approved by a software supervisor or the software manager; there is a line in the "Review Board" section of each tab to indicate who approved the "No" items on that tab.