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Component Implementation

1: GuardCfgAndDiagc Integration Manual
2: GuardCfgAndDiagc Module Design Document
3: GuardCfgAndDiagc_PeerReviewChecklist

Component Implementation

Component Documentation

1 - GuardCfgAndDiagc Integration Manual

Integration Manual

For

GuardCfgAndDiagc

VERSION: 2

DATE: 12/18/17

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA

Location: The official version of this document is stored in the Nexteer Configuration Management System.

Revision History

Sl. No.	Description	Author	Version	Date
1	Initial version	Avinash James	1	11/12/17
2	Added configuration capability for DMA write RAM	Avinash James	2	12/18/17

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

Abbreviation	Description
DFD	Design functional diagram
MDD	Module design Document
FDD	Functional Design Document

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.	Title	Version
1	FDD – CM107B GuardCfgAndDiagc	See Synergy subproject version
2	Software Naming Conventions	Process 04.04.02
3	Software Coding Standards	Process 04.04.02

Dependencies

SWCs

Module	Required Feature
AR202A MicroCtrlrSuprt	NxtrMcuSuprtLib functions and register definitions

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

GuardCfgAndDiagcInit1 - Non-RTE function so that guard protection can be initialized and enabled before the RTE is started

IpgInin - To be configured as a trusted function because it needs to run in supervisor mode

Configuration REQUIREMeNTS

Build Time Config

Modules	Notes

Configuration Files to be provided by Integration Project

Da Vinci Parameter Configuration Changes

Parameter	Notes	SWC

DaVinci Interrupt Configuration Changes

ISR Name	VIM #	Priority Dependency	Notes

Manual Configuration Changes

Constant	Notes	SWC
DmaWrRamBasAddr	DMA Write Ram base address symbol.Defined in the memory architecture document	Linker file

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

None

Required Global Data Outputs

None

Specific Include Path present

Yes

Runnable Scheduling

This section specifies the required runnable scheduling.

Init	Scheduling Requirements
GuardCfgAndDiagcInit1	Non-RTE Init, Called in Startup Sequence*	Function call in Startup Sequence
GuardCfgAndDiagcInit2	RTE	Once At Init (RTE)

*Refer CM100 for the start up sequence

Runnable	Scheduling Requirements	Trigger

Memory Map REQUIREMENTS

Mapping

Memory Section	Contents	Notes
CDD_GuardCfgAndDiagc_START_SEC_CODE

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Feature	RAM	ROM

Table 1: ARM Cortex R4 Memory Usage

NvM Blocks

None

Compiler Settings

Preprocessor MACRO

None

Optimization Settings

None

Appendix

None

2 - GuardCfgAndDiagc Module Design Document

Module Design Document

For

GuardCfgAndDiagc

Nov 12 , 2017

Prepared For:

Software Engineering

Nexteer Automotive,

Saginaw, MI, USA

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA
Change History

Description	Author	Version	Date
Initial Version	Avinash James	1.0	11/12/17

Table of Contents

1 Introduction 5

1.1 Purpose 5

1.2 Scope 5

2 GuardCfgAndDiagc & High-Level Description 6

3 Design details of software module 7

3.1 Graphical representation of GuardCfgAndDiagc 7

3.2 Data Flow Diagram 7

3.2.1 Component level DFD 7

3.2.2 Function level DFD 7

4 Constant Data Dictionary 8

4.1 Program (fixed) Constants 8

4.1.1 Embedded Constants 8

5 Software Component Implementation 9

5.1 Sub-Module Functions 9

5.1.1 Init: GuardCfgAndDiagcInit1 9

5.1.1.1 Design Rationale 9

5.1.1.2 Module Outputs 9

5.1.2 Init: GuardCfgAndDiagcInit2 9

5.1.2.1 Design Rationale 9

5.1.2.2 Module Outputs 9

5.1.3 Per: None 9

5.2 Server Runables 9

5.3 Interrupt Functions 9

5.4 Module Internal (Local) Functions 9

5.4.1 PegInin 9

5.4.1.1 Design Rationale 9

5.4.1.2 Processing 9

5.4.2 PbgInin 10

5.4.2.1 Design Rationale 10

5.4.2.2 Processing 10

5.4.3 FrGuardInin 10

5.4.3.1 Design Rationale 10

5.4.3.2 Processing 10

5.4.4 GlbRamGuardInin 10

5.4.4.1 Design Rationale 10

5.4.4.2 Processing 10

5.5 GLOBAL Function/Macro Definitions 10

5.5.1 GLOBAL Function #1 10

5.5.1.1 Design Rationale 11

5.5.1.2 Processing 11

6 Known Limitations with Design 12

7 UNIT TEST CONSIDERATION 13

Appendix A Abbreviations and Acronyms 14

Appendix B Glossary 15

Appendix C References 16

Introduction

Purpose

Scope

The following definitions are used throughout this document:

Shall: indicates a mandatory requirement without exception in compliance.
Should: indicates a mandatory requirement; exceptions allowed only with documented justification.
May: indicates an optional action.

GuardCfgAndDiagc & High-Level Description

See FDD

Design details of software module

Graphical representation of GuardCfgAndDiagc

Data Flow Diagram

Component level DFD

See FDD

Function level DFD

See FDD

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Constant Name	Resolution	Units	Value
PROTNLOCKENA_CNT_U32	1	uint32	0x80000000UL
GLBRAMGUARDENA_CNT_U32	1	uint32	0x40000000UL
GLBRAMGUARDRSTVAL_CNT_U32	1	uint32	0x07FFFE10UL
GLBRAMGUARD0BASADRREG_CNT_U32	1	uint32	0x00027E00UL
GLBRAMGUARD0VALADRREG_CNT_U32	1	uint32	0x00000000UL
SPID0_CNT_U32	1	uint32	0x00000001UL
SPID1_CNT_U32	1	uint32	0x00000002UL
SPID2_CNT_U32	1	uint32	0x00000004UL
SPID3_CNT_U32	1	uint32	0x00000008UL
SPID4_CNT_U32	1	uint32	0x00000010UL
SPID5_CNT_U32	1	uint32	0x00000020UL
SPID6_CNT_U32	1	uint32	0x00000040UL
SPID7_CNT_U32	1	uint32	0x00000080UL
ALLSPIDDI_CNT_U32	1	uint32	0x00000000UL
HISPDBUSGUARDREADENAPE1_CNT_U32	1	uint32	0x0605FE1BUL
HISPDBUSGUARDWRENAPE1_CNT_U32	1	uint32	0x0605FE17UL
PBGREADENAPE1_CNT_U32	1	uint32	0x0605FE1BUL
PBGWRENAPE1_CNT_U32	1	uint32	0x0605FE17UL
PBGREADENAPE1ANDPE4_CNT_U32	1	uint32	0x0625FE1BUL
PBGWRENAPE1ANDPE4_CNT_U32	1	uint32	0x0625FE17UL
PBGREADALLPEDI_CNT_U32	1	uint32	0x0601FE1BUL
PBGWRALLPEDI_CNT_U32	1	uint32	0x0601FE17UL

Software Component Implementation

Sub-Module Functions

Init: GuardCfgAndDiagcInit1

Design Rationale

Non-RTE function for Guard configuration initialization of PEG, IPG, GRG,HBG and PBG so that guard protection can be initialized and enabled before the RTE is started

Module Outputs

Configuration registers for PEG, IPG,GRG,HRG and PBG

Init: GuardCfgAndDiagcInit2

Design Rationale

RTE Empty function for purposes of memory mapping

See FDD for more.

Module Outputs

None

Per: None

Server Runables

None

Interrupt Functions

None

Module Internal (Local) Functions

PegInin

Function Name	PegInin	Type	Min	Max
Arguments Passed	None	-	-	-
Return Value	None	-	-	-

Design Rationale

Sub function to set Peg Register configuration.

Processing

None

PbgInin

Function Name	PbgInin	Type	Min	Max
Arguments Passed	None	-	-	-
Return Value	None	-	-	-

Design Rationale

Sub function to set PBG Register configuration.

Processing

None

HiSpdBusGuardInin

Function Name	HiSpdBusGuardInin	Type	Min	Max
Arguments Passed	None	-	-	-
Return Value	None	-	-	-

Design Rationale

Sub function to set HBG Register configuration.

Processing

None

GlbRamGuardInin

Function Name	GlbRamGuardInin	Type	Min	Max
Arguments Passed	None	-	-	-
Return Value	None	-	-	-

Design Rationale

Sub function to set GRG Register configuration.

Processing

None

GLOBAL Function/Macro Definitions

GLOBAL Function #1

Function Name	Type	Min	Max
Arguments Passed

Return Value

Design Rationale

Processing

Known Limitations with Design

None

UNIT TEST CONSIDERATION

None

Abbreviations and Acronyms

Abbreviation or Acronym	Description

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

ISO 9000
ISO/IEC 12207
ISO/IEC 15504
Automotive SPICE® Process Reference Model (PRM)
Automotive SPICE® Process Assessment Model (PAM)
ISO/IEC 15288
ISO 26262
IEEE Standards
SWEBOK
PMBOK
Existing Nexteer Automotive documentation

Term	Definition	Source
MDD	Module Design Document
DFD	Data Flow Diagram

References

Ref. #	Title	Version
1	AUTOSAR Specification of Memory Mapping (Link:AUTOSAR_SWS_MemoryMapping.pdf)	v1.3.0 R4.0 Rev 2
2	MDD Guideline	EA4 01.00.01
3	Software Naming Conventions.doc	2.0
4	Software Design and Coding Standards.doc	2.1

3 - GuardCfgAndDiagc_PeerReviewChecklist

Overview

Summary Sheet
Synergy Project
Src-GuardCfgAndDiagcNonRte
PolySpace
Integration Manual

Sheet 1: Summary Sheet

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Summary Sheet

Component Short Name:

Windows User: Intended Use: Identify which component is being reviewed. This should match the component short name from the DataDict.m fileand the middle part of the Synergy project name, e.g. Assi for the SF001A_Assi_Impl Synergy project

GuardCfgAndDiagc

Revision / Baseline:

Windows User: Intended Use: Identify the implementation baseline name intended to be used for the changed component when changes are approved E.g. SF001A_Assi_Impl_1.2.0

CM107B_GuardCfgAndDiagc_Impl_1.1.0

Change Owner:

Windows User: Intended Use: Identify the developer who made the change(s) being reviewed

Avinash James

Work CR ID:

Windows User: Intended Use: Identify the Implementation Work CR whose work is being reviewed (may be more than one)

EA4#18561

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

Check the file types that needed modification for the Work CR(s); macros for the check boxes will populate the appropriate checklist tabs for the review.

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

At start of review, all items below should be marked "No". At the end of the review, all items should be marked "Yes" or "N/A" where N/A indicates the reviewers have reviewed the existing (unchanged) item and confirmed no updates were needed for the Work CR(s).

N/A

MDD

Yes

Source Code

Yes

PolySpace

Yes

Integration Manual

N/A

Davinci Files

Comments:

General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include SWC Owner and/or SWC Design author and Integrator and/or SW Lead as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.

Each peer review shall start with a clean copy of the latest peer review checklist template. Before the peer review, the change owner shall:
o Review the previous component peer review and copy any relevant comments to the new review sheet.
o Review all checklist items and make all corrections needed, so that the component is ready for peer review. The expectation is that peer review should find very few issues,
because the change owner has already used the checklist to ensure the component changes are complete and correct.
o Fill in all file name and version information as needed on peer review checklist tabs (file names may be copied from the previous peer review where appropriate)
o Fill in checklist answers (Yes/No/NA pulldowns) ONLY on those items which are NA for the current change. All other checklist items should be blank going into the review
meeting.

During the peer review meeting:
o For each page of the review, first review the items already marked as N/A for this change, to confirm that reviewers agree with this assessment; change the checklist box to
blank if it is found that the item does apply.
o Then review the items with the checklist box blank. After reviewing each of these items, the checklist box will be marked as "Yes", or the checklist box will be marked as
"No" with needed rework indicated or with rationale indicated.
o If any items are marked "No" with rationale indicated, this must be approved by a software supervisor or the software manager; there is a line in the "Review Board" section
of each tab to indicate who approved the "No" items on that tab.

Sheet 2: Synergy Project

Rev 2.00

29-Nov-17

Peer Review Meeting Log (Component Synergy Project Review)

Quality Check Items:

Rationale is required for all answers of No

New baseline version name from Summary Sheet follows

Yes

Comments:

naming convention

Project contains necessary subprojects

Yes

Comments:

Project contains the correct version of subprojects

Yes

Comments:

Design subproject is correct version

Yes

Comments:

.gpj file in tools folder matches .gpj generated by TL109 script

Yes

Comments:

File/folder structure is correct per documentation in

Yes

Comments:

TL109A_SwcSuprt

General Notes / Comments:

Review Board:

Change Owner:

Avinash James

Review Date :

01/04/18

Lead Peer Reviewer:

Shruthi Raghavan

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Rationale/justification for items marked "No" approved by:

Sheet 3: Src-GuardCfgAndDiagcNonRte

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Meeting Log (Source Code Review)

Source File Name:

CDD_GuardCfgAndDiagcNonRte.c

Source File Revision:

Windows User: Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) 2

Header File Name:

Header File Revision:

Windows User: Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project)

MDD Name:

GuardCfgAndDiagc Module Design Document.docx

Revision:

Windows User: Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) 1

SWC Design Name:

CM107B_GuardCfgAndDiagc_Design

Revision:

Windows User: Intended Use: For FDDs, list the Synergy baseline number (just the number part of the Synergy baseline name) of the FDD baseline being implemented. E.g., for SF001A_Assi_Design_1.3.1, this field would say "1.3.1" 1.2.0

Quality Check Items:

Rationale is required for all answers of No

EA4 Common Naming Convention followed:

Version:1.01

EA4 Software Naming Convention followed:

Version:1.02

for variable names

N/A

Comments:

for constant names

N/A

Comments:

for function names

N/A

Comments:

for other names (component, memory

Yes

Comments:

mapping handles, typedefs, etc.)

Linker Symbol

Verified no possibility of uninitialized variables being

Yes

Comments:

written to component outputs or IRVs

Any requirements traceability tags have been removed

N/A

Comments:

from at least the changed areas of code

All variables are declared at the function level.

Yes

Comments:

Synergy version matches change history

kzshz2: Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). Rationale: There have been many occassions where versions were not updated in files and as a result Unit Test were referencing wrong versions. This often time leads to the need to re-run of batch tests.

Yes

Comments:

and Version Control version in file comment block

Change log contains detailed description of changes

Yes

Comments:

(including any anomaly number(s) being fixed) and

Work CR number

Code accurately implements SWC Design (Document or Model)

Yes

Comments:

in all areas where code was changed and/or Simulink

model was color-coded as changed and/or mentioned

in SWC Design change log. (This item includes looking at all

layers of Simulink model for possible color coding not

reflected at a higher level, and includes looking at any

intermediate SWC Design versions between the version being

implemented and the version that was included as a

subproject in the previous implementation.)

Code comparison against previous version matches

Yes

Comments:

changes needed as described by the work CR(s), all

parent CRs and parent anomalies, and the SWC

Design change log.

Verified no Compiler Errors or Warnings

KMC: Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). Rationale: This is needed to ensure there will be no errors discovered at the time of integration. A Sandox project should be used.

Yes

Comments:

(and verified for all possible combinations

of any conditionally compiled code)

Component.h is included

Yes

Comments:

All other includes are actually needed. (System includes

Yes

Comments:

only allowed in Nexteer library components)

Software Design and Coding Standards followed:

Windows User: Intended Use: list version/revision of latest released Software Design and Coding Standards document. Version:2.01

Code comments are clear, correct, and adequate

Yes

Comments:

and have been updated for the change: [N40] and

all other rules in the same section as rule [N40],

plus [N75], [N12], [N23], [N33], [N37], [N38],

[N48], [N54], [N77], [N79], [N72]

Source file (.c and .h) comment blocks are per

Yes

Comments:

standards and contain correct information: [N41], [N42]

Function comment blocks are per standards and

Yes

Comments:

contain correct information: [N43]

Code formatting (indentation, placement of

Yes

Comments:

braces, etc.) is per standards: [N5], [N55], [N56],

[N57], [N58], [N59]

Embedded constants used per standards; no

Yes

Comments:

"magic numbers": [N12]

Memory mapping for non-RTE code

Yes

Comments:

is per standard

All access of motor control loop data uses macros

N/A

Comments:

generated by the motor control manager

All loops have termination conditions that ensure

N/A

Comments:

finite loop iterations: [N63]

All divides protect against divide by zero

N/A

Comments:

if needed: [N65]

All integer division and modulus operations

N/A

Comments:

handle negative numbers correctly: [N76]

All typecasting and fixed point arithmetic,

N/A

Comments:

including all use of fixed point macros and

timer functions, is correct and has no possibility

of unintended overflow or underflow: [N66]

All float-to-unsigned conversions ensure the.

N/A

Comments:

float value is non-negative: [N67]

All conversions between signed and unsigned

N/A

Comments:

types handle msb==1 as intended: [N78]

All pointer dereferencing protects against

N/A

Comments:

null pointer if needed: [N70]

Component outputs are limited to the legal range

N/A

Comments:

defined in the SWC Design DataDict.m file : [N53]

All code is mapped with SWC Design (all SWC

Yes

Comments:

Design subfunctions and/or model blocks identified

with code comments; all code corresponds to

some SWC Design subfunction and/or model block):

[N40]

Any other violations of design and coding

N/A

Comments:

standards noticed during the review are noted in the

comments section for rework.

Anomaly or Design Work CR created

N/A

Comments: List Anomaly or CR numbers

for any SWC Design corrections needed

General Notes / Comments:

Sandbox has been manually modified to include P1XC register includes- Approved by Steven Horwarth 1/4/2018

Review Board:

Change Owner:

Avinash James

Review Date :

01/04/18

Lead Peer Reviewer:

Shruthi R

Approved by Reviewer(s):

Yes

SWC owner and/or
SWC Design author:

Comments:

Integrator and or
SW lead:

Xin Liu

Comments:

Unit test co-ordinator:

Comments:

Other Reviewer(s):

Rationale/justification for items marked "No" approved by:

Sheet 4: PolySpace

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Meeting Log (PolySpace Review)

Source File Name:

CDD_GuardCfgAndDiagcNonRte.c

Source File Revision:

Source File Name:

CDD_GuardCfgAndDiagc.c

Source File Revision:

Source File Name:

Source File Revision:

EA4 Static Analysis Compliance Guideline version:

01.04.00

Poly Space version:

Windows User: eg. 2013b

2013b

TL109A sub project version:

2.2

Quality Check Items:

Rationale is required for all answers of No

tools/local folders' header files are appropriate and

Yes

Comments:

function prototypes match the latest component version

100% Compliance to the EA4 Static Analysis

Yes

Comments:

Compliance Guideline

Are previously added justification and deviation

Yes

Comments:

comments still appropriate

Do all MISRA deviation comments use approved

Yes

Comments:

deviation tags

For any component source files (.c, .h, generated Cfg.c and Cfg.h)

N/A

Comments:

with conditional compilation, has Polyspace been run with all

combinations of build constants that can be used together in a build?

(Note which conditional compilation results have been archived)

Cyclomatic complexity and Static path count OK

Yes

Comments:

for all functions in the component per Design

and Coding Standards rule [N47]

General Notes / Comments:

8.10 warning exists for the Trusted function call - Analyzed to be okay - Done 11/17/2017
Polyspace projects manually modified to include P1XC register includes. Approved by Steven Horwarth -1/4/2018

Review Board:

Change Owner:

Avinash James

Review Date :

01/04/18

Lead Peer Reviewer:

Shruthi R

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Rationale/justification for items marked "No" approved by:

Sheet 5: Integration Manual

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Meeting Log (Integration Manual Review)

Integration Manual Name:

kzshz2: Intended Use: Identify which file is being reviewed Rationale: Required for traceability. It will help to ensure this sheet is not attached to the wrong design review form. GuardCfgAndDiagc Integration Manual.doc

Integration Manual Revision:

kzshz2: Intended Use: Identify which version of the integration manual has been reviewed. 2

Quality Check Items:

Rationale is required for all answers of No

Synergy version matches header

Yes

Comments:

Latest template used

Yes

Comments:

Change log contains detailed description of changes

Yes

Comments:

Changes Highlighted (for Integrator)

Yes

Comments:

General Notes / Comments:

Review Board:

Change Owner:

Avinash James

Review Date :

01/04/18

Lead Peer Reviewer:

Shruthi R

Approved by Reviewer(s):

Yes

Integrator and or
SW lead:

Xin Liu

Comments:

Other Reviewer(s):

Rationale/justification for items marked "No" approved by: