Sr. No.	Title	Version
1	EA4 Software Naming Conventions	01.01.00
2	Software Design and Coding Standards	2.1
3	CM765A_Uart1CfgAndUse_Design	See Synergy Sub Project Version

Dependencies

SWCs

Module	Required Feature
AR350A ImcArbn	All the IMC signal group definitions

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

Uart1CfgAndUseInin - To be defined as a trusted function as the DTS Channel master registers need to be configured in the supervisor mode.

Configuration REQUIREMeNTS

Build Time Config

Modules	Notes
IMCARBN_NROF2MILLISECRATEGROUP_CNT_U08	Takes unsigned value
IMCARBN_NROF10MILLISECRATEGROUP_CNT_U08	Takes unsigned value
IMCARBN_NROF100MILLISECRATEGROUP_CNT_U08	Takes unsigned value

Configuration Files to be provided by Integration Project

None

Da Vinci Parameter Configuration Changes

Parameter	Notes	SWC
None

DaVinci Interrupt Configuration Changes

ISR Name	VIM #	Priority Dependency	Notes
None

Manual Configuration Changes

Constant	Notes	SWC
None

EXCLUSIVE AREAS

Exclusive Area

Notes

SWC

ExclsvAr1Uart1DrvrTxRxBuf

Exclusive area needs to protect access to Transmit and Receive buffers from asynchronous updates by server runnables and periodic updates by tasks.

Integrator needs to verify if client calls to server runnables can interrupt periodics and set up exclusive area to properly protect access. If exclusive area is needed, at minimum it must disable OS Task scheduling (It is assumed that all clients call occurs in OS Tasks).

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

None

Required Global Data Outputs

None

Specific Include Path present

Yes

Runnable Scheduling

This section specifies the required runnable scheduling.

Init	Scheduling Requirements	Trigger
Uart1CfgAndUseInit1	None	RTE(Init)

Runnable	Scheduling Requirements	Trigger
Uart1CfgAndUsePer1	None	RTE(2ms)
Uart1CfgAndUsePer2	None	RTE(2ms)
Uart1CfgAndUsePer3	None	RTE(10ms)
Uart1CfgAndUsePer4	None	RTE(100ms)

Memory Map REQUIREMENTS

Mapping

Memory Section	Contents	Notes
CDD_Uart1CfgAndUse_START_SEC_CODE	Functions
CDD_Uart1CfgAndUse_START_SEC_VAR_INIT_128	Tx Buffer
CDD_Uart1CfgAndUse_DmaWrite_START_SEC_VAR_INIT_128	Rx Buffer

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Feature	RAM	ROM
None

Table 1: ARM Cortex R4 Memory Usage

NvM Blocks

None

Compiler Settings

Preprocessor MACRO

None

Optimization Settings

None

Appendix

Header file “CDD_Uart1CfgAndUse.h” shall be included inside Rte_UserTypes.h which will provide typedef Ary1D_u8_2048_Uart1CfgAndUse.

2 - Uart1CfgAndUse_MDD

Module Design Document

For

Uart1CfgAndUse

Jan 11, 2018

Prepared For:

Software Engineering

Nexteer Automotive,

Saginaw, MI, USA

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA
Change History

Description	Author	Version	Date
Initial Version	Krzysztof Byrski	1	15-June-2017
Updated local functions	Avinash James	2	11-Jan-2018

Table of Contents

1 Introduction 4

1.1 Purpose 4

1.2 Scope 4

2 Uart1CfgAndUse & High-Level Description 5

3 Design details of software module 6

3.1 Graphical representation of Uart1CfgAndUse 6

3.2 Data Flow Diagram 6

3.2.1 Component level DFD 6

3.2.2 Function level DFD 6

4 Constant Data Dictionary 7

4.1 Program (fixed) Constants 7

4.1.1 Embedded Constants 7

5 Software Component Implementation 8

5.1 Sub-Module Functions 8

5.1.1 Init: Uart1CfgAndUseInit1 8

5.1.2 Per: Uart1CfgAndUsePer1 8

5.1.3 Per: Uart1CfgAndUsePer2 8

5.1.4 Per: Uart1CfgAndUsePer3 8

5.1.5 Per: Uart1CfgAndUsePer4 9

5.2 Server Runables 9

5.3 Interrupt Functions 9

5.4 Module Internal (Local) Functions 9

5.4.1 RollOverAdd 9

5.4.2 UpdDtsTxReg 10

5.4.3 UpdDtsRxReg 10

5.5 GLOBAL Function/Macro Definitions 10

6 Known Limitations with Design 11

7 UNIT TEST CONSIDERATION 12

Appendix A Abbreviations and Acronyms 13

Appendix B Glossary 14

Appendix C References 15

Introduction

Purpose

Module Design Document for CM765A_Uart1CfgAndUse.

Scope

The following definitions are used throughout this document:

Shall: indicates a mandatory requirement without exception in compliance.
Should: indicates a mandatory requirement; exceptions allowed only with documented justification.
May: indicates an optional action.

Uart1CfgAndUse & High-Level Description

Refer FDD.

Design details of software module

Graphical representation of Uart1CfgAndUse

Data Flow Diagram

Refer FDD

Component level DFD

None

Function level DFD

None

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Constant Name	Resolution	Units	Value
ROLLGCNTCHK_CNT_U08	1	Cnt	255
DATABYTE0_CNT_U08	1	Cnt	0
DATABYTE1_CNT_U08	1	Cnt	1
DATABYTE2_CNT_U08	1	Cnt	2
DATABYTE3_CNT_U08	1	Cnt	3
DATABYTE4_CNT_U08	1	Cnt	4
DATABYTE5_CNT_U08	1	Cnt	5
DATABYTE6_CNT_U08	1	Cnt	6
DATABYTE7_CNT_U08	1	Cnt	7
DATABYTE8_CNT_U08	1	Cnt	8
MASKLOWR16BITOFUINT32_CNT_U16	1	Cnt	65535

MAXSIGGROUPFORTX_CNT_U08	1	Cnt	9
TWO_CNT_U08	1	Cnt	2
UART1RXMAXBUFSIZE_CNT_U08	1	Cnt	144
UART1TXBUFSIZE_CNT_U08	1	Cnt	80
RLN31LBRP01BRP_CNT_U08	1	Cnt	4
DTS103CM_CNT_U32	1	Cnt	0x20120000
DTS102CM_CNT_U32	1	Cnt	0x200E0000
DTTCT103_CNT_U32	1	Cnt	256
DTTC102_CNT_U32	1	Cnt	9438624
DTTCT102_CNT_U32	1	Cnt	6720
DTRTC102_CNT_U32	1	Cnt	9438624

Software Component Implementation

Sub-Module Functions

The sub-module functions are grouped based on similar functionality that needs to be executed in a given “State” of the system (refer States and Modes). For a given module, the MDD will identify the type and number of sub-modules required. The sub-module types are described below.

Init: Init1

Design Rationale

Refer FDD

Module Outputs

Refer FDD

Per: Per1

Design Rationale

Refer FDD

Store Module Inputs to Local copies

Refer FDD

(Processing of function)………

Refer FDD

Store Local copy of outputs into Module Outputs

Refer FDD

Per: Per2

Design Rationale

Refer FDD

Store Module Inputs to Local copies

Refer FDD

(Processing of function)………

Refer FDD

Store Local copy of outputs into Module Outputs

Refer FDD

Per: Per3

Design Rationale

Refer FDD

Store Module Inputs to Local copies

Refer FDD

(Processing of function)………

Refer FDD

Store Local copy of outputs into Module Outputs

Refer FDD

Per: Per4

Design Rationale

Refer FDD

Store Module Inputs to Local copies

Refer FDD

(Processing of function)………

Refer FDD

Store Local copy of outputs into Module Outputs

Refer FDD

Server Runables

None

Interrupt Functions

None

Module Internal (Local) Functions

RollOverAdd

Function Name	RollOverAdd	Type	Min	Max
Arguments Passed	Input1_Cnt_T_u08	uint8	0	255
	Input2_Cnt_T_u08	uint8	0	255
Return Value	Output_Cnt_T_u08	uint8	0	143

Design Rationale

Refer FDD

Processing

Refer FDD

UpdDtsTxReg

Function Name	UpdDtsTxReg	Type	Min	Max
Arguments Passed	Uart1GlbTx_Cnt_T_u08	uint8	0	72
Return Value	None	-	-	-

Design Rationale

Refer FDD

Processing

Refer FDD

Uart1Diagc

Function Name	Uart1Diagc	Type	Min	Max
Arguments Passed	Uart1RxDataCntr	uint8	0	255
Return Value	None	-	-	-

Design Rationale

Refer Uart1RxDataCntr block in FDD

Processing

Refer FDD

GLOBAL Function/Macro Definitions

None

Known Limitations with Design

The client call SetRxSigGroup has one argument Buf which is listed as Output in the design but implemented correctly as Input. This is an update to AR350A and is not done as of today.

The component makes use of static component level variables which are needed for the special DMA mapping .

UNIT TEST CONSIDERATION

Code prover flags out of bound array access as it considers range of the index variable outside the array bounds. But this has been functionally checked to be within the limits.

Abbreviations and Acronyms

Abbreviation or Acronym	Description
-	-

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

ISO 9000
ISO/IEC 12207
ISO/IEC 15504
Automotive SPICE® Process Reference Model (PRM)
Automotive SPICE® Process Assessment Model (PAM)
ISO/IEC 15288
ISO 26262
IEEE Standards
SWEBOK
PMBOK
Existing Nexteer Automotive documentation

Term	Definition	Source
MDD	Module Design Document
DFD	Data Flow Diagram

References

Ref. #	Title	Version
1	AUTOSAR Specification of Memory Mapping (Link:AUTOSAR_SWS_MemoryMapping.pdf)	v1.3.0 R4.0 Rev 2
2	MDD Guideline	EA4 01.00.01
3	Software Naming Conventions	01.01.00
4	Software Design and Coding Standards	2.1
5	CM765A_Uart1CfgAndUse_Design	See Synergy Sub Project Version

3 - Uart1CfgAndUse_PeerReviewChecklist

Overview

Summary Sheet
Synergy Project
Davinci Files
CDD_Uart1CfgAndUse.c
MDD
PolySpace
Integration Manual

Sheet 1: Summary Sheet

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Summary Sheet

Component Short Name:

Windows User: Intended Use: Identify which component is being reviewed. This should match the component short name from the DataDict.m fileand the middle part of the Synergy project name, e.g. Assi for the SF001A_Assi_Impl Synergy project

Uart1CfgAndUse

Revision / Baseline:

Windows User: Intended Use: Identify the implementation baseline name intended to be used for the changed component when changes are approved E.g. SF001A_Assi_Impl_1.2.0

CM765A_Uart1CfgAndUse_Impl_1.3.0

Change Owner:

Windows User: Intended Use: Identify the developer who made the change(s) being reviewed

Avinash James

Work CR ID:

Windows User: Intended Use: Identify the Implementation Work CR whose work is being reviewed (may be more than one)

EA4#20047,EA4#20471

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

Check the file types that needed modification for the Work CR(s); macros for the check boxes will populate the appropriate checklist tabs for the review.

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

At start of review, all items below should be marked "No". At the end of the review, all items should be marked "Yes" or "N/A" where N/A indicates the reviewers have reviewed the existing (unchanged) item and confirmed no updates were needed for the Work CR(s).

N/A

MDD

Yes

Source Code

Yes

PolySpace

N/A

Integration Manual

N/A

Davinci Files

Comments:

General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include SWC Owner and/or SWC Design author and Integrator and/or SW Lead as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.

Each peer review shall start with a clean copy of the latest peer review checklist template. Before the peer review, the change owner shall:
o Review the previous component peer review and copy any relevant comments to the new review sheet.
o Review all checklist items and make all corrections needed, so that the component is ready for peer review. The expectation is that peer review should find very few issues,
because the change owner has already used the checklist to ensure the component changes are complete and correct.
o Fill in all file name and version information as needed on peer review checklist tabs (file names may be copied from the previous peer review where appropriate)
o Fill in checklist answers (Yes/No/NA pulldowns) ONLY on those items which are NA for the current change. All other checklist items should be blank going into the review
meeting.

During the peer review meeting:
o For each page of the review, first review the items already marked as N/A for this change, to confirm that reviewers agree with this assessment; change the checklist box to
blank if it is found that the item does apply.
o Then review the items with the checklist box blank. After reviewing each of these items, the checklist box will be marked as "Yes", or the checklist box will be marked as
"No" with needed rework indicated or with rationale indicated.
o If any items are marked "No" with rationale indicated, this must be approved by a software supervisor or the software manager; there is a line in the "Review Board" section
of each tab to indicate who approved the "No" items on that tab.

Sheet 2: Synergy Project

Rev 2.00

29-Nov-17

Peer Review Meeting Log (Component Synergy Project Review)

Quality Check Items:

Rationale is required for all answers of No

New baseline version name from Summary Sheet follows

Yes

Comments:

naming convention

Project contains necessary subprojects

Yes

Comments:

Project contains the correct version of subprojects

Yes

Comments:

Design subproject is correct version

Yes

Comments:

.gpj file in tools folder matches .gpj generated by TL109 script

Yes

Comments:

File/folder structure is correct per documentation in

Yes

Comments:

TL109A_SwcSuprt

General Notes / Comments:

Review Board:

Change Owner:

Avinash James

Review Date :

02/10/18

Lead Peer Reviewer:

Matt Leser

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Rationale/justification for items marked "No" approved by:

Sheet 3: Davinci Files

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Meeting Log (Davinci Review)

Quality Check Items:

Rationale is required for all answers of No

Only StdDef Port interfaces and datatypes are used

Yes

Comments:

(compare against TL107B to ensure only implementation

data types are used)

OBSOLETE/OBSELETE doesn’t appear in any arxml file

Yes

Comments:

Do all port interface names end in PortIf and a sequence

Yes

Comments:

number

Non-program-specific components saved

Yes

Comments:

in Autosar 4.0.3 format

For components with generated configurable content:

N/A

Comments:

*Cfg.arxml.TT: Verfied Davinci Configurator imported the

change correctly

*Cfg.h.TT: Verfied Davinci Configurator generates

N/A

Comments:

the configuration header file(s) correctly

All changed files have been compared against previous

kzshz2: Intended Use: Identify if previous version was compared and only the expected change(s) was present. This is for text files only, not binary or GUIs Rationale: This is helpful in identifying unapproved (intended or mistaken) changes.

Yes

Comments:

versions (If available) and changes match changes

needed as described by the work CR(s), all parent CRs

and parent anomalies, and the SWC Design change log.

Davinci files accurately implement SWC Design (DataDict.m

Yes

Comments:

file) in all areas where arxml was changed and/or the

DataDict.m file was changed as shown by

comparing the DataDict.m from the current SWC Design

with the DataDict.m used in the previous implementation.

(This is NOT always the predecessor.)

Automated validation check is performed with no issues found

Yes

Comments:

Naming conventions followed. All names should

Yes

Comments:

match DataDict.m

Sender/Receiver port properties match DataDict.m file

N/A

Comments:

(name, data type, direction)

Calibration port properties match DataDict.m file

N/A

Comments:

(name, data type)

Sender/Receiver port initialization values match

N/A

Comments:

DataDict.m file and have been converted to counts

for fixed point types

Calibration port initialization values match

N/A

Comments:

DataDict.m file and have been converted to counts

for fixed point types

Mapping set and all unused items have been

Yes

Comments:

removed

All sender/receiver port read/writes using "Write (explicit)"

N/A

Comments:

and "Read (explicit by argument)"(List justification if not)

Runnable calling frequencies match DataDict.m file

Yes

Comments:

Runnable port access matches the DataDict.m file

N/A

Comments:

DataDict.m display variables: created as

N/A

Comments:

PerInstanceMemory. Name and data type match DataDict.m file.

Per Instance Memory names and data types

Yes

Comments:

match DataDict.m file

NVM blocks match DataDict.m file

N/A

Comments:

(Named per naming convention. Default block

used if specified in DataDict.m file. Data type

matches DatatDict.m file)

Component is correct component type

Yes

Comments:

General Notes / Comments:

Removed a PIM. That was the whole change

Review Board:

Change Owner:

Avinash James

Review Date :

02/10/18

Component Type :

CDD

Lead Peer Reviewer:

Matt Leser

Approved by Reviewer(s):

Yes

Integrator and or
SW lead:

Comments:

Other Reviewer(s):

Raghavendran Mohan

Rationale/justification for items marked "No" approved by:

Sheet 4: CDD_Uart1CfgAndUse.c

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Meeting Log (Source Code Review)

Source File Name:

CDD_Uart1CfgAndUse.c

Source File Revision:

Windows User: Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) 3

Header File Name:

CDD_Uart1CfgAndUse.h

Header File Revision:

Windows User: Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) 1

MDD Name:

Uart1CfgAndUse_MDD.docx

Revision:

Windows User: Intended Use: Synergy version number of the file being reviewed. (Version number that Synergy displays on the checked out or unmodified file in the working project) 2

SWC Design Name:

CM765A_Uart1CfgAndUse_Design

Revision:

Windows User: Intended Use: For FDDs, list the Synergy baseline number (just the number part of the Synergy baseline name) of the FDD baseline being implemented. E.g., for SF001A_Assi_Design_1.3.1, this field would say "1.3.1" 1.4.0

Quality Check Items:

Rationale is required for all answers of No

EA4 Common Naming Convention followed:

Version:1.01

EA4 Software Naming Convention followed:

Version:1.02

for variable names

N/A

Comments:

for constant names

Yes

Comments:

for function names

N/A

Comments:

for other names (component, memory

N/A

Comments:

mapping handles, typedefs, etc.)

Verified no possibility of uninitialized variables being

Yes

Comments:

written to component outputs or IRVs

Any requirements traceability tags have been removed

N/A

Comments:

from at least the changed areas of code

All variables are declared at the function level.

Yes

Comments:

Synergy version matches change history

kzshz2: Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). Rationale: There have been many occassions where versions were not updated in files and as a result Unit Test were referencing wrong versions. This often time leads to the need to re-run of batch tests.

Yes

Comments:

and Version Control version in file comment block

Change log contains detailed description of changes

Yes

Comments:

(including any anomaly number(s) being fixed) and

Work CR number

Code accurately implements SWC Design (Document or Model)

Yes

Comments:

in all areas where code was changed and/or Simulink

model was color-coded as changed and/or mentioned

in SWC Design change log. (This item includes looking at all

layers of Simulink model for possible color coding not

reflected at a higher level, and includes looking at any

intermediate SWC Design versions between the version being

implemented and the version that was included as a

subproject in the previous implementation.)

Code comparison against previous version matches

Yes

Comments:

changes needed as described by the work CR(s), all

parent CRs and parent anomalies, and the SWC

Design change log.

Verified no Compiler Errors or Warnings

KMC: Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). Rationale: This is needed to ensure there will be no errors discovered at the time of integration. A Sandox project should be used.

Yes

Comments:

(and verified for all possible combinations

of any conditionally compiled code)

Component.h is included

Yes

Comments:

All other includes are actually needed. (System includes

Yes

Comments:

only allowed in Nexteer library components)

Software Design and Coding Standards followed:

Windows User: Intended Use: list version/revision of latest released Software Design and Coding Standards document. Version:2.01

Code comments are clear, correct, and adequate

Yes

Comments:

and have been updated for the change: [N40] and

all other rules in the same section as rule [N40],

plus [N75], [N12], [N23], [N33], [N37], [N38],

[N48], [N54], [N77], [N79], [N72]

Source file (.c and .h) comment blocks are per

Yes

Comments:

standards and contain correct information: [N41], [N42]

Function comment blocks are per standards and

Yes

Comments:

contain correct information: [N43]

Code formatting (indentation, placement of

Yes

Comments:

braces, etc.) is per standards: [N5], [N55], [N56],

[N57], [N58], [N59]

Embedded constants used per standards; no

Yes

Comments:

"magic numbers": [N12]

Memory mapping for non-RTE code

N/A

Comments:

is per standard

All access of motor control loop data uses macros

N/A

Comments:

generated by the motor control manager

All loops have termination conditions that ensure

N/A

Comments:

finite loop iterations: [N63]

All divides protect against divide by zero

N/A

Comments:

if needed: [N65]

All integer division and modulus operations

N/A

Comments:

handle negative numbers correctly: [N76]

All typecasting and fixed point arithmetic,

N/A

Comments:

including all use of fixed point macros and

timer functions, is correct and has no possibility

of unintended overflow or underflow: [N66]

All float-to-unsigned conversions ensure the.

N/A

Comments:

float value is non-negative: [N67]

All conversions between signed and unsigned

N/A

Comments:

types handle msb==1 as intended: [N78]

All pointer dereferencing protects against

N/A

Comments:

null pointer if needed: [N70]

Component outputs are limited to the legal range

N/A

Comments:

defined in the SWC Design DataDict.m file : [N53]

All code is mapped with SWC Design (all SWC

Yes

Comments:

Design subfunctions and/or model blocks identified

with code comments; all code corresponds to

some SWC Design subfunction and/or model block):

[N40]

Any other violations of design and coding

N/A

Comments:

standards noticed during the review are noted in the

comments section for rework.

Anomaly or Design Work CR created

N/A

Comments: List Anomaly or CR numbers

for any SWC Design corrections needed

General Notes / Comments:

Sandbox has been manually modified to include P1XC register includes- Approved by Steven Horwarth 1/4/2018

Review Board:

Change Owner:

Avinash James

Review Date :

02/10/18

Lead Peer Reviewer:

Matt Leser

Approved by Reviewer(s):

Yes

SWC owner and/or
SWC Design author:

Comments:

Raghavendran Mohan

Integrator and or
SW lead:

Comments:

Unit test co-ordinator:

Comments:

Other Reviewer(s):

Rationale/justification for items marked "No" approved by:

Steven Horwarth

Sheet 5: MDD

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Meeting Log (MDD Review)

MDD Name:

Uart1CfgAndUse_MDD.docx

MDD Revision:

Source File Name:

CDD_Uart1CfgAndUse.c

Source File Revision:

Source File Name:

Source File Revision:

Source File Name:

Source File Revision:

Quality Check Items:

Rationale is required for all answers of No

Synergy version matches document

Yes

Comments:

Change log contains detailed description of changes

Yes

Comments:

Changes Highlighted (for Unit Tester)

Yes

Comments:

Diagrams have been included per MDD Guideline

Yes

Comments:

and reviewed

All Design Exceptions and Limitations are listed

Yes

Comments:

Design rationale given for all global

N/A

Comments:

data not communicated through RTE ports, per

Design and Coding Standards rules [N9] and [N10].

All implementation details that differ from the SWC

N/A

Comments:

Design are noted and explained in Design Rationale

All Unit Test Considerations have been described

Yes

Comments:

General Notes / Comments:

Review Board:

Change Owner:

Avinash James

Review Date :

02/10/18

Lead Peer Reviewer:

Krishna Anne

Approved by Reviewer(s):

Other Reviewer(s):

Rationale/justification for items marked "No" approved by:

Sheet 6: PolySpace

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Meeting Log (PolySpace Review)

Source File Name:

CDD_Uart1CfgAndUse.c

Source File Revision:

Source File Name:

CDD_Uart1CfgAndUse.h

Source File Revision:

Source File Name:

Source File Revision:

EA4 Static Analysis Compliance Guideline version:

01.04.00

Poly Space version:

Windows User: eg. 2013b

2013b

TL109A sub project version:

2.2

Quality Check Items:

Rationale is required for all answers of No

tools/local folders' header files are appropriate and

Yes

Comments:

function prototypes match the latest component version

100% Compliance to the EA4 Static Analysis

Yes

Comments:

Compliance Guideline

Are previously added justification and deviation

Yes

Comments:

comments still appropriate

Do all MISRA deviation comments use approved

Yes

Comments:

deviation tags

For any component source files (.c, .h, generated Cfg.c and Cfg.h)

N/A

Comments:

with conditional compilation, has Polyspace been run with all

combinations of build constants that can be used together in a build?

(Note which conditional compilation results have been archived)

Cyclomatic complexity and Static path count OK

Yes

Comments:

for all functions in the component per Design

and Coding Standards rule [N47]

General Notes / Comments:

8.10 warning exists for the Trusted function call - Analyzed to be okay - Done 1/11/2018
Polyspace projects manually modified to include P1XC register includes. Approved by Steven Horwarth -1/4/2018
Polyspace generated DRS and Rte_Stubs file manually modified to include the static variables and also to cortrect the mistake in AR350 - Approved by Steve 1/11/2018

Review Board:

Change Owner:

Avinash James

Review Date :

02/10/18

Lead Peer Reviewer:

Matt Leser

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Rationale/justification for items marked "No" approved by:

Steven Horwarth

Sheet 7: Integration Manual

Rev 2.00

29-Nov-17

Nexteer SWC Implementation Peer Review Meeting Log (Integration Manual Review)

Integration Manual Name:

kzshz2: Intended Use: Identify which file is being reviewed Rationale: Required for traceability. It will help to ensure this sheet is not attached to the wrong design review form. GuardCfgAndDiagc Integration Manual.doc

Integration Manual Revision:

kzshz2: Intended Use: Identify which version of the integration manual has been reviewed. 1

Quality Check Items:

Rationale is required for all answers of No

Synergy version matches header

Yes

Comments:

Latest template used

Yes

Comments:

Change log contains detailed description of changes

Yes

Comments:

Changes Highlighted (for Integrator)

N/A

Comments:

General Notes / Comments:

Review Board:

Change Owner:

Avinash James

Review Date :

02/10/18

Lead Peer Reviewer:

Shruthi R

Approved by Reviewer(s):

Yes

Integrator and or
SW lead:

Xin Liu

Comments:

Other Reviewer(s):

Rationale/justification for items marked "No" approved by: