Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

This component provides the following inline functions in NxtrMcuSuprtLib.h for use as needed in components and integration project. Note that the exact API for usage can be found in the header file.

For P1M devices:

Function Name	Description
WrProtdRegPortJ_u32	Protected Register write sequence for 32bit PortJ peripheral registers
WrProtdRegPort0_u32	Protected Register write sequence for 32bit Port0 peripheral registers
WrProtdRegPort1_u32	Protected Register write sequence for 32bit Port1 peripheral registers
WrProtdRegPort2_u32	Protected Register write sequence for 32bit Port2 peripheral registers
WrProtdRegPort3_u32	Protected Register write sequence for 32bit Port3 peripheral registers
WrProtdRegPort4_u32	Protected Register write sequence for 32bit Port4 peripheral registers
WrProtdRegPort5_u32	Protected Register write sequence for 32bit Port5 peripheral registers
WrProtdRegSys_u08	Protected Register write sequence for 8bit Sys peripheral registers
WrProtdRegSys_u32	Protected Register write sequence for 32bit Sys peripheral registers
WrProtdRegSysClmac_u32	Protected Register write sequence for 32bit Clmac peripheral registers
WrProtdRegClma0_u08	Protected Register write sequence for 8bit Clma0 peripheral registers
WrProtdRegClma1_u08	Protected Register write sequence for 8bit Clma1 peripheral registers
WrProtdRegClma2_u08	Protected Register write sequence for 8bit Clma2 peripheral registers
WrProtdRegClma3_u08	Protected Register write sequence for 8bit Clma3 peripheral registers
WrProtdRegEcmm_u08	Protected Register write sequence for 8bit Ecmm peripheral registers
WrProtdRegEcmc_u08	Protected Register write sequence for 8bit Ecmc peripheral registers
WrProtdRegEcm_u08	Protected Register write sequence for 8bit Ecm peripheral registers
WrProtdRegEcm_u16	Protected Register write sequence for 16bit Ecm peripheral registers
WrProtdRegEcm_u32	Protected Register write sequence for 32bit Ecm peripheral registers
WrProtdRegFlmd_u32	Protected Register write sequence for 32bit Flmd peripheral registers
NxtrSwRst	API to issue a Nexteer Defined Software Reset
NxtrSwRstFromExcpn	API to issue a Nexteer Defined Software Reset for resetting from a hardware exception source

For P1XC devices:

Function Name	Description
WrProtdRegEcmm0_u32	Protected Register write sequence for 32bit Ecmm0 peripheral registers
WrProtdRegEcmc0_u32	Protected Register write sequence for 32bit Ecmc0 peripheral registers
WrProtdRegEcm0_u32	Protected Register write sequence for 32bit Ecm0 peripheral registers
WrProtdRegFlmd_u32	Protected Register write sequence for 32bit Flmd peripheral registers
NxtrSwRst	API to issue a Nexteer Defined Software Reset
NxtrSwRstFromExcpn	API to issue a Nexteer Defined Software Reset for resetting from a hardware exception source

Configuration REQUIREMeNTS

None

Build Time Config

Modules	Notes

Configuration Files to be provided by Integration Project

N/A

Da Vinci Parameter Configuration Changes

Parameter	Notes	SWC

DaVinci Interrupt Configuration Changes

ISR Name	Notes

Manual Configuration Changes

Constant	Notes	SWC

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Required Global Data Outputs

Specific Include Path present

Yes – Integrator must properly choose the correct include search path in this component in the integration .gpj file. The path chosen must align with the correct micro family (e.g. P1M vs P1MC) as well as the correct specific micro derivative that is being used in the integration project (e.g. R7F701373A). Additionally, the integration .gpj should only include the correct subproject .gpj file (again aligning to the correct micro family as well as correct micro derivative). Please note that two include paths are required in the integration project for use of this component, one to the base family being used (e.g. “-I..\..\AR202A_MicroCtrlrSuprt_Impl\include\P1XC\”) and one to the exact micro derivative (e.g. “-I..\..\AR202A_MicroCtrlrSuprt_Impl\include\P1XC\R7F701373A\”).

Runnable Scheduling

None.

Init	Scheduling Requirements	Trigger

Runnable	Scheduling Requirements	Trigger

Memory Map REQUIREMENTS

Mapping

Memory Section	Contents	Notes

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Feature	RAM	ROM