Sr. No.	Title	Version
1	Software Naming Conventions	Process 04.02.01
2	Software Coding Standards	Process 04.02.01
3	FDD – ES311A GateDrv0Ctrl	See synergy sub project version

Dependencies

SWCs

Module	Required Feature
Spi_Renesas_Ar4.0.3_01.05.00_0

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

None

Configuration REQUIREMeNTS

Build Time Config

Modules	Notes
None

Configuration Files to be provided by Integration Project

None

Da Vinci Parameter Configuration Changes

Parameter	Notes	SWC
None

DaVinci Interrupt Configuration Changes

ISR Name	VIM #	Priority Dependency	Notes
None

Manual Configuration Changes

Constant	Notes	SWC
None

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

See FDD DataDict.m.

Required Global Data Outputs

See FDD DataDict.m.

Specific Include Path present

Runnable Scheduling

This section specifies the required runnable scheduling.

Init	Scheduling Requirements	Trigger
GateDrv0CtrlInit1	None	RTE (Init)

Runnable	Scheduling Requirements	Trigger
GateDrv0CtrlPer1	At the beginning of all 2ms Tasks as close as possible	RTE (2 ms)
GateDrv0CtrlPer2	At the end of all 2ms Tasks as close as possible	RTE (2 ms)

Memory Map REQUIREMENTS

Mapping

Memory Section *	Contents	Notes
None

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Feature	RAM	ROM
None

Non RTE NvM Blocks

Block Name

None

Note : Size of the NVM block if configured in configurator

RTE NvM Blocks

Block Name

None

Note : Size of the NVM block if configured in developer

Compiler Settings

Preprocessor MACRO

None

Optimization Settings

None

2 - GateDrv0Ctrl_MDD

Module Design Document

For

Gate Drive 0 Control

VERSION: 1

DATE: 07-July-2016

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA

Location: The official version of this document is stored in the Nexteer Configuration Management System.

Revision History

Version	Description	Author	Date
1	Initial version	Rijvi Ahmed	07-July-2016

Table of Contents

1 Abbrevations And Acronyms 5

2 References 6

3 GATEDRV0CTRL & High-Level Description 7

4 Design details of software module 8

4.1 Graphical representation of GATEDRV0CTRL 8

5 Variable Data Dictionary 9

5.1 User defined typedef definition/declaration 9

5.2 Variable definition for enumerated types 9

6 Constant Data Dictionary 10

6.1 Program(fixed) Constants 10

6.1.1 Embedded Constants 10

6.1.1.1 Local 10

6.1.1.2 Global 10

6.1.2 Module specific Lookup Tables Constants 10

7 Software Module Implementation 11

7.1 Sub-Module Functions 11

7.2 Initialization Functions 11

7.2.1 Per: GateDrv0CtrlInit1 11

7.3 PERIODIC FUNCTIONS 11

7.3.1 Per: GateDrv0CtrlPer1 11

7.3.1.1 Design Rationale 11

7.3.1.2 Processing of Function 11

7.3.2 Per: GateDrv0CtrlPer2 11

7.3.2.1 Design Rationale 11

7.3.2.2 Processing of Function 11

7.4 Interrupt Functions 11

7.5 Serial Communication Functions 11

7.6 Local Function/Macro Definitions 11

7.6.1 Local Function #1 11

7.6.1.1 Description 11

7.6.2 Local Function #2 12

7.6.2.1 Description 12

7.6.3 Local Function #3 12

7.6.3.1 Description 12

7.6.4 Local Function #4 12

7.6.4.1 Description 12

7.6.5 Local Function #5 12

7.6.5.1 Description 12

7.6.6 Local Function #6 12

7.6.6.1 Description 12

7.6.7 Local Function #7 13

7.6.7.1 Description 13

7.6.8 Local Function #8 13

7.6.8.1 Description 13

7.6.9 Local Function #9 13

7.6.9.1 Description 13

7.7 GLObAL Function/Macro Definitions 13

8 Known Limitations With Design 14

9 UNIT TEST CONSIDERATION 15

Abbrevations And Acronyms

Abbreviation	Description
DFD	Design functional diagram
MDD	Module design Document

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.	Title	Version
1	MDD Guidelines	Process 04.02.01
2	Software Naming Conventions	Process 04.02.01
3	Software Coding Standards	Process 04.02.01
4	FDD – ES311A GateDrv0Ctrl	See synergy sub project version

GATEDRV0CTRL & High-Level Description

This module configures the GateDrive0 connected with SPI channel CSIH2. It also does the diagnostics for GateDrive0 using SPI interface.

Design details of software module

Graphical representation of GATEDRV0CTRL

Variable Data Dictionary

User defined typedef definition/declaration

Typedef Name

Element Name

User Defined Type

Legal Range

(min)

Legal Range

(max)

None

Variable definition for enumerated types

Enum Name	Element Name	Value
None

Constant Data Dictionary

Program(fixed) Constants

Embedded Constants

Local

Constant Name

Resolution

Units

Value

Global

Constant Name

Refer to the FDD

Module specific Lookup Tables Constants

Constant Name	Resolution	Value	Software Segment
Refer to the design

Software Module Implementation

Sub-Module Functions

None

Initialization Functions

Per: GateDrv0CtrlInit1

PERIODIC FUNCTIONS

Per: GateDrv0CtrlPer1

Design Rationale

None

Processing of Function

See design model for details.

Per: GateDrv0CtrlPer2

Design Rationale

None

Processing of Function

See design model for details.

Interrupt Functions

None

Serial Communication Functions

None

Local Function/Macro Definitions

Local Function #1

Function Name	SpiAsyncTx	Type	Min	Max
Arguments Passed	Channel_Cnt_T_u08	Spi_ChannelType	0	Full
	TxData_Cnt_T_u16	Spi_DataType	0	Full
	Sequence_Cnt_T_u08	Spi_SequenceType	0	Full
Return Value	None

Description

(void) Spi_WriteIB( Channel_Cnt_T_u08, &TxData_Cnt_T_u16 );

(void) Call_Spi_AsyncTransmit( Sequence_Cnt_T_u08 );

Local Function #2

Function Name	OffStVrfySt	Type	Min	Max
Arguments Passed	None
Return Value	None

Description

See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/OffState Verification Stateblock in design model.

Local Function #3

Function Name	OffStVrfyData	Type	Min	Max
Arguments Passed	None
Return Value	Flt_Cnt_T_logl	Boolean	FALSE	TRUE

Description

See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/OffState Verification State/OffSt Verification Chk and Transition to Config State/OffStChk Incomplete/Offstate Verification /OffState Verification Check block in design model.

*It is optimized in the implementation to reduce the high static path count.

Local Function #4

Function Name	CfgSt	Type	Min	Max
Arguments Passed	None
Return Value	None

Description

See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Configuration State block in design model.

Local Function #5

Function Name	ReadBackRegs	Type	Min	Max
Arguments Passed	None
Return Value	None

Description

See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Configuration State/Read back Registers block in design model.

Local Function #6

Function Name	OperFltMonrSt	Type	Min	Max
Arguments Passed	None
Return Value	None

Description

See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State block in design model.

Local Function #7

Function Name	GateDrvDetermineOnStSngFETFlt	Type	Min	Max
Arguments Passed	None
Return Value	GenGateDrvFlt_Cnt_T_logl	Boolean	FALSE	TRUE

Description

See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/Status Register indicates Fault/Determine OnState Single FET Fault block in design model.

Local Function #8

Function Name	GateDrvDetermineVltgFlt	Type	Min	Max
Arguments Passed	None
Return Value	GenGateDrvFlt_Cnt_T_logl	Boolean	FALSE	TRUE

Description

See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/Status Register indicates Fault/Determine VREG/Bootstrap Voltage Fault block in design model.

Local Function #9

Function Name	GateDrvDetermineGenericFlt	Type	Min	Max
Arguments Passed	None
Return Value	GenGateDrvFlt_Cnt_T_logl	Boolean	FALSE	TRUE

Description

See GateDrv0Ctrl/GateDrv0CtrlPer2/Gate Drive Enable/Gate Drive State/Operate Fault Monitor State/Determine Faults/Status Register indicates Fault/Determine Generic Gate Drive Fault block in design model.

GLObAL Function/Macro Definitions

None

Known Limitations With Design

“Operate Fault Monitor State” block need to be revisited and optimized.

UNIT TEST CONSIDERATION

None

3 - GateDrv0Ctrl_PeerReviewChecklist

Overview

Summary Sheet
Synergy Project
Source Code
PolySpace

Sheet 1: Summary Sheet

Rev 1.2

8-Jun-15

Peer Review Summary Sheet

Synergy Project Name:

kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. ES311A_GateDrv0Ctrl_Impl

Revision / Baseline:

kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. 1.1.0

Change Owner:

kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Rijvi Ahmed

Work CR ID:

EA4#7437

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

N/A

MDD

Yes

Source Code

Yes

PolySpace

N/A

Integration Manual

N/A

Davinci Files

Comments:

General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include FDD Owner and Integrator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.

Sheet 2: Synergy Project

Peer Review Meeting Log (Component Synergy Project Review)

Quality Check Items:

Rationale is required for all answers of No

New baseline version name from Summary Sheet follows

Yes

Comments:

naming convention

Project contains necessary subprojects

Yes

Comments:

Project contains the correct version of subprojects

Yes

Comments:

Design subproject is correct version

Yes

Comments:

General Notes / Comments:

LN: Intended Use: Identify who were the reviewers and if the reviewed changes have been approved. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. KMC: Group Review Level removed in Rev 4.0 since the design review is not checked in until approved, so it would always be DR4. Review Board:

Change Owner:

Rijvi Ahmed

Review Date :

09/23/16

Lead Peer Reviewer:

Selva Sengottaiyan

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 3: Source Code

Rev 1.2

8-Jun-15

Peer Review Meeting Log (Source Code Review)

Source File Name:

GateDrv0Ctrl.c

Source File Revision:

Header File Name:

N/A

Header File Revision:

kzshz2: Intended Use: Identify which version of the source file is being review. Rationale: Required for traceability between source code and review. Auditors will likely require this. N/A

MDD Name:

GateDrv0Ctrl_MDD.doc

Revision:

FDD/SCIR/DSR/FDR/CM Name:

GateDrv0Ctrl_Design

Revision:

1.5.0

Quality Check Items:

Rationale is required for all answers of No

Working EA4 Software Naming Convention followed:

for variable names

Yes

Comments:

for constant names

Yes

Comments:

for function names

Yes

Comments:

for other names (component, memory

Yes

Comments:

mapping handles, typedefs, etc.)

All paths assign a value to outputs, ensuring

Yes

Comments:

all outputs are initialized prior to being written

Requirements Tracability tags in code match the requirements tracability in the FDD

N/A

Comments:

requirements tracability in the FDD

Per the current decision of the SW team all the requirement tags are removed

All variables are declared at the function level.

Yes

Comments:

Synergy version matches change history

kzshz2: Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). Rationale: There have been many occassions where versions were not updated in files and as a result Unit Test were referencing wrong versions. This often time leads to the need to re-run of batch tests.

Yes

Comments:

and Version Control version in file comment block

Change log contains detailed description of changes

Yes

Comments:

and Work CR number

Code accurately implements FDD (Document or Model)

Yes

Comments:

Verified no Compiler Errors or Warnings

KMC: Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). Rationale: This is needed to ensure there will be no errors discovered at the time of integration. A Sandox project should be used; QAC can find compiler errors but not warnings.

Yes

Comments:

Component.h is included

N/A

Comments:

All other includes are actually needed. (System includes

Yes

Comments:

only allowed in Nexteer library components)

Software Design and Coding Standards followed:

Version: 2.1

Code comments are clear, correct, and adequate

Yes

Comments:

and have been updated for the change: [N40] and

all other rules in the same section as rule [N40],

plus [N75], [N12], [N23], [N33], [N37], [N38],

[N48], [N54], [N77], [N79], [N72]

Source file (.c and .h) comment blocks are per

Yes

Comments:

standards and contain correct information: [N41], [N42]

Function comment blocks are per standards and

Yes

Comments:

contain correct information: [N43]

Code formatting (indentation, placement of

Yes

Comments:

braces, etc.) is per standards: [N5], [N55], [N56],

[N57], [N58], [N59]

Embedded constants used per standards; no

Yes

Comments:

"magic numbers": [N12]

Some magic numbers are used to match the design.

Memory mapping for non-RTE code

Yes

Comments:

is per standard

All execution-order-dependent code can be

Yes

Comments:

recognized by the compiler: [N80]

All loops have termination conditions that ensure

Yes

Comments:

finite loop iterations: [N63]

All divides protect against divide by zero

N/A

Comments:

if needed: [N65]

All integer division and modulus operations

N/A

Comments:

handle negative numbers correctly: [N76]

All typecasting and fixed point arithmetic,

N/A

Comments:

including all use of fixed point macros and

timer functions, is correct and has no possibility

of unintended overflow or underflow: [N66]

All float-to-unsiged conversions ensure the.

N/A

Comments:

float value is non-negative: [N67]

All conversions between signed and unsigned

N/A

Comments:

types handle msb==1 as intended: [N78]

All pointer dereferencing protects against

Yes

Comments:

null pointer if needed: [N70]

Component outputs are limited to the legal range

Yes

Comments:

Not needed

defined in the FDD DataDict.m file : [N53]

All code is mapped with FDD (all FDD

Yes

Comments:

subfunctions and/or model blocks identified

with code comments; all code corresponds to

some FDD subfunction and/or model block): [N40]

Review did not identify violations of other

Yes

Comments:

coding standard rules

Anomaly or Design Work CR created

Yes

Comments: List Anomaly or CR numbers

for any FDD corrections needed

“Operate Fault Monitor State” block need to be optimized.

General Notes / Comments:

Reviewed only for the changes

Change Owner:

Rijvi Ahmed

Review Date :

09/23/16

Lead Peer Reviewer:

Selva Sengottaiyan

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 4: PolySpace

Rev 1.2

8-Jun-15

Peer Review Meeting Log (QAC/PolySpace Review)

Source File Name:

GateDrv0Ctrl.c

Source File Revision:

Source File Name:

Source File Revision:

Source File Name:

Source File Revision:

EA4 Static Analysis Compliance Guideline version:

01.01.00

Poly Space version:

Windows User: eg. 2013b 2013b

Polyspace sub project version:

Windows User: eg. TL108a_PolyspaceSuprt_1.0.0 N/A

QAC version:

Windows User: eg 8.1.1-R 8.1.1-R

QAC sub project version:

Windows User: eg. TL_100A_1.1.0 1.2.0

Quality Check Items:

Rationale is required for all answers of No

Contract Folder's header files are appropriate and

kzshz2: Intended Use: Identify that the contract folder contains only the information required for this component. All other variables, constants, function prototypes, etc. should be removed. Rationale: This will help avoid unit testers having to considers object not used. It will also avoid having other files required for QAC.

Yes

Comments:

function prototypes match the latest component version

100% Compliance to the EA4 Static Analysis

Yes

Comments:

Compliance Guideline

Are previously added justification and deviation

Yes

Comments:

comments still appropriate

Do all MISRA deviation comments use approved

Yes

Comments:

deviation tags

Cyclomatic complexity and Static path count OK

Creager, Kathleen: use Browse Function Metrics, STCYC and STPTH

Yes

Comments:

for all functions in the component per Design

and Coding Standards rule [N47]

General Notes / Comments:

Change Owner:

Rijvi Ahmed

Review Date :

09/23/16

Lead Peer Reviewer:

Selva Sengottaiyan

Approved by Reviewer(s):

Yes

Other Reviewer(s):