Component Implementation

• 1: PolarityCfg_Integration Manual
• 2: PolarityCfg_MDD
• 3: PolarityCfg_Peer Review Checklists
• 4: requirements

1 - PolarityCfg_Integration Manual

Integration Manual

For

‘PolarityCfg’

VERSION: 1.0

DATE: 26-May-2015

Prepared By:

Sankardu Varadapureddi,

Nexteer Automotive,

Saginaw, MI, USA

Revision History

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 Non RTE NvM Blocks 10

7.4 RTE NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

References

This section lists the title & version of all the documents that are referred for development of this document

Dependencies

SWCs

Global Functions(Non RTE) to be provided to Integration Project

None

Configuration REQUIREMeNTS

Build Time Config

Configuration Files to be provided by Integration Project

None

Da Vinci Parameter Configuration Changes

DaVinci Interrupt Configuration Changes

Manual Configuration Changes

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer DataDict.m file in the FDD

Required Global Data Outputs

Refer DataDict.m file file in the FDD

Specific Include Path present

No

Runnable Scheduling

This section specifies the required runnable scheduling.

Memory Map REQUIREMENTS

Mapping

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Table 1: ARM Cortex R4 Memory Usage

Non RTE NvM Blocks

RTE NvM Blocks

Compiler Settings

Preprocessor MACRO

None.

Optimization Settings

None

Appendix

None

2 - PolarityCfg_MDD

Module Design Document

For

‘PolarityCfg’

VERSION: 1.0

DATE: 26-May-2015

Prepared By:

Sankardu Varadapureddi,

Nexteer Automotive,

Saginaw, MI, USA

Location: The official version of this document is stored in the Nexteer Configuration Management System.

Revision History

Table of Contents

1 Abbrevations And Acronyms 5

2 References 6

3 Power Disconnect High-Level Description 7

4 Design details of software module 8

4.1 Graphical representation of POWER DISCONNECT 8

4.2 Data Flow Diagram 8

4.2.1 Module level DFD 8

4.2.2 Sub-Module level DFD 8

4.3 COMPONENT FLOW DIAGRAM 8

5 Variable Data Dictionary 9

5.1 User defined typedef definition/declaration 9

5.2 Variable definition for enumerated types 9

6 Constant Data Dictionary 10

6.1 Program(fixed) Constants 10

6.1.1 Embedded Constants 10

6.1.1.1 Local 10

6.1.1.2 Global 10

6.1.2 Module specific Lookup Tables Constants 10

7 Software Module Implementation 12

7.1 Sub-Module Functions 12

7.1.1 Initialization Functions 12

7.1.1.1 INIT: PolarityCfgInit 12

7.1.1.1.1 Design Rationale 12

7.1.1.1.2 Module Outputs 12

7.1.1.1.3 Module Internal 12

7.1.2 PERIODIC FUNCTIONS 12

7.1.3 Interrupt Functions 12

7.1.4 Server runnables 13

7.1.4.1 PolarityCfgRead 13

7.1.4.1.1 Design Rationale 13

7.1.4.1.2 Store Module Inputs to Local copies 13

7.1.4.1.3 (Processing of function)……… 13

7.1.4.1.4 Store Local copy of outputs into Module Outputs 13

7.1.4.2 PolarityCfgWr 13

7.1.4.2.1 Design Rationale 13

7.1.4.2.2 Store Module Inputs to Local copies 13

7.1.4.2.3 (Processing of function)……… 13

7.1.4.2.4 Store Local copy of outputs into Module Outputs 13

7.1.5 Local Function/Macro Definitions 13

7.1.5.1 Local Function #1 13

7.1.5.2 Description 13

7.1.6 GLObAL Function/Macro Definitions 13

7.1.7 Tranisition FUNCTIONS 14

8 Known Limitations With Design 15

9 UNIT TEST CONSIDERATION 16

10 Appendix 17

Abbrevations And Acronyms

References

This section lists the title & version of all the documents that are referred for development of this document

Power Disconnect High-Level Description

This function will identify polarity control settings for certain points in the design.

Design details of software module

Graphical representation of POWER DISCONNECT

Data Flow Diagram

Refer FDD

Module level DFD

Refer FDD

Sub-Module level DFD

Refer FDD

COMPONENT FLOW DIAGRAM

Refer FDD

Variable Data Dictionary

User defined typedef definition/declaration

<This section documents any user types uniquely used for the module.>

Variable definition for enumerated types

Constant Data Dictionary

Program(fixed) Constants

Embedded Constants

Local

Global

Module specific Lookup Tables Constants

Software Module Implementation

Sub-Module Functions

Initialization Functions

PolarityCfgInit

INIT: PolarityCfgInit

Design Rationale

Design follows implemenetation in FDD.

Module Outputs

Refer ‘PolarityCfgInit’ block in FDD

Module Internal

None

PERIODIC FUNCTIONS

None

Interrupt Functions

None

Server runnables

PolarityCfgRead

Design Rationale

None

Store Module Inputs to Local copies

None

(Processing of function)………

Refer ‘PolarityCfgRead’ block in FDD

Store Local copy of outputs into Module Outputs

None

PolarityCfgWr

Design Rationale

None

Store Module Inputs to Local copies

None

(Processing of function)………

Refer ‘PolarityCfgWr’ block in FDD

Store Local copy of outputs into Module Outputs

None

Local Function/Macro Definitions

Local Function #1

Description

• Design:

if ( (Polarity_Cnt_T_u32 & PolarityMask_Cnt_T_u32) == PolarityMask_Cnt_T_u32 )

set ‘Polarity_Cnt_T_s08’ to ‘1’

else

set ‘Polarity_Cnt_T_s08’ to ‘-1’

• Note: ‘PolarityMask_Cnt_T_u32’ is a bit field mask and takes values mentioned in table at sec 6.1.1.1

GLObAL Function/Macro Definitions

None

Tranisition FUNCTIONS

None

Known Limitations With Design

None

UNIT TEST CONSIDERATION

None

Appendix

None

3 - PolarityCfg_Peer Review Checklists

Rev 1.2

8-Jun-15

Peer Review Summary Sheet

Synergy Project Name:

kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. ES102A_PolarityCfg_Impl

Revision / Baseline:

kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. ES102A_PolarityCfg_Impl_1.0.1

Change Owner:

kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Nick Saxton

Work CR ID:

EA4#5590

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

MDD

Source Code

PolySpace

Integration Manual

Davinci Files

Comments:

Design only change - pulled in new FDD

General Guidelines: - The reviews shall be performed over the portions of the component that were modified as a result of the Change Request. - New components should include FDD Owner and Integrator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files) - Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed. - To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file. - .h file should be reviewed with the source file as part of the source file.

4 - requirements