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Component Implementation

1: requirements
2: StHlthSigNormn Review
3: StHlthSigNormn_IntegrationManual
4: StHlthSigNormn_MDD

Component Implementation

Component Documentation

1 - requirements

FDD	ID	Source	Function	Line(s)	Status	Comment
		.SwFileName	.SwFuncName	.SwLines	.SwStatus	.SwComment
ES105A	26	StHlthSigNormn.c	EcuTFildMon	890,892	I
ES105A	27	StHlthSigNormn.c	OutpAssiMon	991,993	I
ES105A	48	StHlthSigNormn.c	EcuTFildMon	905-995	I
ES105A	49	StHlthSigNormn.c	OutpAssiMon	906-996	I
ES105A	46	StHlthSigNormn.c	EcuTFildMon	811-815,822-827,834-839,845-850,856-861,865-884	I
ES105A	44	StHlthSigNormn.c	EcuTFildMon	842,844-849	I
ES105A	45	StHlthSigNormn.c	EcuTFildMon	855-860	I
ES105A	42	StHlthSigNormn.c	EcuTFildMon	819,821-826	I
ES105A	43	StHlthSigNormn.c	EcuTFildMon	831,833-838	I
ES105A	40	StHlthSigNormn.c	EcuTFildMon	796-896	I
ES105A	41	StHlthSigNormn.c	EcuTFildMon	808,810-814	I
ES105A	7	StHlthSigNormn.c	UpdRawSig_Oper	756-772	I
ES105A	6	StHlthSigNormn.c	UpdRawSig_Oper	755-771	I
ES105A	9	StHlthSigNormn.c	StHlthSigNormnInit1	694-700	I
ES105A	8	StHlthSigNormn.c	UpdRawSig_Oper	757-773	I
ES105A	39	StHlthSigNormn.c	UpdRawSig_Oper	795-895	I
ES105A	15	StHlthSigNormn.c	OutpAssiMon	919,920,921	I
ES105A	14	StHlthSigNormn.c	EcuTFildMon	804	I
ES105A	54	StHlthSigNormn.c	OutpAssiMon	966-985	I
ES105A	51	StHlthSigNormn.c	OutpAssiMon	934-941	I
ES105A	50	StHlthSigNormn.c	OutpAssiMon	923	I
ES105A	53	StHlthSigNormn.c	OutpAssiMon	953-960	I
ES105A	52	StHlthSigNormn.c	OutpAssiMon	943-951	I

2 - StHlthSigNormn Review

Overview

Summary Sheet
Synergy Project
Source Code
PolySpace

Sheet 1: Summary Sheet

Rev 1.2

8-Jun-15

Peer Review Summary Sheet

Synergy Project Name:

kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. ES105A_StHlthSigNormn_Impl

Revision / Baseline:

kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. ES105A_StHlthSigNormn_Impl_3.1.0

Change Owner:

kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Akilan Rathakrishnan

Work CR ID:

EA#7978

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

MDD

Yes

Source Code

Yes

PolySpace

Integration Manual

Davinci Files

Comments:

General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include FDD Owner and Integrator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.

Sheet 2: Synergy Project

Peer Review Meeting Log (Component Synergy Project Review)

Quality Check Items:

Rationale is required for all answers of No

New baseline version name from Summary Sheet follows

Yes

Comments:

naming convention

Project contains necessary subprojects

Yes

Comments:

Project contains the correct version of subprojects

Yes

Comments:

Design subproject is correct version

Yes

Comments:

General Notes / Comments:

LN: Intended Use: Identify who were the reviewers and if the reviewed changes have been approved. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. KMC: Group Review Level removed in Rev 4.0 since the design review is not checked in until approved, so it would always be DR4. Review Board:

Change Owner:

Akilan Rathakrishnan

Review Date :

10/13/16

Lead Peer Reviewer:

Krishna Anne

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 3: Source Code

Rev 1.2

8-Jun-15

Peer Review Meeting Log (Source Code Review)

Source File Name:

StHlthSigNormn.c

Source File Revision:

Header File Name:

Header File Revision:

kzshz2: Intended Use: Identify which version of the source file is being review. Rationale: Required for traceability between source code and review. Auditors will likely require this.

MDD Name:

StHlthSigNormn_MDD.doc

Revision:

FDD/SCIR/DSR/FDR/CM Name:

ES105A_StHlthSigNormn_Design

Revision:

3.2.0

Quality Check Items:

Rationale is required for all answers of No

Working EA4 Software Naming Convention followed:

for variable names

Yes

Comments:

for constant names

Yes

Comments:

for function names

Yes

Comments:

for other names (component, memory

N/A

Comments:

mapping handles, typedefs, etc.)

All paths assign a value to outputs, ensuring

Yes

Comments:

all outputs are initialized prior to being written

Requirements Tracability tags in code match the requirements tracability in the FDD

N/A

Comments:

requirements tracability in the FDD

All variables are declared at the function level.

Yes

Comments:

Synergy version matches change history

kzshz2: Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). Rationale: There have been many occassions where versions were not updated in files and as a result Unit Test were referencing wrong versions. This often time leads to the need to re-run of batch tests.

Yes

Comments:

and Version Control version in file comment block

Change log contains detailed description of changes

Yes

Comments:

and Work CR number

Code accurately implements FDD (Document or Model)

Yes

Comments:

Verified no Compiler Errors or Warnings

KMC: Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). Rationale: This is needed to ensure there will be no errors discovered at the time of integration. A Sandox project should be used; QAC can find compiler errors but not warnings.

Yes

Comments:

Component.h is included

N/A

Comments:

All other includes are actually needed. (System includes

N/A

Comments:

only allowed in Nexteer library components)

Software Design and Coding Standards followed:

Version:

Code comments are clear, correct, and adequate

Yes

Comments:

and have been updated for the change: [N40] and

all other rules in the same section as rule [N40],

plus [N75], [N12], [N23], [N33], [N37], [N38],

[N48], [N54], [N77], [N79], [N72]

Source file (.c and .h) comment blocks are per

Yes

Comments:

standards and contain correct information: [N41], [N42]

Function comment blocks are per standards and

Yes

Comments:

contain correct information: [N43]

Code formatting (indentation, placement of

Yes

Comments:

braces, etc.) is per standards: [N5], [N55], [N56],

[N57], [N58], [N59]

Embedded constants used per standards; no

Yes

Comments:

"magic numbers": [N12]

Memory mapping for non-RTE code

N/A

Comments:

is per standard

All execution-order-dependent code can be

N/A

Comments:

recognized by the compiler: [N80]

All loops have termination conditions that ensure

N/A

Comments:

finite loop iterations: [N63]

All divides protect against divide by zero

Yes

Comments:

if needed: [N65]

All integer division and modulus operations

Yes

Comments:

handle negative numbers correctly: [N76]

All typecasting and fixed point arithmetic,

Yes

Comments:

including all use of fixed point macros and

timer functions, is correct and has no possibility

of unintended overflow or underflow: [N66]

All float-to-unsiged conversions ensure the.

Yes

Comments:

float value is non-negative: [N67]

All conversions between signed and unsigned

N/A

Comments:

types handle msb==1 as intended: [N78]

All pointer dereferencing protects against

N/A

Comments:

null pointer if needed: [N70]

Component outputs are limited to the legal range

Yes

Comments:

defined in the FDD DataDict.m file : [N53]

All code is mapped with FDD (all FDD

Yes

Comments:

subfunctions and/or model blocks identified

with code comments; all code corresponds to

some FDD subfunction and/or model block): [N40]

Review did not identify violations of other

Yes

Comments:

coding standard rules

Anomaly or Design Work CR created

Yes

Comments:

for any FDD corrections needed

General Notes / Comments:

Change Owner:

Akilan Rathakrishnan

Review Date :

10/13/16

Lead Peer Reviewer:

Krishna Anne

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 4: PolySpace

Rev 1.2

8-Jun-15

Peer Review Meeting Log (QAC/PolySpace Review)

Source File Name:

StHlthSigNormn.c

Source File Revision:

Source File Name:

Source File Revision:

Source File Name:

Source File Revision:

EA4 Static Analysis Compliance Guideline version:

01.01.00

Poly Space version:

Windows User: eg. 2013b R2013b

Polyspace sub project version:

Windows User: eg. TL108a_PolyspaceSuprt_1.0.0 Not released

QAC version:

Windows User: eg 8.1.1-R 8.1.1-R

QAC sub project version:

Windows User: eg. TL_100A_1.1.0 TL100A_QACSuprt_1.2.0

Quality Check Items:

Rationale is required for all answers of No

Contract Folder's header files are appropriate and

kzshz2: Intended Use: Identify that the contract folder contains only the information required for this component. All other variables, constants, function prototypes, etc. should be removed. Rationale: This will help avoid unit testers having to considers object not used. It will also avoid having other files required for QAC.

Yes

Comments:

function prototypes match the latest component version

100% Compliance to the EA4 Static Analysis

Yes

Comments:

Compliance Guideline

Are previously added justification and deviation

Yes

Comments:

comments still appropriate

Do all MISRA deviation comments use approved

Yes

Comments:

deviation tags

Cyclomatic complexity and Static path count OK

Creager, Kathleen: use Browse Function Metrics, STCYC and STPTH

Yes

Comments:

for all functions in the component per Design

and Coding Standards rule [N47]

General Notes / Comments:

Change Owner:

Akilan Rathakrishnan

Review Date :

10/13/16

Lead Peer Reviewer:

Krishna Anne

Approved by Reviewer(s):

Yes

Other Reviewer(s):

3 - StHlthSigNormn_IntegrationManual

Integration Manual

For

SThlthSigNormn

VERSION: 1.0

DATE: 09-Feb-2016

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA

Revision History

Sl. No.	Description	Author	Version	Date
1	Initial version	Akilan Rathakrishnan	1.0	09-Feb-2016

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 Non RTE NvM Blocks 10

7.4 RTE NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

Abbreviation	Description
DFD	Design functional diagram
MDD	Module design Document
	<ADD more to the table if applicable>

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.	Title	Version
<1>	<FDD - <FDD ES105A_StHlthSigNormn_Design>	Refer Synergy subproject version

Dependencies

SWCs

Module	Required Feature
None	N/A

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

< Global function (except the ones that are defined in RTE modules) that is defined in this component but used by other function

Configuration REQUIREMeNTS

Build Time Config

Modules	Notes
None

Configuration Files to be provided by Integration Project

None

Da Vinci Parameter Configuration Changes

Parameter	Notes	SWC
N/A

DaVinci Interrupt Configuration Changes

ISR Name	VIM #	Priority Dependency	Notes
N/A

Manual Configuration Changes

Constant	Notes	SWC
N/A

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer ES105A_StHlthSigNormn_DataDict.m file

Required Global Data Outputs

Refer ES105A_StHlthSigNormn_DataDict.m file

Specific Include Path present

Runnable Scheduling

This section specifies the required runnable scheduling.

Init	Scheduling Requirements	Trigger
StHlthSigNormnInit1	None	RTE Init

Runnable	Scheduling Requirements	Trigger
UpdRawSig_Oper	Shall be triggered at the end of every tasks from which signals are monitored.	Server invocation for OperationPrototype <Oper> of PortPrototype <UpdRawSig>

Memory Map REQUIREMENTS

Mapping

Memory Section	Contents	Notes
None

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Feature	RAM	ROM
None

Table 1: ARM Cortex R4 Memory Usage

Non RTE NvM Blocks

Block Name

None

Note : Size of the NVM block if configured in developer

RTE NvM Blocks

Block Name

None

Note : Size of the NVM block if configured in developer

Compiler Settings

Preprocessor MACRO

None

Optimization Settings

None

Appendix

<This section is for appendix>

4 - StHlthSigNormn_MDD

Module Design Document

For

State of Health Signal Normalization

Sep 27, 2016

Prepared For:

Software Engineering

Nexteer Automotive,

Saginaw, MI, USA

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USAChange History

Sl. No.	Description	Author	Version	Date
1	Initial Version	Akilan Rathakrishnan	1.0	09-Feb-2016
2	Updated for EA4# 5445	Akilan Rathakrishnan	2.0	02-May-2016
3	Updated for EA4#7305	Akilan Rathakrishnan	3.0	27-Sep-2016

Table of Contents

1 StHlthSignNormn High-Level Description 5

2 Design details of software module 6

2.1.1.1 Graphical representation of StHlthSigNormn 6

2.1.1.2 Data Flow Diagram 7

2.1.2 Component level DFD 8

2.1.3 Function level DFD 8

3 Constant Data Dictionary 9

3.1.1.1 Program (fixed) Constants 9

3.1.2 Embedded Constants 9

4 Software Component Implementation 10

4.1.1 Sub-Module Functions 10

4.1.1.1 Init: StHlthSigNormnInit1 10

4.1.1.2 Per: None 10

4.1.2 Interrupt Service Routines 10

4.1.3 Server Runnable Functions 10

4.1.3.1 UpdRawSig 10

4.1.3.1.1 Design Rationale 10

4.1.3.1.2 Store Module Inputs to Local copies 10

4.1.3.1.3 (Processing of function)……… 10

4.1.3.1.4 Store Local copy of outputs into Module Outputs 10

4.1.4 Module Internal (Local) Functions 11

4.1.4.1 Local Function #1 11

4.1.4.1.1 Description 11

4.1.4.2 Local Function #2 Rationale 11

4.1.4.2.1 Description 11

4.1.4.3 Local Function #3 Rationale 11

4.1.4.3.1 Description 11

4.1.4.4 Local Function #4 Rationale 12

4.1.4.4.1 Description 12

4.1.4.5 Local Function #5 Rationale 12

4.1.4.5.1 Description 12

4.1.4.6 Local Function #6 Rationale 12

4.1.4.6.1 Description 12

4.1.4.7 Local Function #7 Rationale 12

4.1.4.7.1 Description 13

4.1.4.8 Local Function #8 Rationale 13

4.1.4.8.1 Description 13

4.1.4.9 Local Function #9 Rationale 13

4.1.4.9.1 Description 13

4.1.4.10 Local Function #10 Rationale 13

4.1.4.10.1 Description 13

4.1.4.11 Local Function #11 Rationale 14

4.1.4.11.1 Description 14

4.1.4.12 Local Function #12 Rationale 14

4.1.4.12.1 Description 14

4.1.4.13 Local Function #13 Rationale 14

4.1.4.13.1 Description 14

4.1.5 Transition Functions 14

5 Known Limitations with Design 15

6 UNIT TEST CONSIDERATION 16

Appendix A Abbreviations and Acronyms 17

Appendix B Glossary 18

Appendix C References 19

StHlthSignNormn High-Level Description

This component acts as an interface component between ES106A (State of Health Signal Statistics) and rest of the components from which signals need to be monitored. It reads data or status values from different components, applies normalization algorithm to convert it as State of Health information which will be in the scale of 0 to 100. It also provides auxiliary output for some signals to indicate the additional information about monitored signals.

Design details of software module

See FDD.

Graphical representation of StHlthSigNormn

Data Flow Diagram

See FDD.

Component level DFD

See FDD.

Function level DFD

See FDD.

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Constant Name	Resolution	Units	Value
TMAXRNGVAL_CNT_U08	1	Cnt	15
VLTGMAXRNGVAL_CNT_U08	1	Cnt	15



PHAVLTGDIVBYZEROPROTNVAL_NANOSEC_U32	1	NanoSec	180000

* Also see FDD ES105A_StHlthSigNormn_DataDict.m file

Software Component Implementation

Sub-Module Functions

Init: StHlthSigNormnInit1

Design Rationale

None

Module Outputs

See FDD

Module Internal

See FDD

Per: None

Interrupt Service Routines

None

Server Runnable Functions

UpdRawSig

Design Rationale

None

Store Module Inputs to Local copies

See FDD

(Processing of function)………

See FDD

Store Local copy of outputs into Module Outputs

See FDD

Module Internal (Local) Functions

Local Function #1

Function Name	EcuTFildMon	Type	Min	Max
Arguments Passed	None	N/A	N/A	N/A
Return Value	CtrlrTStHlth	Uint8	0	100
Return Value	CtrlrTRng	Uint8	0	15

Description

This function implements “Controller Temperature” block in the FDD

Local Function #2 Rationale

Function Name	OutpAssiMon	Type	Min	Max
Arguments Passed	None	N/A	N/A	N/A
Return Value	OutpAssiStHlth	Uint8	0	100
Return Value	VltgRng	Uint8	0	15

Description

This function implements “Health of Assist Due To Voltage” block in the FDD

Local Function #3 Rationale

Function Name	DigTqSnsrStHlthCalc	Type	Min	Max
Arguments Passed	SigId_Arg	StHlthMonSig2	0	20
Return Value	DigTqSnsrAStHlth	Uint8	0	100
Return Value	DigTqSnsrBStHlth	Uint8	0	100
Return Value	DigTqIdptSigStHlth	Uint8	0	100

Description

This function implements “Digital Torque Sensor” block in the FDD

Local Function #4 Rationale

Function Name	DutyCycExcddStHlthCalc	Type	Min	Max
Arguments Passed	None	N/A	N/A	N/A
Return Value	DutyCycStHlth	Uint8	0	100

Description

This function implements “Duty Cycle” block in the FDD

Local Function #5 Rationale

Function Name	EotImpctCntrStHlthCalc	Type	Min	Max
Arguments Passed	None	N/A	N/A	N/A
Return Value	EotImpctStHlth	Uint8	0	100

Description

This function implements “EOT Impact” block in the FDD

Local Function #6 Rationale

Function Name	MotPosnStHlthCalc	Type	Min	Max
Arguments Passed	None	N/A	N/A	N/A
Return Value	MotPosStHlth	Uint8	0	100

Description

This function implements “Motor Position” block in the FDD

Local Function #7 Rationale

Function Name	MotPosnErrStHlthCalc	Type	Min	Max
Arguments Passed	SigId_Arg	StHlthMonSig2	0	20
Return Value	AbsltMotPosABDifStHlth	Uint8	0	100
Return Value	AbsltMotPosACDifStHlth	Uint8	0	100
Return Value	AbsltMotPosBCDifStHlth	Uint8	0	100

Description

This function implements “Motor Position Phase Difference” block in the FDD

Local Function #8 Rationale

Function Name	CurrMotSumStHlthCalc	Type	Min	Max
Arguments Passed	SigId_Arg	StHlthMonSig2	0	20
Return Value	CurrMotSumABCStHlth	Uint8	0	100
Return Value	CurrMotSumDEFStHlth	Uint8	0	100

Description

This function implements “Current Motor Sum” block in the FDD

Local Function #9 Rationale

Function Name	PhaVltgStHlthCalc	Type	Min	Max
Arguments Passed	SigId_Arg	StHlthMonSig2	0	20
Return Value	PhaAStHlth	Uint8	0	100
Return Value	PhaBStHlth	Uint8	0	100
Return Value	PhaCStHlth	Uint8	0	100
Return Value	PhaDStHlth	Uint8	0	100
Return Value	PhaEStHlth	Uint8	0	100
Return Value	PhaFStHlth	Uint8	0	100

Description

This function implements “Health of Phase” block in the FDD

Local Function #10 Rationale

Function Name	RamEccSngBitCorrnStHlthCalc	Type	Min	Max
Arguments Passed	None	N/A	N/A	N/A
Return Value	RamEccSngBitCorrnStHlth	Uint8	0	100

Description

This function implements “Single Bit Correction” block in the FDD

Local Function #11 Rationale

Function Name	PhaVltgCalcStHlth	Type	Min	Max
Arguments Passed	MotDrvErrX_NanoSec_T_f32	float32	0,0	40000000,0
Return Value	PhaXStHlth_Cnt_T_u08	Uint8	0	100

Description

This function implements a sub-section in“Health of Phase”” block in the FDD

Local Function #12 Rationale

Function Name	FricEstimnStHlthCalc	Type	Min	Max
Arguments Passed	None	NA
Return Value	None	NA

Description

This function implements a sub-section in“Friction Estimation”” block in the FDD

Local Function #13 Rationale

Function Name	WhlImbRejctnStHlthCalc	Type	Min	Max
Arguments Passed	None	NA
Return Value	None	NA

Description

This function implements a sub-section in“Wheel Imbalance Rejection”” block in the FDD

Transition Functions

None.

Known Limitations with Design

None

UNIT TEST CONSIDERATION

None

Abbreviations and Acronyms

Abbreviation or Acronym	Description
DFD	Design functional diagram
MDD	Module design Document
FDD	Functional Design Document

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

ISO 9000
ISO/IEC 12207
ISO/IEC 15504
Automotive SPICE® Process Reference Model (PRM)
Automotive SPICE® Process Assessment Model (PAM)
ISO/IEC 15288
ISO 26262
IEEE Standards
SWEBOK
PMBOK
Existing Nexteer Automotive documentation

Term	Definition	Source
MDD	Module Design Document
DFD	Data Flow Diagram

References

Ref. #	Title	Version
1	AUTOSAR Specification of Memory Mapping (Link:AUTOSAR_SWS_MemoryMapping.pdf)	v1.3.0 R4.0 Rev 2
2	MDD Guideline	Process Release 04.02.01
3	Software Naming Conventions.doc	Process Release 04.02.01
4	Software Design and Coding Standards.doc	Process Release 04.02.01
5	FDD: ES105A_StHlthSigNormn_Design	See Synergy subproject version