This is the multi-page printable view of this section. Click here to print.

Return to the regular view of this page.

Component Design

1: CM320A_Adc1CfgAndUse_RegisterConfiguration
2: CM320A_Adc1CfgAndUse_Design_PeerReviewChkList

Component Design

Module Detailled Design

CM320A_Adc1CfgAndUse_RegisterConfiguration.html

Component Documentation

CM320A_Adc1CfgAndUse_Design_PeerReviewChkList.html

1 - CM320A_Adc1CfgAndUse_RegisterConfiguration

Overview

ConfigInit
Change Log

Sheet 1: ConfigInit

Order	Feature/Function	Register	Field	Header File Definition	Value (Decimal)	Notes	Write Constraints

1	Virtual Channel	VCR00	UINT32	ADCD1VCR00	ADC1CFGANDUSE_ADCD1VCR00_CNT_U32		Must be written at register level
2	Virtual Channel	VCR00	GCTRL	ADCD1GCTRL	Unused	Unused field of parent register	Must be written at register level
3	Virtual Channel	VCR00	ADIE	ADCD1ADIE	Unused	Unused field of parent register	Must be written at register level
4	Virtual Channel	VCR00	CNVCLS	ADCD1CNVCLS	Unused	Unused field of parent register	Must be written at register level
5	Virtual Channel	VCR00	PDE	ADCD1PDE	Unused	Unused field of parent register	Must be written at register level
6	Virtual Channel	VCR00	PUE	ADCD1PUE	Unused	Unused field of parent register	Must be written at register level
7	Virtual Channel	VCR01	UINT32	ADCD1VCR01	ADC1CFGANDUSE_ADCD1VCR01_CNT_U32		Must be written at register level
8	Virtual Channel	VCR02	UINT32	ADCD1VCR02	ADC1CFGANDUSE_ADCD1VCR02_CNT_U32		Must be written at register level
9	Virtual Channel	VCR03	UINT32	ADCD1VCR03	ADC1CFGANDUSE_ADCD1VCR03_CNT_U32		Must be written at register level
10	Virtual Channel	VCR04	UINT32	ADCD1VCR04	ADC1CFGANDUSE_ADCD1VCR04_CNT_U32		Must be written at register level
11	Virtual Channel	VCR05	UINT32	ADCD1VCR05	ADC1CFGANDUSE_ADCD1VCR05_CNT_U32		Must be written at register level
12	Virtual Channel	VCR06	UINT32	ADCD1VCR06	ADC1CFGANDUSE_ADCD1VCR06_CNT_U32		Must be written at register level
13	Virtual Channel	VCR07	UINT32	ADCD1VCR07	ADC1CFGANDUSE_ADCD1VCR07_CNT_U32		Must be written at register level
14	Virtual Channel	VCR08	UINT32	ADCD1VCR08	ADC1CFGANDUSE_ADCD1VCR08_CNT_U32		Must be written at register level
15	Virtual Channel	VCR09	UINT32	ADCD1VCR09	ADC1CFGANDUSE_ADCD1VCR09_CNT_U32		Must be written at register level
16	Virtual Channel	VCR10	UINT32	ADCD1VCR10	ADC1CFGANDUSE_ADCD1VCR10_CNT_U32		Must be written at register level
17	Virtual Channel	VCR11	UINT32	ADCD1VCR11	ADC1CFGANDUSE_ADCD1VCR11_CNT_U32		Must be written at register level
18	Virtual Channel	VCR12	UINT32	ADCD1VCR12	ADC1CFGANDUSE_ADCD1VCR12_CNT_U32		Must be written at register level
19	Virtual Channel	VCR13	UINT32	ADCD1VCR13	ADC1CFGANDUSE_ADCD1VCR13_CNT_U32		Must be written at register level
20	Virtual Channel	VCR14	UINT32	ADCD1VCR14	ADC1CFGANDUSE_ADCD1VCR14_CNT_U32		Must be written at register level
21	Virtual Channel	VCR15	UINT32	ADCD1VCR15	ADC1CFGANDUSE_ADCD1VCR15_CNT_U32		Must be written at register level
22	Virtual Channel	VCR16	UINT32	ADCD1VCR16	ADC1CFGANDUSE_ADCD1VCR16_CNT_U32		Must be written at register level
23	Virtual Channel	VCR17	UINT32	ADCD1VCR17	ADC1CFGANDUSE_ADCD1VCR17_CNT_U32		Must be written at register level
24	Virtual Channel	VCR18	UINT32	ADCD1VCR18	ADC1CFGANDUSE_ADCD1VCR18_CNT_U32		Must be written at register level
25	Virtual Channel	VCR19	UINT32	ADCD1VCR19	ADC1CFGANDUSE_ADCD1VCR19_CNT_U32		Must be written at register level
26	Virtual Channel	VCR20	UINT32	ADCD1VCR20	ADC1CFGANDUSE_ADCD1VCR20_CNT_U32		Must be written at register level
27	Virtual Channel	VCR21	UINT32	ADCD1VCR21	ADCD1VCR21_CNT_U32		Must be written at register level
28	Virtual Channel	VCR22	UINT32	ADCD1VCR22	ADCD1VCR22_CNT_U32		Must be written at register level
29	Virtual Channel	VCR23	UINT32	ADCD1VCR23	ADCD1VCR23_CNT_U32		Must be written at register level
30	ADC Control	ADCR1	UINT8	ADCD1ADCR1	Unused	Unused parent register	May be written at field or register level
31	ADC Control	ADCR1	SUSMTD	ADCD1SUSMTD	00	Synchronous suspend - By design ADC groups shouldn't collide	May be written at field or register level
32	ADC Control	ADCR2	UINT8	ADCD1ADCR2	Unused	Unused parent register	May be written at field or register level
33	ADC Control	ADCR2	ADDNT	ADCD1ADDNT	0	Feature not used	May be written at field or register level
34	ADC Control	ADCR2	DFMT	ADCD1DFMT	1	1: Signed integer format	May be written at field or register level
35	Safety Control	SFTCR	UINT8	ADCD1SFTCR	Unused	Unused parent register	May be written at field or register level
36	Safety Control	SFTCR	IDEIE	ADCD1IDEIE	0	ID Error Interrupt - Disabled	May be written at field or register level
37	Safety Control	SFTCR	PEIE	ADCD1PEIE	0	Parity Error Interrupt - Disabled	May be written at field or register level
38	Safety Control	SFTCR	OWEIE	ADCD1OWEIE	0	Overwrite Error Interrupt - Disabled	May be written at field or register level
39	Safety Control	SFTCR	ULEIE	ADCD1ULEIE	0	Upper-limit/lower-limit Error Interrupt - Disabled	May be written at field or register level
40	Safety Control	SFTCR	RDCLRE	ADCD1RDCLRE	1	Perform read and clear	May be written at field or register level
41	Safety Control - UpperLower Limit	ULLMTBR0	UINT32	ADCD1ULLMTBR0	0	Upper-limit/lower-limit Error Interrupt - Disabled	May be written at field or register level
42	Safety Control - UpperLower Limit	ULLMTBR0	LLMTB	ADCD1LLMTB	Unused	Unused field of parent register	May be written at field or register level
43	Safety Control - UpperLower Limit	ULLMTBR0	ULMTB	ADCD1ULMTB	Unused	Unused field of parent register	May be written at field or register level
44	Safety Control - UpperLower Limit	ULLMTBR1	UINT32	ADCD1ULLMTBR1	0	Upper-limit/lower-limit Error Interrupt - Disabled	May be written at field or register level
45	Safety Control - UpperLower Limit	ULLMTBR2	UINT32	ADCD1ULLMTBR2	0	Upper-limit/lower-limit Error Interrupt - Disabled	May be written at field or register level
46	Safety Control - Wiring Break	ODCR	UINT32	ADCD1ODCR	0	Wiring break detection - not diagnosed	May be written at field or register level
47	Safety Control - Wiring Break	ODCR	ODPW	ADCD1ODPW	Unused	Unused field of parent register	May be written at field or register level
48	Safety Control - Wiring Break	ODCR	ODE	ADCD1ODE	Unused	Unused field of parent register	May be written at field or register level
49	Safety Control - Wiring Break	ODCR	ODDE	ADCD1ODDE	Unused	Unused field of parent register	May be written at field or register level
50	Safety Control - Wiring Break	ADOPDIG0	UINT32	ADCD1ADOPDIG1	0	0: Pulling up or pulling down the ADCDnIm pin is disabled	May be written at field or register level
51	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG000	ADCD1ADOPDIG000	Unused	Unused field of parent register	May be written at field or register level
52	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG001	ADCD1ADOPDIG001	Unused	Unused field of parent register	May be written at field or register level
53	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG002	ADCD1ADOPDIG002	Unused	Unused field of parent register	May be written at field or register level
54	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG003	ADCD1ADOPDIG003	Unused	Unused field of parent register	May be written at field or register level
55	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG004	ADCD1ADOPDIG004	Unused	Unused field of parent register	May be written at field or register level
56	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG005	ADCD1ADOPDIG005	Unused	Unused field of parent register	May be written at field or register level
57	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG006	ADCD1ADOPDIG006	Unused	Unused field of parent register	May be written at field or register level
58	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG007	ADCD1ADOPDIG007	Unused	Unused field of parent register	May be written at field or register level
59	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG008	ADCD1ADOPDIG008	Unused	Unused field of parent register	May be written at field or register level
60	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG009	ADCD1ADOPDIG009	Unused	Unused field of parent register	May be written at field or register level
61	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG010	ADCD1ADOPDIG010	Unused	Unused field of parent register	May be written at field or register level
62	Safety Control - Wiring Break	ADOPDIG0	ADOPDIG011	ADCD1ADOPDIG011	Unused	Unused field of parent register	May be written at field or register level
63	Transfer & Hold	THCR	UINT8	ADCD1THCR	0	Transfer and Hold is not used	May be written at field or register level
64	Transfer & Hold	THCR	ASMPMSK	ADCD1ASMPMSK	Unused	Unused field of parent register	May be written at field or register level
65	Transfer & Hold	THACR	UINT8	ADCD1THACR	0	Transfer and Hold is not used	May be written at field or register level
66	Transfer & Hold	THACR	SGS	ADCD1SGS	Unused	Unused field of parent register	May be written at field or register level
67	Transfer & Hold	THACR	HLDTE	ADCD1HLDTE	Unused	Unused field of parent register	May be written at field or register level
68	Transfer & Hold	THACR	HLDCTE	ADCD1HLDCTE	Unused	Unused field of parent register	May be written at field or register level
69	Transfer & Hold	THBCR	UINT8	ADCD1THBCR	0	Transfer and Hold is not used	May be written at field or register level
70	Transfer & Hold	THER	UINT8	ADCD1THER	0	Transfer and Hold is not used	May be written at field or register level
71	Transfer & Hold	THER	TH0E	ADCD1TH0E	Unused	Unused field of parent register	May be written at field or register level
72	Transfer & Hold	THER	TH1E	ADCD1TH1E	Unused	Unused field of parent register	May be written at field or register level
73	Transfer & Hold	THER	TH2E	ADCD1TH2E	Unused	Unused field of parent register	May be written at field or register level
74	Transfer & Hold	THER	TH3E	ADCD1TH3E	Unused	Unused field of parent register	May be written at field or register level
75	Transfer & Hold	THER	TH4E	ADCD1TH4E	Unused	Unused field of parent register	May be written at field or register level
76	Transfer & Hold	THER	TH5E	ADCD1TH5E	Unused	Unused field of parent register	May be written at field or register level
77	Transfer & Hold	THGSR	UINT16	ADCD1THGSR	0	Transfer and Hold is not used	May be written at field or register level
78	Transfer & Hold	THGSR	TH0GS	ADCD1TH0GS	Unused	Unused field of parent register	May be written at field or register level
79	Transfer & Hold	THGSR	TH1GS	ADCD1TH1GS	Unused	Unused field of parent register	May be written at field or register level
80	Transfer & Hold	THGSR	TH2GS	ADCD1TH2GS	Unused	Unused field of parent register	May be written at field or register level
81	Transfer & Hold	THGSR	TH3GS	ADCD1TH3GS	Unused	Unused field of parent register	May be written at field or register level
82	Transfer & Hold	THGSR	TH4GS	ADCD1TH4GS	Unused	Unused field of parent register	May be written at field or register level
83	Transfer & Hold	THGSR	TH5GS	ADCD1TH5GS	Unused	Unused field of parent register	May be written at field or register level
84	Scan Group 0	SGSTCR0	UINT8	ADCD1SGSTCR0	0	Not used, performs software start of Scan Group	May be written at field or register level
85	Scan Group 0	SGSTCR0	SGST	ADCD1SGST	Unused	Unused field of parent register	May be written at field or register level
86	Scan Group 0	Erlenbeck, Jason M: Don't move cells, parent register is a calculation SGCR0	UINT8	ADCD1SGCR0	0		Must be written at register level
87	Scan Group 0	SGCR0	TRGMD	Erlenbeck, Jason M: Don't use these register definitions, use whole word, one of the fields is missing ADCD1TRGMD	0	0 - Disabled, SG0 is triggered by SW	Must be written at register level
88	Scan Group 0	SGCR0	SCANMD	ADCD1SCANMD	0	0: Multicycle scan mode	Must be written at register level
89	Scan Group 0	SGCR0	ADSTARTE	ADCD1ADSTARTE	0	0: ADSTART is disabled	Must be written at register level
90	Scan Group 0	SGCR0	ADIE	* See notes *	0	Results are read via direct register read, no interrupt needed 0: INTADCDnIx is not output at the end of scan for SGx. 8/26/2015 - Field level access doesn't exist in header file. This entry is used in ADCD1SGCR0 derivation only	NA
91	Scan Group 0	SGVCSP0	UINT8	ADCD1SGVCSP0	0	Start pointer for Group 0 is fixed at 0 (minimum)	Must be written at register level
92	Scan Group 0	SGVCSP0	VCSP	ADCD1VCSP	Unused	Unused field of parent register	Must be written at register level
93	Scan Group 0	SGVCEP0	UINT8	ADCD1SGVCEP0	23	End pointer for Group 0 is fixed at 23 (maximum)	Must be written at register level
94	Scan Group 0	SGVCEP0	VCEP	ADCD1VCEP	Unused	Unused field of parent register	Must be written at register level
95	Scan Group 0	SGMCYCR0	UINT8	ADCD1SGMCYCR0	0	Perform scan group reads only once	Must be written at register level
96	Scan Group 0	SGMCYCR0	MCYC	ADCD1MCYC	Unused	Unused field of parent register	Must be written at register level
97	Scan Group 0	SGSR0	SGACT	ADCD1SGACT	Unused	Unused field of parent register	Must be written at register level
98	Scan Group 0	ULLMSR0	UINT8	ADCD1ULLMSR0	0	0H: Neither upper limit nor lower limit is checked.	Must be written at register level
99	Scan Group 0	ULLMSR0	ULS	ADCD1ULS	Unused	Unused field of parent register	Must be written at register level
100	Scan Group 1	SGSTCR1	UINT8	ADCD1SGSTCR1	0	Not used, performs software start of Scan Group	Must be written at register level
101	Scan Group 1	SGCR1	UINT8	ADCD1SGCR1	17		Must be written at register level
102	Scan Group 1	SGCR1	TRGMD	* See notes *	1	Field level access doesn't exist in header file. This entry is used in ADCD1SGCR1 derivation only	Must be written at register level
103	Scan Group 1	SGCR1	SCANMD	* See notes *	0	Field level access doesn't exist in header file. This entry is used in ADCD1SGCR1 derivation only	Must be written at register level
104	Scan Group 1	SGCR1	ADSTARTE	* See notes *	0	Field level access doesn't exist in header file. This entry is used in ADCD1SGCR1 derivation only	Must be written at register level
105	Scan Group 1	SGCR1	ADIE	* See notes *	1	Used to trigger DMA 8/26/2015 - Field level access doesn't exist in header file. This entry is used in ADCD1SGCR1 derivation only	Must be written at register level
106	Scan Group 1	SGVCSP1	UINT8	ADCD1SGVCSP1	21	Configured to be start of ADC Reference voltage group	Must be written at register level
107	Scan Group 1	SGVCEP1	UINT8	ADCD1SGVCEP1	23	Configured to be end of ADC Reference voltage group	Must be written at register level
108	Scan Group 1	SGMCYCR1	UINT8	ADCD1SGMCYCR1	0	Perform scan group reads only once	Must be written at register level
109	Scan Group 1	ULLMSR1	UINT8	ADCD1ULLMSR1	0	0H: Neither upper limit nor lower limit is checked.	Must be written at register level
110	Scan Group 2	SGSTCR2	UINT8	ADCD1SGSTCR2	0	Not used, performs software start of Scan Group	Must be written at register level
111	Scan Group 2	SGCR2	UINT8	ADCD1SGCR2	1		Must be written at register level
112	Scan Group 2	SGCR2	TRGMD	* See notes *	1	Field level access doesn't exist in header file. This entry is used in ADCD1SGCR2 derivation only	Must be written at register level
113	Scan Group 2	SGCR2	SCANMD	* See notes *	0	Field level access doesn't exist in header file. This entry is used in ADCD1SGCR2 derivation only	Must be written at register level
114	Scan Group 2	SGCR2	ADSTARTE	* See notes *	0	Field level access doesn't exist in header file. This entry is used in ADCD1SGCR2 derivation only	Must be written at register level
115	Scan Group 2	SGCR2	ADIE	* See notes *	0	Used to trigger DMA 8/26/2015 - Field level access doesn't exist in header file. This entry is used in ADCD1SGCR2 derivation only	Must be written at register level
116	Scan Group 2	SGVCSP2	UINT8	ADCD1SGVCSP2	ADC1CFGANDUSE_ADCD1SGVCSP2_CNT_U08		Must be written at register level
117	Scan Group 2	SGVCEP2	UINT8	ADCD1SGVCEP2	ADC1CFGANDUSE_ADCD1SGVCEP2_CNT_U08		Must be written at register level
118	Scan Group 2	SGMCYCR2	UINT8	ADCD1SGMCYCR2	0	Perform scan group reads only once	Must be written at register level
119	Scan Group 2	ULLMSR2	UINT8	ADCD1ULLMSR2	0	0H: Neither upper limit nor lower limit is checked.	Must be written at register level
120	Scan Group 3	SGSTCR3	UINT8	ADCD1SGSTCR3	0	Not used, performs software start of Scan Group	Must be written at register level
121	Scan Group 3	SGCR3	UINT8	ADCD1SGCR3	1		Must be written at register level
122	Scan Group 3	SGCR3	TRGMD	* See notes *	1	Field level access doesn't exist in header file. This entry is used in ADCD1SGCR3 derivation only	Must be written at register level
123	Scan Group 3	SGCR3	SCANMD	* See notes *	0	Field level access doesn't exist in header file. This entry is used in ADCD1SGCR3 derivation only	Must be written at register level
124	Scan Group 3	SGCR3	ADSTARTE	* See notes *	0	Field level access doesn't exist in header file. This entry is used in ADCD1SGCR3 derivation only	Must be written at register level
125	Scan Group 3	SGCR3	ADIE	* See notes *	0	Not used to trigger DMA 8/26/2015 - Field level access doesn't exist in header file. This entry is used in ADCD1SGCR3 derivation only	Must be written at register level
126	Scan Group 3	SGCR3	ADTSTARTE	ADCD1ADTSTARTE	Unused	Unused field of parent register	Must be written at register level
127	Scan Group 3	SGVCSP3	UINT8	ADCD1SGVCSP3	ADC1CFGANDUSE_ADCD1SGVCSP3_CNT_U08		Must be written at register level
128	Scan Group 3	SGVCEP3	UINT8	ADCD1SGVCEP3	ADC1CFGANDUSE_ADCD1SGVCEP3_CNT_U08		Must be written at register level
129	Scan Group 3	SGMCYCR3	UINT8	ADCD1SGMCYCR3	0	Perform scan group reads only once	Must be written at register level
130	Scan Group 3	SGSR3	ADTACT	ADCD1ADTACT	Unused	Unused field of parent register	Must be written at register level
131	Scan Group 3	ULLMSR3	UINT8	ADCD1ULLMSR3	0	0H: Neither upper limit nor lower limit is checked.	Must be written at register level
132	Scan Group 4	SGSTCR4	UINT8	ADCD1SGSTCR4	0	Not used, performs software start of Scan Group	Must be written at register level
133	Scan Group 4	SGCR4	UINT8	ADCD1SGCR4	0	Scan Group 4 is not used	Must be written at register level
134	Scan Group 4	SGVCSP4	UINT8	ADCD1SGVCSP4	23	Scan Group 4 is not used	Must be written at register level
135	Scan Group 4	SGVCEP4	UINT8	ADCD1SGVCEP4	23	Scan Group 4 is not used	Must be written at register level
136	Scan Group 4	SGMCYCR4	UINT8	ADCD1SGMCYCR4	0	Perform scan group reads only once	Must be written at register level
137	Scan Group 4	ULLMSR4	UINT8	ADCD1ULLMSR4	0	0H: Neither upper limit nor lower limit is checked.	Must be written at register level
138	*Read Only*
139	Scan Group 0	SGSR0	UINT8	ADCD1SGSR0	Read only	Status register
140	Scan Group 1	SGSR1	UINT8	ADCD1SGSR1	Read only	Status register
141	Scan Group 2	SGSR2	UINT8	ADCD1SGSR2	Read only	Status register
142	Scan Group 3	SGSR3	UINT8	ADCD1SGSR3	Read only	Status register
143	Scan Group 4	SGSR4	UINT8	ADCD1SGSR4	Read only	Status register
144	Data Register	DR00	UINT32	ADCD1DR00	Read Only
145	Data Register	DR00	DR01	ADCD1DR01	Read Only
146	Data Register	DR02	UINT32	ADCD1DR02	Read Only
147	Data Register	DR02	DR03	ADCD1DR03	Read Only
148	Data Register	DR04	UINT32	ADCD1DR04	Read Only
149	Data Register	DR04	DR05	ADCD1DR05	Read Only
150	Data Register	DR06	UINT32	ADCD1DR06	Read Only
151	Data Register	DR06	DR07	ADCD1DR07	Read Only
152	Data Register	DR08	UINT32	ADCD1DR08	Read Only
153	Data Register	DR08	DR09	ADCD1DR09	Read Only
154	Data Register	DR10	UINT32	ADCD1DR10	Read Only
155	Data Register	DR10	DR11	ADCD1DR11	Read Only
156	Data Register	DR12	UINT32	ADCD1DR12	Read Only
157	Data Register	DR12	DR13	ADCD1DR13	Read Only
158	Data Register	DR14	UINT32	ADCD1DR14	Read Only
159	Data Register	DR14	DR15	ADCD1DR15	Read Only
160	Data Register	DR16	UINT32	ADCD1DR16	Read Only
161	Data Register	DR16	DR17	ADCD1DR17	Read Only
162	Data Register	DR18	UINT32	ADCD1DR18	Read Only
163	Data Register	DR18	DR19	ADCD1DR19	Read Only
164	Data Register	DR20	UINT32	ADCD1DR20	Read Only
165	Data Register	DR20	DR21	ADCD1DR21	Read Only
166	Data Register	DR22	UINT32	ADCD1DR22	Read Only
167	Data Register	DR22	DR23	ADCD1DR23	Read Only
168	Data Register - Supplemental Information	DIR00	UINT32	ADCD1DIR00	Read Only
169	Data Register - Supplemental Information	DIR00	ID	ADCD1ID	Read Only
170	Data Register - Supplemental Information	DIR00	PRTY	ADCD1PRTY	Read Only
171	Data Register - Supplemental Information	DIR00	WFLG	ADCD1WFLG	Read Only
172	Data Register - Supplemental Information	DIR01	UINT32	ADCD1DIR01	Read Only
173	Data Register - Supplemental Information	DIR02	UINT32	ADCD1DIR02	Read Only
174	Data Register - Supplemental Information	DIR03	UINT32	ADCD1DIR03	Read Only
175	Data Register - Supplemental Information	DIR04	UINT32	ADCD1DIR04	Read Only
176	Data Register - Supplemental Information	DIR05	UINT32	ADCD1DIR05	Read Only
177	Data Register - Supplemental Information	DIR06	UINT32	ADCD1DIR06	Read Only
178	Data Register - Supplemental Information	DIR07	UINT32	ADCD1DIR07	Read Only
179	Data Register - Supplemental Information	DIR08	UINT32	ADCD1DIR08	Read Only
180	Data Register - Supplemental Information	DIR09	UINT32	ADCD1DIR09	Read Only
181	Data Register - Supplemental Information	DIR10	UINT32	ADCD1DIR10	Read Only
182	Data Register - Supplemental Information	DIR11	UINT32	ADCD1DIR11	Read Only
183	Data Register - Supplemental Information	DIR12	UINT32	ADCD1DIR12	Read Only
184	Data Register - Supplemental Information	DIR13	UINT32	ADCD1DIR13	Read Only
185	Data Register - Supplemental Information	DIR14	UINT32	ADCD1DIR14	Read Only
186	Data Register - Supplemental Information	DIR15	UINT32	ADCD1DIR15	Read Only
187	Data Register - Supplemental Information	DIR16	UINT32	ADCD1DIR16	Read Only
188	Data Register - Supplemental Information	DIR17	UINT32	ADCD1DIR17	Read Only
189	Data Register - Supplemental Information	DIR18	UINT32	ADCD1DIR18	Read Only
190	Data Register - Supplemental Information	DIR19	UINT32	ADCD1DIR19	Read Only
191	Data Register - Supplemental Information	DIR20	UINT32	ADCD1DIR20	Read Only
192	Data Register - Supplemental Information	DIR21	UINT32	ADCD1DIR21	Read Only
193	Data Register - Supplemental Information	DIR22	UINT32	ADCD1DIR22	Read Only
194	Data Register - Supplemental Information	DIR23	UINT32	ADCD1DIR23	Read Only

195	*Unused Features*
~~196~~	~~ADC Synchronization~~	~~ADSYNSTCR~~	~~UINT8~~	~~ADCD1ADSYNSTCR~~	~~Unused Feature - neither read or write~~	~~ADC0 & ADC1 are not synchronized with each other~~
~~197~~	~~ADC Synchronization~~	~~ADSYNSTCR~~	~~ADSTART~~	~~ADCD1ADSTART~~	~~Unused Feature - neither read or write~~	~~Unused field of parent register~~
~~198~~	~~ADC Synchronization~~	~~ADTSYNSTCR~~	~~UINT8~~	~~ADCD1ADTSYNSTCR~~	~~Unused Feature - neither read or write~~	~~ADC0 & ADC1 are not synchronized with each other~~
~~199~~	~~ADC Synchronization~~	~~ADTSYNSTCR~~	~~ADTSTART~~	~~ADCD1ADTSTART~~	~~Unused Feature - neither read or write~~	~~Unused field of parent register~~
200	ADC Control	SMPCR	UINT16	ADCD1SMPCR	Unused Feature - neither read or write	Configured for 1uSec conversion, other option is 11.3uSec (too long)
201	ADC Control	ADHALTR	UINT8	ADCD1ADHALTR	Unused Feature - neither read or write	Feature not used
202	ADC Control	ADHALTR	HALT	ADCD1HALT	Unused Feature - neither read or write	Unused field of parent register
203	External Multiplexer	MPXCURCR	UINT8	ADCD1MPXCURCR	Unused Feature - neither read or write	Feature not used
204	External Multiplexer	MPXCURCR	MSKCFMT	ADCD1MSKCFMT	Unused Feature - neither read or write	Unused field of parent register
205	External Multiplexer	MPXCURR	UINT32	ADCD1MPXCURR	Unused Feature - neither read or write	Feature not used
206	External Multiplexer	MPXCURR	MPXCUR	ADCD1MPXCUR	Unused Feature - neither read or write	Unused field of parent register
207	External Multiplexer	MPXCURR	MSKC	ADCD1MSKC	Unused Feature - neither read or write	Unused field of parent register
208	External Multiplexer	MPXOWR	UINT8	ADCD1MPXOWR	Unused Feature - neither read or write	Feature not used
209	External Multiplexer	MPXOWR	MPXOW	ADCD1MPXOW	Unused Feature - neither read or write	Unused field of parent register
210	Virtual Channel Monitor	ADENDP0	UINT8	ADCD1ADENDP0	Unused Feature - neither read or write	Feature not used
211	Virtual Channel Monitor	ADENDP0	ENDP	ADCD1ENDP	Unused Feature - neither read or write	Unused field of parent register
212	Virtual Channel Monitor	ADENDP1	UINT8	ADCD1ADENDP1	Unused Feature - neither read or write	Feature not used
213	Virtual Channel Monitor	ADENDP2	UINT8	ADCD1ADENDP2	Unused Feature - neither read or write	Feature not used
214	Virtual Channel Monitor	ADENDP3	UINT8	ADCD1ADENDP3	Unused Feature - neither read or write	Feature not used
215	Virtual Channel Monitor	ADENDP4	UINT8	ADCD1ADENDP4	Unused Feature - neither read or write	Feature not used
216	Safety Control	TDCR	UINT8	ADCD1TDCR	Unused Feature - neither read or write	Pin level self diagnosis is disabled
217	Safety Control	TDCR	TDLV	ADCD1TDLV	Unused Feature - neither read or write	Unused field of parent register
218	Safety Control	TDCR	TDE	ADCD1TDE	Unused Feature - neither read or write	Unused field of parent register
219	Safety Control	ECR	UINT8	ADCD1ECR	Unused Feature - neither read or write	Safety features not used
220	Safety Control	ECR	IDEC	ADCD1IDEC	Unused Feature - neither read or write	Unused field of parent register
221	Safety Control	ECR	PEC	ADCD1PEC	Unused Feature - neither read or write	Unused field of parent register
222	Safety Control	ECR	OWEC	ADCD1OWEC	Unused Feature - neither read or write	Unused field of parent register
223	Safety Control	ECR	ULEC	ADCD1ULEC	Unused Feature - neither read or write	Unused field of parent register
224	Safety Control	ULER	UINT8	ADCD1ULER	Unused Feature - neither read or write
225	Safety Control	ULER	ULECAP	ADCD1ULECAP	Unused Feature - neither read or write	Unused field of parent register
226	Safety Control	ULER	ULE	ADCD1ULE	Unused Feature - neither read or write	Unused field of parent register
227	Safety Control	OWER	UINT8	ADCD1OWER	Unused Feature - neither read or write
228	Safety Control	OWER	OWECAP	ADCD1OWECAP	Unused Feature - neither read or write	Unused field of parent register
229	Safety Control	OWER	OWE	ADCD1OWE	Unused Feature - neither read or write	Unused field of parent register
230	Safety Control	PER	UINT8	ADCD1PER	Unused Feature - neither read or write
231	Safety Control	PER	PECAP	ADCD1PECAP	Unused Feature - neither read or write	Unused field of parent register
232	Safety Control	PER	PE	ADCD1PE	Unused Feature - neither read or write	Unused field of parent register
233	Safety Control	IDER	UINT8	ADCD1IDER	Unused Feature - neither read or write
234	Safety Control	IDER	IDECAP	ADCD1IDECAP	Unused Feature - neither read or write	Unused field of parent register
235	Safety Control	IDER	IDE	ADCD1IDE	Unused Feature - neither read or write	Unused field of parent register
236	Transfer & Hold	THSMPSTCR	UINT8	ADCD1THSMPSTCR	Unused Feature - neither read or write	Transfer and Hold is not used
237	Transfer & Hold	THSMPSTCR	SMPST	ADCD1SMPST	Unused Feature - neither read or write	Unused field of parent register
238	Transfer & Hold	THSTPCR	UINT8	ADCD1THSTPCR	Unused Feature - neither read or write	Transfer and Hold is not used
239	Transfer & Hold	THSTPCR	THSTP	ADCD1THSTP	Unused Feature - neither read or write	Unused field of parent register
240	Transfer & Hold	THAHLDSTCR	UINT8	ADCD1THAHLDSTCR	Unused Feature - neither read or write	Transfer and Hold is not used
241	Transfer & Hold	THAHLDSTCR	HLDST	ADCD1HLDST	Unused Feature - neither read or write	Unused field of parent register
242	Transfer & Hold	THBHLDSTCR	UINT8	ADCD1THBHLDSTCR	Unused Feature - neither read or write	Transfer and Hold is not used
243	AD Timer	ADTSTCR3	UINT8	ADCD1ADTSTCR3	Unused Feature - neither read or write	AD Timer is not used
244	AD Timer	ADTSTCR3	ADTST	ADCD1ADTST	Unused Feature - neither read or write	Unused field of parent register
245	AD Timer	ADTENDCR3	UINT8	ADCD1ADTENDCR3	Unused Feature - neither read or write	AD Timer is not used
246	AD Timer	ADTENDCR3	ADTEND	ADCD1ADTEND	Unused Feature - neither read or write	Unused field of parent register
247	AD Timer	ADTSTCR4	UINT8	ADCD1ADTSTCR4	Unused Feature - neither read or write	AD Timer is not used
248	AD Timer	ADTENDCR4	UINT8	ADCD1ADTENDCR4	Unused Feature - neither read or write	AD Timer is not used
249	AD Timer	ADTIPR3	UINT32	ADCD1ADTIPR3	Unused Feature - neither read or write	AD Timer is not used
250	AD Timer	ADTIPR3	ADTIP	ADCD1ADTIP	Unused Feature - neither read or write	Unused field of parent register
251	AD Timer	ADTPRR3	UINT32	ADCD1ADTPRR3	Unused Feature - neither read or write	AD Timer is not used
252	AD Timer	ADTPRR3	ADTPR	ADCD1ADTPR	Unused Feature - neither read or write	Unused field of parent register
253	AD Timer	ADTIPR4	UINT32	ADCD1ADTIPR4	Unused Feature - neither read or write	AD Timer is not used
254	AD Timer	ADTPRR4	UINT32	ADCD1ADTPRR4	Unused Feature - neither read or write	AD Timer is not used

Sheet 2: Change Log

Date	Description
9/7/2016	Changed ADCD1SGCR1 from 1 to 17 to trigger DMA
	Changed ADCD1SGCR3 from 17 to 1 to not trigger DMA

2 - CM320A_Adc1CfgAndUse_Design_PeerReviewChkList

Nexteer_Template_V1.0

Overview

Peer Review Instructions
Technical Review Checklist
Template Change Log

Sheet 1: Peer Review Instructions

Instructions for Functional Design Package Peer Review

PRE-MEETING
	Function Owner	Confirm that requirements are reviewed and approved PRIOR to the FDP peer review
	Function Owner	Start with latest version of the template for any "first reviews" - Continue to use existing temmplate for re-reviews
	Function Owner	Provide the functional design package (changed documents) to the invited attendees 1-2 working days in advance of review
	Function Owner	Notify the assigned peer reviewer and make sure they are prepared to do their function in the meeting
	Function Owner	Identify necessary attendance and invite to meeting
	Function Owner	Complete the "Author" column information for sections 1 through 3 prior to the review
	Function Owner	Complete the attendance invitation list in section 5
	Function Owner	For Re-reviews only: Complete the column "remarks by author" to identify actions taken to address items found in earlier reviews.

DURING MEETING
	Function Owner	Present document changes to the review team
	Peer Reviewer	Capture attendance of the review
	Peer Reviewer	Capture actions and issues in section 4. Identify issue summary, Document type, Reference (Requirement ID, section number, etc), Defect Type and indicate status as "OPEN"

POST MEETING
	Function Owner	Follow up on all "open" items. Update "Summary of Resolution" to indicate what was done or decided.
	Function Owner	Schedule follow up review OR review open items with peer reviewer and obtain agreement to close
	Peer Reviewer	Close change request in system and confirm all associated tasks are complete. Upload peer review checklist (this document) with any FDP updates

Sheet 2: Technical Review Checklist

Technical Review Checklist - Template Version 01.00.09

Product Name

Electric Power Steering

Electrical Arch.

Review Scope

Defect Type

Numbers

Yes

Closed

Function Name

CM320A_Adc1CfgAndUse

Version

2.3.0

-Initialize Adc1DiagcStrtPtr and Adc1DiagcEndPtr in Adc1CfgAndUseInit1
-Updated CM320A_Adc1CfgAndUse_RegisterConfiguration.xlsm to use ADCD1SGCR1 to trigger DMA instead of ADCD1SGCR3 to trigger DMA

Requirement

Rejected

FDD

Author

Gerald McCann

Interface

Open

Model

Effort

Design

FMEA

Review Effort(Hrs.)

0.50

Standards

*.m File

Corr+Verf effort(Hrs.)

Documentation

Cal Process

Total Effort (Hrs.)

0.50

Others

Total

Checklist No.

Description of Check

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

Section 1: TECHNICAL CHECK

1.1

Confirm that all signal inputs into the FDP (Functional Design Package) are contained within and exactly named as the "Available_Nexteer_Signals.m" states.

Handled by Darryl's tool

Closed

1.2

Confirm any removed signal inputs from the design have been removed from the "Available_Nexteer_Signals.m" file.

Handled by Darryl's tool

Closed

1.3

Confirm all signals and parameters (outputs, calibrations, constants, non-volatile memory) used in the *.m file and the design conform to the AutoSAR naming convention documentation.

VerifyDD returns a couple errors "Name does not match required pattern."

Closed

1.4

Confirm *.m file has been provided to the "Available_Signal_Names" Author.

Handled by Darryl's tool

Closed

1.5

Confirm Electrical Systems interface map is updated to reflect the FDP (signal IO)

Handled by Darryl's tool

Closed

1.6

Confirm that Static Register evaluation has been completed and updated for any register data that is written to.

Closed

1.7

Have calibration default values been reviewed for correctness?

No cal changes

Closed

Section 2: Safety CHECK

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

2.1

Confirm that the functional DFMEA is up to date based on the design in the current package.

Closed

2.2

Confirm that Safety requirements (ASIL A - D) are referenced in the design documents.

Yes

Closed

Section 3: Lessons Learned

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

3.01

Have functions depending upon system state been reviewed for need to be executed at the 2ms rate to avoid system lag issues?

Closed

3.02

Have all diagnostics (NTCs) been confirmed to show logic to invoke a diagnostic "PASS" for control of the status byte at the customer level.

Yes

Closed

3.03

Has the requirements traceability steps used the RMI steps as defined in the FDD authoring spec to generate the traceability report?

Closed

3.04

Has the requirements traceability report been verified to only contain ONLY requirements from the FR.

Closed

3.05

Confirm that all PIM that does NOT have an initialization value of zero is initialized in an INIT function.

Yes

Closed

3.06

Confirm if NVM is used, the NVM is defined in structures

Closed

3.07

If the function uses NVM, confirm that the m file uses the SetBlockStatus to indicate a write at powerdown

Closed

3.08

Confirm NTCs are not set within an IRQ (not related to the typical periodic OS)

Closed

3.09

Confirm NTCs are not set or read in a periodic rate faster than 2 ms (ex. Motor Control Loop)

Yes

Closed

3.10

Constants check: Do all constants have the correct scope (local, global) and are they defined in the correct location (this FDD, ES/SF/AR999)?

Yes

Closed

3.11

Confirm all calibrations are required (ie they cannot be constants)

Closed

Section 4: Issues / Actions Identified

Document

Reference

Summary of resolution

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

4.12

4.13

4.14

4.15

4.16

4.17

4.18

4.19

4.20

4.21

4.22

4.23

4.24

4.25

Section 5: APPROVALS

Role

First Review

Date

Attendance

Approval?

Function Owner*

Gerald McCann

9/8/2016

Yes

Peer Reviewer*

Samanth Kumaraswamy

Yes

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Second Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Third Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Fourth Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Add more if necessary

Date

Attendance

Approval?

P.S.:

Yes indicates adherence

No indicates non-adherence, reviewer shall provide suitable comments at the end of this document for each point.

NA indicates not applicable

Sheet 3: Template Change Log

Rev	Change	Author
01.00.05	Added lesson learned #3.5	MDK
01.00.06	Added lesson learned #3.6, 3.7 - Structure and writing of NVM in mfiles and models.	MDK
01.00.07	Clarified 3.6 and 3.7 Added lessons learned for NTCs not being set in IRQs or periodics faster than 2ms/	MDK
01.00.08	Added section 1.6 to look for critical static register analysis	MDK
01.00.09	Added two checks - default cals and are all cals really required to be a calibration	MDK