This is the multi-page printable view of this section. Click here to print.

Return to the regular view of this page.

Component Implementation

1: AdcDiagc_IntegrationManual
2: AdcDiagc_MDD
3: AdcDiagc_PeerReviewCheckList
4: requirements

Component Implementation

Component Documentation

1 - AdcDiagc_IntegrationManual

Integration Manual

For

AdcDiagc

VERSION: 4.0

DATE: Aug 25, 2016

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA

Location: The official version of this document is stored in the Nexteer Configuration Management System.

Revision History

Sl. No.	Description	Author	Version	Date
1	Initial version	Rijvi Ahmed	1.0	02-Feb-2016
2	Updated per design rev. 1.1.0	Rijvi Ahmed	2.0	23-Mar-2016
3	Updated per design rev. 1.6.0	Avinash James	3.0	18-Jul-2016
4	Updated per design rev. 1.7.0	Avinash James	4.0	25-Aug-2016

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

Abbreviation	Description
DFD	Design functional diagram
MDD	Module design Document
	<ADD more to the table if applicable>

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.	Title	Version
1	FDD – CM340A-AdcDiagc_Design	See Synergy sub project version
2	Software Naming Conventions	Process 04.02.01
3	Software Design and Coding Standards	Process 04.02.01

Dependencies

SWCs

Module	Required Feature
None

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

Configuration REQUIREMeNTS

Build Time Config

Modules	Notes
None

Configuration Files to be provided by Integration Project

Da Vinci Parameter Configuration Changes

Parameter	Notes	SWC
Refer the .m file in the design

DaVinci Interrupt Configuration Changes

ISR Name	VIM #	Priority Dependency	Notes
N/A

Manual Configuration Changes

Constant	Notes	SWC
N/A

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer DataDict.m file

Required Global Data Outputs

Refer DataDict.m file

Specific Include Path present

None Runnable Scheduling

This section specifies the required runnable scheduling.

Init	Scheduling Requirements	Trigger
AdcDiagcInit1	None	RTE/Init

Runnable	Scheduling Requirements	Trigger
AdcDiagcPer1	None	RTE/2ms

Memory Map REQUIREMENTS

Mapping

Memory Section	Contents	Notes
None

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Feature	RAM	ROM
None

Table 1: ARM Cortex R4 Memory Usage

NvM Blocks

*See DataDict.m

Compiler Settings

Preprocessor MACRO

None.

Optimization Settings

None.

Appendix

None.

2 - AdcDiagc_MDD

Module Design Document

For

AdcDiagc

Aug 25, 2016

Prepared For:

Software Engineering

Nexteer Automotive,

Saginaw, MI, USA

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA
Change History

Description	Author	Version	Date
Initial Version	Rijvi Ahmed	1.0	02-Feb-2016
Updated per design rev. 1.1.0	Rijvi Ahmed	2.0	23-Mar-2016
Updated per design rev. 1.4.0	Avinash James	3.0	21-Jun-2016
Updated per design rev. 1.6.0	Avinash James	4.0	15-Jul-2016
Updated per design rev. 1.7.0	Avinash James	5.0	25-Aug-2016

Table of Contents

1 Introduction 5

1.1 Purpose 5

1.2 Scope 5

2 AdcDiagc & High-Level Description 6

3 Design details of software module 7

3.1 Graphical representation of AdcDiagc 7

3.2 Data Flow Diagram 7

3.2.1 Component level DFD 7

3.2.2 Function level DFD 7

4 Constant Data Dictionary 8

4.1 Program (fixed) Constants 8

4.1.1 Embedded Constants 8

5 Software Component Implementation 9

5.1 Sub-Module Functions 9

5.1.1 Init: AdcDiagcInit1 9

5.1.1.1 Design Rationale 9

5.1.1.2 Module Outputs 9

5.1.2 Per: AdcDiagcPer1 9

5.1.2.1 Design Rationale 9

5.1.2.2 Store Module Inputs to Local copies 9

5.1.2.3 (Processing of function)……… 9

5.1.2.4 Store Local copy of outputs into Module Outputs 9

5.2 Server Runables 9

5.2.1 SetAdcParFlt 9

5.2.1.1 Design Rationale 9

5.2.1.2 (Processing of function)……… 9

5.3 Interrupt Functions 10

5.4 Module Internal (Local) Functions 10

5.4.1 Local Function #1 10

5.4.1.1 Design Rationale 10

5.4.1.2 Processing 10

5.4.2 Local Function #2 10

5.4.2.1 Design Rationale 10

5.4.2.2 Processing 10

5.4.3 Local Function #3 10

5.4.3.1 Design Rationale 11

5.4.3.2 Processing 11

5.4.4 Local Function #4 11

5.4.4.1 Design Rationale 11

5.4.4.2 Processing 11

5.4.5 Local Function #5 11

5.4.5.1 Design Rationale 11

5.4.5.2 Processing 11

5.4.6 Local Function #6 11

5.4.6.1 Design Rationale 12

5.4.6.2 Processing 12

5.5 GLOBAL Function/Macro Definitions 12

6 Known Limitations with Design 13

7 UNIT TEST CONSIDERATION 14

Appendix A Abbreviations and Acronyms 15

Appendix B Glossary 16

Appendix C References 17

Introduction

Purpose

MDD for AdcDiagc

Scope

AdcDiagc & High-Level Description

Refer to FDD.

Design details of software module

Graphical representation of AdcDiagc

Data Flow Diagram

None.

Component level DFD

Refer FDD.

Function level DFD

Refer FDD.

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Constant Name	Resolution	Units	Value
MAXADCDIAGCST_CNT_U08	1	CNT	7U
Refer to the FDD
MASKFLTCNTR_CNT_U08	1	CNT	127U

Software Component Implementation

Sub-Module Functions

The sub-module functions are grouped based on similar functionality that needs to be executed in a given “State” of the system (refer States and Modes). For a given module, the MDD will identify the type and number of sub-modules required. The sub-module types are described below.

Init:

Design Rationale

None

Module Outputs

None

Per:

Design Rationale

Refer FDD.

Store Module Inputs to Local copies

Refer FDD

(Processing of function)………

Refer FDD

Store Local copy of outputs into Module Outputs

Refer FDD.

Server Runables

Interrupt Functions

None

Module Internal (Local) Functions

Local Function #1

Function Name	St2Proc	Type	Min	Max
Arguments Passed	AdcSelfDiag0_Volt_T_f32	float32	0.0	5.0
	AdcSelfDiag2_Volt_T_f32	float32	0.0	5.0
	AdcSelfDiag4_Volt_T_f32	float32	0.0	5.0
	AdcDiagcSt_Uls_T_u08	Uint8	0	3
	*RollgCntr_Cnt_T_u08	*uint8	0	255
Return Value	AdcNtcStInfo_Uls_T_u08	Uint8	0	255

Design Rationale

Processing

See “State 2” block in the Simulink model of the design.

Local Function #2

Function Name	St4Proc	Type	Min	Max
Arguments Passed	AdcSelfDiag0_Volt_T_f32	float32	0.0	5.0
	AdcSelfDiag2_Volt_T_f32	float32	0.0	5.0
	AdcSelfDiag4_Volt_T_f32	float32	0.0	5.0
	AdcDiagcSt_Uls_T_u08	Uint8	0	3
	*RollgCntr_Cnt_T_u08	*uint8	0	255
Return Value	AdcNtcStInfo_Uls_T_u08	Uint8	0	255

Design Rationale

Processing

See “State 4” block in the Simulink model of the design.

Local Function #3

Function Name	St6Proc	Type	Min	Max
Arguments Passed	AdcSelfDiag0_Volt_T_f32	float32	0.0	5.0
	AdcSelfDiag2_Volt_T_f32	float32	0.0	5.0
	AdcSelfDiag4_Volt_T_f32	float32	0.0	5.0
	AdcDiagcSt_Uls_T_u08	Uint8	0	3
	*RollgCntr_Cnt_T_u08	*uint8	0	255
Return Value	AdcNtcStInfo_Uls_T_u08	Uint8	0	255

Design Rationale

Processing

See “State 6” block in the Simulink model of the design.

Local Function #4

Function Name	St0Proc	Type	Min	Max
Arguments Passed	AdcSelfDiag0_Volt_T_f32	float32	0.0	5.0
	AdcSelfDiag2_Volt_T_f32	float32	0.0	5.0
	AdcSelfDiag4_Volt_T_f32	float32	0.0	5.0
	*RollgCntr_Cnt_T_u08	*uint8	00	3255
		*uint8	0	255
Return Value	AdcNtcStInfo_Uls_T_u08	Uint8	0	255

Design Rationale

Processing

See “State 0” block in the Simulink model of the design.

Local Function #5

Function Name	Adc0StBasdProc	Type	Min	Max
Arguments Passed	Adc0ParFlt_Cnt_T_u08	uint8	0	255
Return Value	None	N/A	N/A	N/A

Design Rationale

Processing

See “Adc0 State Based Processing” block in the Simulink model of the design.

Local Function #6

Function Name	Adc1StBasdProc	Type	Min	Max
Arguments Passed	Adc1ParFlt_Cnt_T_u08	uint8	0	255
Return Value	None	N/A	N/A	N/A

Design Rationale

Processing

See “Adc1 State Based Processing” block in the Simulink model of the design.

Local Function #7

Function Name	AdcDiagcPtrProc	Type	Min	Max
Arguments Passed	None	N/A	N/A	N/A
Return Value	None	N/A	N/A	N/A

Design Rationale

Processing

See “Adc Daigc Pointer” block in the Simulink model of the design.

Local Function #8

Function Name	ScanGroupAccrcyChk	Type	Min	Max
Arguments Passed	AdcScanGroupInpRefVltg_Volt_T_f32	float32	0.0	5.0
	AdcScanGroupRefVltg_Volt_T_f32	float32	0.0	5.0
	AdcScanGroupInpRefPrm_Cnt_T_u08	Uint8	0	255
Return Value	ScanGroupAccrcyChkRefPrm_Cnt_u08	Uint8	0	255

Design Rationale

Processing

See “Scan Group Accuracy Check” block in the Simulink model of the design.

Local Function #9

Function Name	SetAdcParFlt	Type	Min	Max
Arguments Passed	*Adc0ParFlt_Cnt_T_u08	Uint8	0	255
	*Adc1ParFlt_Cnt_T_u08	Uint8	0	255

Return Value

Design Rationale

Processing

See “Adc Parity Fault” block in the Simulink model of the design.

GLOBAL Function/Macro Definitions

Note: The server runnable of this component are non-rte. So they are actually global functions which should belong to this section. But as they are already described under Server Runnable section so it’s omitted here.

Known Limitations with Design

None.

UNIT TEST CONSIDERATION

The overflow for the following PIMs are intentional as they are used as rolling counter.

Rte_Pim_Adc0FltCntSt0

Rte_Pim_Adc0FltCntSt2

Rte_Pim_Adc0FltCntSt4

Rte_Pim_Adc0FltCntSt6

Rte_Pim_Adc1FltCntSt0

Rte_Pim_Adc1FltCntSt2

Rte_Pim_Adc1FltCntSt4

Rte_Pim_Adc1FltCntSt6

Abbreviations and Acronyms

Abbreviation or Acronym	Description

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

ISO 9000
ISO/IEC 12207
ISO/IEC 15504
Automotive SPICE® Process Reference Model (PRM)
Automotive SPICE® Process Assessment Model (PAM)
ISO/IEC 15288
ISO 26262
IEEE Standards
SWEBOK
PMBOK
Existing Nexteer Automotive documentation

Term	Definition	Source
MDD	Module Design Document
DFD	Data Flow Diagram

References

Ref. #	Title	Version
1	AUTOSAR Specification of Memory Mapping (Link:AUTOSAR_SWS_MemoryMapping.pdf)	v1.3.0 R4.0 Rev 2
2	MDD Guideline	EA4 01.00.01
3	Software Naming Conventions.doc	1.0
4	Software Design and Coding Standards.doc	2.1
5	FDD - CM340A_AdcDiagc_Design	See Synergy sub project version

3 - AdcDiagc_PeerReviewCheckList

Overview

Summary Sheet
Synergy Project
Davinci Files
Src (CDD_AdcDiagc.c)
MDD
PolySpace
Integration Manual

Sheet 1: Summary Sheet

Rev 1.2

8-Jun-15

Peer Review Summary Sheet

Synergy Project Name:

kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. CM340A_AdcDiagc_Impl

Revision / Baseline:

kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. 1.4.0

Change Owner:

kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Avinash James

Work CR ID:

EA4#6957

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

Yes

MDD

Yes

Source Code

Yes

PolySpace

Yes

Integration Manual

Yes

Davinci Files

Comments:

General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include FDD Owner and Integrator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.

Sheet 2: Synergy Project

Peer Review Meeting Log (Component Synergy Project Review)

Quality Check Items:

Rationale is required for all answers of No

New baseline version name from Summary Sheet follows

Yes

Comments:

naming convention

Project contains necessary subprojects

Yes

Comments:

Project contains the correct version of subprojects

Yes

Comments:

Design subproject is correct version

Yes

Comments:

General Notes / Comments:

LN: Intended Use: Identify who were the reviewers and if the reviewed changes have been approved. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. KMC: Group Review Level removed in Rev 4.0 since the design review is not checked in until approved, so it would always be DR4. Review Board:

Change Owner:

Avinash James

Review Date :

08/26/16

Lead Peer Reviewer:

Rijvi Ahmed

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 3: Davinci Files

Rev 1.2

8-Jun-15

Peer Review Meeting Log (Davinci Review)

Quality Check Items:

Rationale is required for all answers of No

Only StdDef Port types are used

Yes

Comments:

For components not using application data types, do all

N/A

Comments:

port interface names end in PortIf and a sequence number

Non-program-specific components saved

Yes

Comments:

in Autosar 4.0.3 format

*Cfg.arxml.TT: Verfied Davinci Configurator imported the

Yes

Comments:

N/A for the changes

change correctly

*Cfg.h.TT: Verfied Davinci Configurator generates

Yes

Comments:

N/A for the changes

the configuration header(s) file correctly

kzshz2: Either a generic sandbox or a baselined integration project can be used to verify

All changed files have been compared against previous

Yes

Comments:

versions (If available)

kzshz2: Intended Use: Identify if previous version was compared and only the expected change(s) was present. This is for text files only, not binary or GUIs Rationale: This is helpful in identifying unapproved (intended or mistaken) changes.

Automated validation check is performed

Yes

Comments:

Naming conventions followed. All names should

N/A

Comments:

N/A for the changes

match DataDict.m

Sender/Receiver port properties match DataDict.m

N/A

Comments:

N/A for the changes

file (use .m file helper tool)

Calibration port properties match DataDict.m

N/A

Comments:

N/A for the changes

file (use .m file helper tool)

Components using application data types:

Sender/Receiver port initialization values match

N/A

Comments:

DataDict.m file

Calibration port initialization values match

N/A

Comments:

DataDict.m file

Components not using application data types:

Sender/Receiver port initialization values match

N/A

Comments:

DataDict.m file and have been converted to counts

for fixed point types

Calibration port initialization values match

N/A

Comments:

N/A for the changes

DataDict.m file and have been converted to counts

for fixed point types

Mapping set and all unused items have been

N/A

Comments:

N/A for the changes

removed

All sender/receiver port read/writes using direct

N/A

Comments:

read/writes(List justification if not)

Runnable calling frequencies match FDD

N/A

Comments:

DataDict.m display variables: created as

N/A

Comments:

PerInstanceMemory. Matches the FDD

Component is correct component type

Yes

Comments:

General Notes / Comments:

Reviewed only for the changes

Change Owner:

Avinash James

Review Date :

08/26/16

Component Type :

CDD

Lead Peer Reviewer:

Rijvi Ahmed

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 4: Src (CDD_AdcDiagc.c)

Rev 1.2

8-Jun-15

Peer Review Meeting Log (Source Code Review)

Source File Name:

CDD_AdcDiagc.c

Source File Revision:

Header File Name:

Header File Revision:

kzshz2: Intended Use: Identify which version of the source file is being review. Rationale: Required for traceability between source code and review. Auditors will likely require this.

MDD Name:

AdcDiagc_MDD.docx

Revision:

FDD/SCIR/DSR/FDR/CM Name:

CM340A_AdcDiagc_Design

Revision:

1.7.0

Quality Check Items:

Rationale is required for all answers of No

Working EA4 Software Naming Convention followed:

for variable names

Yes

Comments:

for constant names

Yes

Comments:

for function names

Yes

Comments:

for other names (component, memory

Yes

Comments:

mapping handles, typedefs, etc.)

All paths assign a value to outputs, ensuring

Yes

Comments:

all outputs are initialized prior to being written

Requirements Tracability tags in code match the requirements tracability in the FDD

Yes

Comments:

requirements tracability in the FDD

All variables are declared at the function level.

Yes

Comments:

Synergy version matches change history

kzshz2: Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). Rationale: There have been many occassions where versions were not updated in files and as a result Unit Test were referencing wrong versions. This often time leads to the need to re-run of batch tests.

Yes

Comments:

and Version Control version in file comment block

Change log contains detailed description of changes

Yes

Comments:

and Work CR number

Code accurately implements FDD (Document or Model)

Yes

Comments:

Verified no Compiler Errors or Warnings

KMC: Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). Rationale: This is needed to ensure there will be no errors discovered at the time of integration. A Sandox project should be used; QAC can find compiler errors but not warnings.

Yes

Comments:

Component.h is included

N/A

Comments:

All other includes are actually needed. (System includes

Yes

Comments:

only allowed in Nexteer library components)

Software Design and Coding Standards followed:

Version: 2.1

Code comments are clear, correct, and adequate

Yes

Comments:

and have been updated for the change: [N40] and

all other rules in the same section as rule [N40],

plus [N75], [N12], [N23], [N33], [N37], [N38],

[N48], [N54], [N77], [N79], [N72]

Source file (.c and .h) comment blocks are per

Yes

Comments:

standards and contain correct information: [N41], [N42]

Function comment blocks are per standards and

Yes

Comments:

contain correct information: [N43]

Code formatting (indentation, placement of

Yes

Comments:

braces, etc.) is per standards: [N5], [N55], [N56],

[N57], [N58], [N59]

Embedded constants used per standards; no

Yes

Comments:

"magic numbers": [N12]

Memory mapping for non-RTE code

Yes

Comments:

is per standard

All execution-order-dependent code can be

Yes

Comments:

recognized by the compiler: [N80]

All loops have termination conditions that ensure

N/A

Comments:

finite loop iterations: [N63]

All divides protect against divide by zero

N/A

Comments:

if needed: [N65]

All integer division and modulus operations

N/A

Comments:

handle negative numbers correctly: [N76]

All typecasting and fixed point arithmetic,

N/A

Comments:

including all use of fixed point macros and

timer functions, is correct and has no possibility

of unintended overflow or underflow: [N66]

All float-to-unsiged conversions ensure the.

N/A

Comments:

float value is non-negative: [N67]

All conversions between signed and unsigned

N/A

Comments:

types handle msb==1 as intended: [N78]

All pointer dereferencing protects against

Yes

Comments:

null pointer if needed: [N70]

Component outputs are limited to the legal range

N/A

Comments:

defined in the FDD DataDict.m file : [N53]

All code is mapped with FDD (all FDD

Yes

Comments:

subfunctions and/or model blocks identified

with code comments; all code corresponds to

some FDD subfunction and/or model block): [N40]

Review did not identify violations of other

Yes

Comments:

coding standard rules

Anomaly or Design Work CR created

N/A

Comments:

for any FDD corrections needed

General Notes / Comments:

Change Owner:

Avinash James

Review Date :

08/26/16

Lead Peer Reviewer:

Rijvi Ahmed

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 5: MDD

Rev 1.2

8-Jun-15

Peer Review Meeting Log (MDD Review)

MDD Name:

AdcDiagc_MDD.docx

MDD Revision:

Source File Name:

CDD_AdcDiagc.c

Source File Revision:

Source File Name:

Source File Revision:

Source File Name:

Source File Revision:

Quality Check Items:

Rationale is required for all answers of No

Synergy version matches document

Yes

Comments:

Change log contains detailed description of changes

Yes

Comments:

Changes Highlighted (for Unit Tester)

Yes

Comments:

Diagrams have been included per MDD Guideline

Yes

Comments:

and reviewed

All Design Exceptions and Limitations are listed

N/A

Comments:

Design rationale given for all global

N/A

Comments:

data not communicated through RTE ports, per

Design and Coding Standards rules [N9] and [N10].

All implementation details that differ from the FDD are

N/A

Comments:

noted and explained in Design Rationale

All Unit Test Considerations have been described

Yes

Comments:

General Notes / Comments:

Change Owner:

Avinash James

Review Date :

08/26/16

Lead Peer Reviewer:

Rijvi Ahmed

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 6: PolySpace

Rev 1.2

8-Jun-15

Peer Review Meeting Log (QAC/PolySpace Review)

Source File Name:

CDD_AdcDiagc.c

Source File Revision:

Source File Name:

Source File Revision:

Source File Name:

Source File Revision:

EA4 Static Analysis Compliance Guideline version:

1.1.0

Poly Space version:

Windows User: eg. 2013b 2013b

Polyspace sub project version:

Windows User: eg. TL108a_PolyspaceSuprt_1.0.0 N/A

QAC version:

Windows User: eg 8.1.1-R 8.1.1-R

QAC sub project version:

Windows User: eg. TL_100A_1.1.0 1.2.0

Quality Check Items:

Rationale is required for all answers of No

Contract Folder's header files are appropriate and

kzshz2: Intended Use: Identify that the contract folder contains only the information required for this component. All other variables, constants, function prototypes, etc. should be removed. Rationale: This will help avoid unit testers having to considers object not used. It will also avoid having other files required for QAC.

Yes

Comments:

function prototypes match the latest component version

100% Compliance to the EA4 Static Analysis

Yes

Comments:

Compliance Guideline

Are previously added justification and deviation

Yes

Comments:

comments still appropriate

Do all MISRA deviation comments use approved

Yes

Comments:

deviation tags

Cyclomatic complexity and Static path count OK

Creager, Kathleen: use Browse Function Metrics, STCYC and STPTH

Yes

Comments:

for all functions in the component per Design

and Coding Standards rule [N47]

General Notes / Comments:

Change Owner:

Avinash James

Review Date :

08/26/16

Lead Peer Reviewer:

Rijvi Ahmed

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 7: Integration Manual

Rev 1.2

8-Jun-15

Peer Review Meeting Log (Integration Manual Review)

Integration Manual Name:

kzshz2: Intended Use: Identify which file is being reviewed Rationale: Required for traceability. It will help to ensure this sheet is not attached to the wrong design review form. AdcDiagc_IntegrationManual.doc

Integration Manual Revision:

kzshz2: Intended Use: Identify which version of the integration manual has been reviewed. Rationale: Required for traceability between the MDD and review. Auditors will likely require this. 4

Quality Check Items:

Rationale is required for all answers of No

Synergy version matches header

Yes

Comments:

Latest template used

Yes

Comments:

Change log contains detailed description of changes

Yes

Comments:

Changes Highlighted (for Integrator)

Yes

Comments:

General Notes / Comments:

Change Owner:

Avinash James

Review Date :

08/26/16

Lead Peer Reviewer:

Rijvi Ahmed

Approved by Reviewer(s):

Yes

Other Reviewer(s):

4 - requirements

FDD	ID	Source	Function	Line(s)	Status	Comment
		.SwFileName	.SwFuncName	.SwLines	.SwStatus	.SwComment
CM340A	216	CDD_AdcDiagc.c	Adc0StBasdProc	973-997	I
CM340A	151	CDD_AdcDiagc.c	Adc1StBasdProc	1046-1051	I
CM340A	153	CDD_AdcDiagc.c	Adc1StBasdProc	1046-1051	I
CM340A	152	CDD_AdcDiagc.c	Adc1StBasdProc	1046-1051	I
CM340A	154	CDD_AdcDiagc.c	Adc1StBasdProc	1046-1051	I
CM340A	217	CDD_AdcDiagc.c	Adc1StBasdProc	1095-1119	I
CM340A	194	CDD_AdcDiagc.c	AdcDiagcPer1	858	I
CM340A	134	CDD_AdcDiagc.c	Adc1StBasdProc	1095-1119	I
CM340A	191	CDD_AdcDiagc.c	Adc0StBasdProc	920-924	I
CM340A	190	CDD_AdcDiagc.c	Adc0StBasdProc	920-924	I
CM340A	192	CDD_AdcDiagc.c	Adc0StBasdProc	920-924	I
CM340A	115	CDD_AdcDiagc.c	Adc0StBasdProc	940-946	I
CM340A	164	CDD_AdcDiagc.c	Adc1StBasdProc	1053-1058	I
CM340A	117	CDD_AdcDiagc.c	Adc0StBasdProc	940-946	I
CM340A	116	CDD_AdcDiagc.c	Adc0StBasdProc	940-946	I
CM340A	163	CDD_AdcDiagc.c	Adc1StBasdProc	1053-1058	I
CM340A	136	CDD_AdcDiagc.c	Adc1StBasdProc	1095-1119	I
CM340A	112	CDD_AdcDiagc.c	AdcDiagcPer1	858	I
CM340A	80	CDD_AdcDiagc.c	AdcDiagcPer1	858	I
CM340A	173	CDD_AdcDiagc.c	Adc0StBasdProc,Adc1StBasdProc	920-924,926-931,933-938,940-946,1040-1044,1046-1051,1053-1058,1060-1066	I
CM340A	118	CDD_AdcDiagc.c	Adc0StBasdProc	940-946	I
CM340A	171	CDD_AdcDiagc.c	Adc1StBasdProc	1060-1066	I
CM340A	170	CDD_AdcDiagc.c	Adc1StBasdProc	1060-1066	I
CM340A	203	CDD_AdcDiagc.c	Adc1StBasdProc	1095-1119	I
CM340A	22	CDD_AdcDiagc.c	Adc0StBasdProc	973-997	I
CM340A	160	CDD_AdcDiagc.c	Adc1StBasdProc	1053-1058	I
CM340A	211	CDD_AdcDiagc.c	SetAdcParFlt	1362-1382	I
CM340A	28	CDD_AdcDiagc.c	Adc0StBasdProc	973-997	I
CM340A	105	CDD_AdcDiagc.c	AdcDiagcPtrProc	1150	I
CM340A	172	CDD_AdcDiagc.c	Adc1StBasdProc	1060-1066	I
CM340A	162	CDD_AdcDiagc.c	Adc1StBasdProc	1053-1058	I
CM340A	189	CDD_AdcDiagc.c	Adc0StBasdProc,AdcDiagcPtrProc	920-924,1135	I
CM340A	146	CDD_AdcDiagc.c	Adc1StBasdProc	1040-1044	I
CM340A	200	CDD_AdcDiagc.c	Adc0StBasdProc,Adc1StBasdProc	973-997,1040-1044	I
CM340A	144	CDD_AdcDiagc.c	Adc1StBasdProc	1040-1044	I
CM340A	145	CDD_AdcDiagc.c	Adc1StBasdProc	1040-1044	I
CM340A	204	CDD_AdcDiagc.c	AdcDiagcPer1,Adc0StBasdProc,Adc1StBasdProc	816-863,952-971,1074-1093	I
CM340A	206	CDD_AdcDiagc.c	SetAdcParFlt	1362-1382	I
CM340A	99	CDD_AdcDiagc.c	Adc0StBasdProc	926-931	I
CM340A	98	CDD_AdcDiagc.c	Adc0StBasdProc	926-931	I
CM340A	108	CDD_AdcDiagc.c	Adc0StBasdProc	933-938	I
CM340A	109	CDD_AdcDiagc.c	Adc0StBasdProc	933-938	I
CM340A	132	CDD_AdcDiagc.c	Adc1StBasdProc	1095-1119	I
CM340A	169	CDD_AdcDiagc.c	Adc1StBasdProc	1060-1066	I
CM340A	70	CDD_AdcDiagc.c	AdcDiagcPer1	816-863	I
CM340A	102	CDD_AdcDiagc.c	AdcDiagcPer1	858	I
CM340A	106	CDD_AdcDiagc.c	Adc0StBasdProc,AdcDiagcPtrProc	933-938,1145	I
CM340A	107	CDD_AdcDiagc.c	Adc0StBasdProc	933-938	I
CM340A	97	CDD_AdcDiagc.c	Adc0StBasdProc	926-931	I
CM340A	96	CDD_AdcDiagc.c	Adc0StBasdProc,AdcDiagcPtrProc	926-931,1140	I
CM340A	16	CDD_AdcDiagc.c	AdcDiagcPer1	816-863	I
CM340A	31	CDD_AdcDiagc.c	Adc0StBasdProc	973-997	I
CM340A	122	CDD_AdcDiagc.c	Adc0StBasdProc	973-997	I
CM340A	130	CDD_AdcDiagc.c	Adc1StBasdProc	1095-1119	I
CM340A	215	CDD_AdcDiagc.c	SetAdcParFlt	1362-1382	I