FDD CM-600X provides the interface to the ES FDDs which need to communicate with the external peripherals connected to the main micro through CSIG0 SPI channel. RENESAS AUTOSAR SPI driver is used to achieve the communication requirements. CM-600A constitutes the required configurations of RENESAS AUTOSAR SPI DRIVER for communicating with PwrSply/TmplMonr IC through CSIG0 SPI channel. This document also contains the API (client/server functions) descriptions used for communicating with PwrSply/TmplMonr IC using CSIG0.

Following picture depicts the top level interface.

Note: Implementation of CM600A will be a part of the RENESAS AUTOSAR SPI driver component which represents the driver configuration and APIs (or interfaces) specific to CSIG0 SPI channel used for PwrSply/TmplMonr IC.

Derived Requirements

None.

Sub-Function Data Flow

None.

Design Rationale

None.

Sub-Functions

Sub-Function:

None.

Following version (version used in Synergy) of RENESAS AUTOSAR SPI driver is used to make the configurations for CSIG0.

Spi_Renesas_Ar4.0.3_01.05.00_0

RENESAS SPI driver is developed following the AUTOSAR SPI driver/handler specifications. So the following definitions from the AUTOSAR SPI driver specification need to be realized to understand the configuration.

Definition:	Description:
Channel	A Channel is a software exchange medium for data that are defined with the same criteria: Config. Parameters, Number of Data elements with same size and data pointers (Source & Destination) or location.
Job	A Job is composed of one or several Channels with the same Chip Select (is not released during the processing of Job). A Job is considered atomic and therefore cannot be interrupted by another Job. A Job has an assigned priority.
Sequence	A Sequence is a number of consecutive Jobs to transmit but it can be rescheduled between Jobs using a priority mechanism. A Sequence transmission is interruptible (by another Sequence transmission) or not depending on a static configuration.

For simplicity and to make sure the minimal changes of this FDD for any future changes in the ES function (which uses/depends on this FDD) it is decided to define the Channel, Job and Sequence as following.

Channel: A bunch of channels are defined which can be used to transmit read/write command for any register to the PwrSply/TmplMonr IC. No channel ID is specific to any particular register. So any channel can be used for any register read/write operation.

Job: For each of the channel a job is defined. So one job contains only one channel.

Sequence: For each of the job a sequence is defined. So one sequence contains only one job.

Note: Sequence is used to initiate a transmission. Channel maintains the Tx/Rx buffer. Each sequence is tied with one specific channel.

SPI driver configuration constitutes three main sections/containers – ‘SpiDriver’, ‘SpiGeneral’ and ‘SpiPublishedInformation’. The last two containers contain the general configurations which are common for all Spi channels used and hence fixed for a program or for all program. So only the container ‘SpiDriver’ contains the peripheral specific configurations which is PwrSply/TmplMonr IC.

SPI Driver Configurations (General)

Table below contains the configurations for ‘SpiGeneral’ and ‘SpiPublishedInformation’ containers.

Configuration Parameter	Value	Rationale	Remark

Container: Spi/SpiPublishedInformation
Short Name	SpiPublishedInformation
Max Hw Unit	5	Five Hw units are available in Renesas R7F701311 device. CSIG0, CSIH0, CSIH1, CSIH2, and CSIH3	This parameter can be made to 3 as CSIH1 and CSIH3 do not use RENESAS Spi driver for communication with its peripheral.

Container: Spi/SpiGeneral
Short Name	SpiGeneral
Already Init Det Check	FALSE		Recommended to be retained TRUE during development phase
Cancel Api	FALSE	Switches the Spi_Cancel function ON or OFF. Not required per current requirement.
Channel Buffers Allowed	0	0 = Internal Buffer. 1 = External Buffer. There will not be more than 128 words transactions required. Hence IB should suffice.
Critical Section Protection	TRUE	Interrupt blocking time by SchM is around 1us
Data Consistency Check Enable	TRUE	It is recommended to enable this as per the Safety Application Note
Data Width Selection	BITS_16	Both Gate Drive and Power Supply have max of 16 bit SPI transfers
Dev Error Detect	FALSE		Recommended to be retained TRUE during development phase
Device Name	R7F701311
Dma Mode	FALSE	Not required as the data length is not so big
Dma Type Used	SPI_DMA_TYPE_TWO	This parameter could be configured to only one value.
High Priority Hw Handling Enable	FALSE	Currently no requirement is seen for this.
Hw Status Api	FALSE	Currently no requirement is seen for this API.
Interruptible Seq Allowed	FALSE	Currently no requirement is seen for this functionality.
Level Delivered	1	Current assumption is to use Asynchronous mode with interrupt based job processing.
Max Baudrate	PCLK_DIV_BY_8	Maximum acceptable baud rate for the Job should be less than or equal to PCLK/8 (which is 10Mbps)
Persistent HW Configuration	TRUE	Enabled from safety perspective
Seq Start Notification Enable	FALSE
Support Concurrent Sync Transmit	FALSE	This is not applicable for Level 1
Sync Seq End Notification Enable	FALSE	This is not applicable for Level 1
Time Out	65535
Version Check External Modules	TRUE	Enabled from safety perspective
Version Info Api	FALSE

The DEM error reporting related configuration is also common for all Spi channels though this resides under the ‘SpiDrivers’ container. Table below contains DEM error reporting configuration.

Configuration Parameter	Value	Rationale	Remark

Container: Spi/SpiDrivers/SpiDriver/SpiDemEventParameterRefs

Short Name	SpiDemEventParameterRefs
E DATA TX TIMEOUT FAILURE	SPI_ E_DATA_TX_TIMEOUT_FAILURE	Reference to the DemEventParameter which shall be issued when a time out error was detected
E HARDWARE ERROR	SPI_ E_HARDWARE_ERROR	Reference to the DemEventParameter which shall be issued when a hardware error was detected

SPI Driver Configurations (PwrSply/TmplMonr specific)

Container/section ‘SpiDriver’ contains the PwrSply/TmplMonr specific configurations which are divided into the following sub containers:

SpiChannels

SpiDmas

SpiExternalDevices

SpiJobs

SpiMemoryModes

SpiSequences

SpiDemEventParameterRefs

Table below contains all of the channels definitions for PwrSply/TmplMonr which resides under the container ‘SpiChannels’.

Configuration Parameter	Value	Rationale	Remark

Container: Spi/SpiDrivers/SpiDriver/SpiChannels

Short Name	TmplMonrCh1		Configuration for TmplMonr channel 1
Channel Id	52	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	TmplMonrCh2		Configuration for TmplMonr channel 2
Channel Id	53	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	TmplMonrCh3		Configuration for TmplMonr channel 3
Channel Id	54	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	TmplMonrCh4		Configuration for TmplMonr channel 4
Channel Id	55	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	TmplMonrCh5		Configuration for TmplMonr channel 5
Channel Id	56	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	PwrSplyCh1		Configuration for PwrSply channel 1
Channel Id	57	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	PwrSplyCh2		Configuration for PwrSply channel 2
Channel Id	58	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	PwrSplyCh3		Configuration for PwrSply channel 3
Channel Id	59	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	PwrSplyCh4		Configuration for PwrSply channel 4
Channel Id	60	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	PwrSplyCh5		Configuration for PwrSply channel 5
Channel Id	61	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	PwrSplyCh6		Configuration for PwrSply channel 6
Channel Id	62	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	PwrSplyCh7		Configuration for PwrSply channel 7
Channel Id	63	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	PwrSplyCh8		Configuration for PwrSply channel 8
Channel Id	64	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	PwrSplyCh9		Configuration for PwrSply channel 9
Channel Id	65	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Short Name	PwrSplyCh10		Configuration for PwrSply channel 10
Channel Id	66	To be assigned in sequence
Channel Type	IB	This prevents additional variable requirements from the Application software
Data Width	15	All SPI sequences are 16 bits long which contains 15 bits of data and 1 bit parity
Default Data	0	Better to set a value which requests a Read of the corresponding Register
Eb Max Length	1	EB is not used. Hence this parameter is not applicable.
Ib NBuffers	1	For all the cases, a 1 size for IB NBuffer would suffice.
Transfer Start	MSB	Communicate with MSB first.

Note: The channel ids used in the above table is for reference only and do not represent the actual channel number in the implementation.

Table below contains DMA related configuration of PwrSply/TmplMonr which resides under the container ‘SpiDmas’.

Configuration Parameter	Value	Rationale	Remark

Container: Spi/SpiDrivers/SpiDriver/SpiDmas

	NONE

Table below contains external device configuration for PwrSply/TmplMonr which resides under the container ‘SpiExternalDevices’.

Configuration Parameter	Value	Rationale	Remark

Container: Spi/SpiDrivers/SpiDriver/SpiExternalDevices

Short Name	PwrSplyTmplMonr
Baudrate Configuration	10	Required baudrate is 1Mbps. This is achieved using 2 parameters m and k, where k is configured in ‘Baudrate Configuration’, and m is configured in ‘Input Clock Select’. Baudrate = Pclk/((2^m) * k * 2) Pclk = 80Mhz. To achieve 1Mbps, M = 2 K = 10
Baudrate Register Select	CSIH_BAUDRATE_REGISTER_0
Baudrate	0	Unused parameter
Broadcasting Priority	DOMINANT (default)	This parameter is applicable only when priority implementation is used.
Clk2 Cs Count	5	To be adjusted to achieve 30ns
Clock Frequency Ref	McuHighspeedPeriClk
Cs Hold Timing	HOLD_TIME_0_POINT_5	Not sure about the difference between this parameter and ‘Clk2 Cs Count’. Mantis ticket 0026854 raised for clarification
Cs Identifier	NULL (default)	Unused parameter
Cs Idle Enforcement	TRUE	Since every transfer is limited to 16 bits, this parameter does not have any significance to our usecase.
Cs Idle Timing	IDLE_TIME_3_POINT_5	Idle time must be minimum 300ns
Cs Inactive After Last Data	TRUE	Since every transfer is limited to 16 bits, this parameter does not have any significance to our usecase.
Cs Inter Data Delay	INTER_DATA_TIME_0_POINT_5	Minimum Inter data delay expected is 10ns
Cs Polarity	LOW	Chip select is active low for PwrSply/TmplMonr IC
Cs Selection	CS_VIA_GPIO
Cs Setup Time	SETUP_TIME_0_POINT_5	Minimum setup time of 30ns required
Data Shift Edge	LEADING
Enable Cs	TRUE*	If single chip is connected to the SPI bus, and if the CS pin of the peripheral chip is connected to ground, then this parameter can be made FALSE.
Fifo Time Out	0	FIFO mode is not planned to be used
Hw Unit	CSIG0	PwrSply/TmplMonr IC uses CSIG0
Input Clock Select	PCLK_DIVBY_4	Required baudrate is 1Mbps. This is achieved using 2 parameters m and k, where k is configured in ‘Baudrate Configuration’ and m is configured in ‘Input Clock Select’. Baudrate = Pclk/((2^m) * k * 2) Pclk = 80Mhz. To achieve 1Mbps, M = 2 K = 10
Interrupt Delay Mode	FALSE	No delay required in triggering the interrupts
Parity Selection	ODD_PARITY	PwrSply/TmplMonr requires Odd parity
Shift Clock Idle Level	HIGH	PwrSply/TmplMonr chip retains Clock high on idle state
Time Clk2 Cs	0 (default)	Unused parameter

As discussed before every channel is grouped under one Spi job. Table below contains Spi jobs configurations for PwrSply/TmplMonr which resides under the container ‘SpiJobs’.

Configuration Parameter	Value	Rationale	Remark

Container: Spi/SpiDrivers/SpiDriver/SpiJobs

Short Name	TmplMonrJob1		Job configuration for TmplMonr job 1
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	52	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	TmplMonrCh1
Channel Index	0	Specify the order of the channel inside the job.

Short Name	TmplMonrJob2		Job configuration for TmplMonr job 2
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	53	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	TmplMonrCh2
Channel Index	0	Specify the order of the channel inside the job.

Short Name	TmplMonrJob3		Job configuration for TmplMonr job 3
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	54	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	TmplMonrCh3
Channel Index	0	Specify the order of the channel inside the job.

Short Name	TmplMonrJob4		Job configuration for TmplMonr job 4
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	55	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	TmplMonrCh4
Channel Index	0	Specify the order of the channel inside the job.

Short Name	TmplMonrJob5		Job configuration for TmplMonr job 5
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	56	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	TmplMonrCh5
Channel Index	0	Specify the order of the channel inside the job.

Short Name	PwrSplyJob1		Job configuration for PwrSply job 1
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	57	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	PwrSplyCh1
Channel Index	0	Specify the order of the channel inside the job.

Short Name	PwrSplyJob2		Job configuration for PwrSply job 2
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	58	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	PwrSplyCh2
Channel Index	0	Specify the order of the channel inside the job.

Short Name	PwrSplyJob3		Job configuration for PwrSply job 3
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	59	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	PwrSplyCh3
Channel Index	0	Specify the order of the channel inside the job.

Short Name	PwrSplyJob4		Job configuration for PwrSply job 4
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	60	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	PwrSplyCh4
Channel Index	0	Specify the order of the channel inside the job.

Short Name	PwrSplyJob5		Job configuration for PwrSply job 5
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	61	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	PwrSplyCh5
Channel Index	0	Specify the order of the channel inside the job.

Short Name	PwrSplyJob6		Job configuration for PwrSply job 6
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	62	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	PwrSplyCh6
Channel Index	0	Specify the order of the channel inside the job.

Short Name	PwrSplyJob7		Job configuration for PwrSply job 7
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	63	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	PwrSplyCh7
Channel Index	0	Specify the order of the channel inside the job.

Short Name	PwrSplyJob8		Job configuration for PwrSply job 8
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	64	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	PwrSplyCh8
Channel Index	0	Specify the order of the channel inside the job.

Short Name	PwrSplyJob9		Job configuration for PwrSply job 9
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	65	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	PwrSplyCh9
Channel Index	0	Specify the order of the channel inside the job.

Short Name	PwrSplyJob10		Job configuration for PwrSply job 10
Device Assignment	PwrSplyTmplMonr
Hw Unit Synchronous	ASYNCHRONOUS	Level 1 support only Asynchronous job
Job End Notification	NULL
Job Id	66	Should be increased sequentially
Job Priority	3 (Default)
Port Pin Select	PORTGROUP_5_PORTPIN_9	Chip select line
Sub Container: .…/SpiChannel Lists
Short Name	SpiChannelList
Channel Assignment	PwrSplyCh10
Channel Index	0	Specify the order of the channel inside the job.

Note: The job ids used in the above table is for reference only and do not represent the actual job number in the implementation.

Table below contains Spi hardware unit selection and memory mode selection configuration for PwrSply/TmplMonr which resides under the container ‘SpiMemoryModes’.

Configuration Parameter	Value	Rationale	Remark

Container: Spi/SpiDrivers/SpiDriver/ SpiMemoryModes

Not Applicable for CSIG0

As discussed before every job is grouped under one Spi sequence. Table below contains Spi sequence configurations for PwrSply/TmplMonr which resides under the container ‘SpiSequences’.

Configuration Parameter	Value	Rationale	Remark

Container: Spi/SpiDrivers/SpiDriver/SpiSequences

Short Name	TmplMonrSeq1		Configuration for TmplMonr sequence 1
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	52	Should be increased sequentially
Job Assignment	TmplMonrJob1

Short Name	TmplMonrSeq2		Configuration for TmplMonr sequence 2
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	53	Should be increased sequentially
Job Assignment	TmplMonrJob2

Short Name	TmplMonrSeq3		Configuration for TmplMonr sequence 3
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	54	Should be increased sequentially
Job Assignment	TmplMonrJob3

Short Name	TmplMonrSeq4		Configuration for TmplMonr sequence 4
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	55	Should be increased sequentially
Job Assignment	TmplMonrJob4

Short Name	TmplMonrSeq5		Configuration for TmplMonr sequence 5
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	56	Should be increased sequentially
Job Assignment	TmplMonrJob5

Short Name	PwrSplySeq1		Configuration for PwrSply sequence 1
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	57	Should be increased sequentially
Job Assignment	PwrSplyJob1

Short Name	PwrSplySeq2		Configuration for PwrSply sequence 2
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	58	Should be increased sequentially
Job Assignment	PwrSplyJob2

Short Name	PwrSplySeq3		Configuration for PwrSply sequence 3
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	59	Should be increased sequentially
Job Assignment	PwrSplyJob3

Short Name	PwrSplySeq4		Configuration for PwrSply sequence 4
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	60	Should be increased sequentially
Job Assignment	PwrSplyJob4

Short Name	PwrSplySeq5		Configuration for PwrSply sequence 5
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	61	Should be increased sequentially
Job Assignment	PwrSplyJob5

Short Name	PwrSplySeq6		Configuration for PwrSply sequence 6
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	62	Should be increased sequentially
Job Assignment	PwrSplyJob6

Short Name	PwrSplySeq7		Configuration for PwrSply sequence 7
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	63	Should be increased sequentially
Job Assignment	PwrSplyJob7

Short Name	PwrSplySeq8		Configuration for PwrSply sequence 8
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	64	Should be increased sequentially
Job Assignment	PwrSplyJob8

Short Name	PwrSplySeq9		Configuration for PwrSply sequence 9
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	65	Should be increased sequentially
Job Assignment	PwrSplyJob9

Short Name	PwrSplySeq10		Configuration for PwrSply sequence 10
High Priority Hw Sequence	FALSE
Interruptible Sequence	FALSE	It would be recommended to keep all the sequences as Non-Interruptible
Seq End Notification	NULL
Seq Start Notification	NULL
Sequence Id	66	Should be increased sequentially
Job Assignment	PwrSplyJob10

Note: The sequence ids used in the above table is for reference only and do not represent the actual sequence implemented.

PORT Configurations (PwrSply/TmplMonr specific)

It is assumed that the CSIG0 SPI pins are configured properly in PORT configuration. The required pin settings are below:

CSIG0 Pin	Port Name	Pin Direction

Chip Select	P5_9	Out
MISO	P5_0	In
MOSI	P5_1	Out
SCK	P5_4	Out

OS Configurations (PwrSply/TmplMonr specific)

Following table contains interrupt configurations.

Configuration Parameter	Value	Rationale	Remark

Container: Os/OsIsrs

Short Name	SPI_CSIG0_TIC_CAT2_ISR		Configuration for ‘Communication Status Interrupt’
Isr Category	CATEGORY_2
Isr Enable Nesting	TRUE
Isr Accessing Application	NONE
Isr Resource Ref.	NONE
Sub Container: …../OsIsrUseResourceOccupations
	None
Sub Container: …../ OsIsrExceptionType
Short Name	EIINT
Isr Int channel	175
Isr Interrupt Priority	14	Example only. Actual value will be changed in the program
Isr Interrupt Stack Size	512	Example only. Actual value will be changed in the program
Sub Container: …../ OsIsrUseSpecialFunctionName
Short Name	FALSE

Short Name	SPI_CSIG0_TIRE_CAT2_ISR		Configuration for ‘Communication Error Interrupt’
Isr Category	CATEGORY_2
Isr Enable Nesting	TRUE
Isr Accessing Application	NONE
Isr Resource Ref.	NONE
Sub Container: …../OsIsrUseResourceOccupations
	None
Sub Container: …../ OsIsrExceptionType
Short Name	EIINT
Isr Int channel	174
Isr Interrupt Priority	14	Example only. Actual value will be changed in the program
Isr Interrupt Stack Size	512	Example only. Actual value will be changed in the program
Sub Container: …../ OsIsrUseSpecialFunctionName
Short Name	FALSE

Short Name	SPI_CSIG0_TIR_CAT2_ISR		Configuration for ‘Receive Status Interrupt’
Isr Category	CATEGORY_2
Isr Enable Nesting	TRUE
Isr Accessing Application	NONE
Isr Resource Ref.	NONE
Sub Container: …../OsIsrUseResourceOccupations
	None
Sub Container: …../ OsIsrExceptionType
Short Name	EIINT
Isr Int channel	176
Isr Interrupt Priority	14	Example only. Actual value will be changed in the program
Isr Interrupt Stack Size	512	Example only. Actual value will be changed in the program
Sub Container: …../ OsIsrUseSpecialFunctionName
Short Name	FALSE

Important Note: Keep all of the interrupts configured above under a trusted application. Because they require to run in Supervisory/Privilege mode. Also add the SPI driver API

Spi_AsyncTransmit() as a trusted function under a trusted application.

API Descriptions

Following table describes available APIs (Client/Server functions) per current configurations for PwrSply/TmplMonr.

API Name	Functionality	Syntax	Argument	Return

Spi_Init	Initializes the SPI module. Shall be called by EcuM or BswM	void Spi_Init( const Spi_ConfigType* ConfigPtr)	SpiDriver. This is a pointer constant points to the Spi config structure.	None
Spi_WriteIB	Function to specify the data which has to be transmitted over the SPI bus intended to a particular register.	Std_ReturnType Spi_WriteIB( Spi_ChannelType Channel, const Spi_DataType* DataBufferPtr )	Channel = (Channel ID for the specific register) DataBufferPtr = (Pointer to the 16 bit data buffer which need to transmit. Note: the function takes the lower significant 15 bits of data and calculate the odd parity and append it as a LSB with the 15 bits data)	E_OK: write command has been accepted. E_NOT_OK: write command has not been accepted.
Call_Spi_AsyncTransmit	Function to initiate the SPI transmission intended for a particular register.	Std_ReturnType Call_Spi_AsyncTransmit( Spi_SequenceType Sequence )	Sequence = (Sequence ID for the specific register)	E_OK: Transmit command has been accepted. E_NOT_OK: Transmit command has not been accepted.
Spi_ReadIB	Function to get the data that has been received from the SPI bus during a transmission intended for a register.	Std_ReturnType Spi_ReadIB( Spi_ChannelType Channel, Spi_DataType* DataBufferPointer )	Channel = (Channel ID for the specific register) DataBufferPtr = (Pointer to the 16 bit data buffer where the received SPI data supposed to store. Note: the function takes off the parity bits and gives the rest 15 bits of data in 16 bit format)	E_OK: Read command has been accepted. E_NOT_OK: Read command has not been accepted.
Spi_GetSequenceResult	Function to get the result of the last transmission intended for a particular register.	Spi_SeqResultType Spi_GetSequenceResult( Spi_SequenceType Sequence )	Sequence: Sequence ID for the register.	SPI_SEQ_OK. SPI_SEQ_PENDING. SPI_SEQ_FAILED. SPI_SEQ_CANCELLED

Note:

For both server and client the API name will be same. The use method of server/client functions are described in “CM600A_CSIG0CfgAndUse_DataDict.m” file.

Use the API Call_Spi_AsyncTransmit () if it is being called from a software component which does not reside under a trusted application.

Sub-Function: Next Sub-function

None

Timing / Execution Constraints

Rationale / Comments

Per RENESAS user manual Spi_Init() should be placed before Port_Init() in the ECU startup sequence.

The order of API function calls when transmit any SPI message:

Spi_WriteIB()

Call_Spi_AsyncTransmit()

The order of API function calls to receive or read any SPI message when the transmission is finished:

Spi_GetSequenceResult() ---🡪 Optional. Use this if want to verify whether the transmission is done or

not before reading the buffer.

Spi_ReadIB()

Note: In a 2ms loop use separate SequenceID for transmitting each of the message. For example if we have n different message to transmit in a 2ms loop then use n different SequenceID for each of the transmission. The SequenceID can be reused once the transmission is done, i.e in the next 2ms loop same SequenceID can be reused.

Rates and State Execution

None.

Serial Communications Interfaces

None.

Additional Information

None.

Revision Record & Change Approval

Rev	Date	Change Control #	Drw	Change Description
1.0.0	07-01-2015	CR ID: EA4#1027		Initial version

2 - A4412 Datasheet 2015_05_20

Microsoft Word - A4412 Datasheet 2015_05_20.docx

3 - A4412 Datasheet 2015_05_20_ind

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4 - A4412 Datasheet 2015_05_20s

A4412

Buck or Buck/Boost Pre-Regulator with a Synchronous Buck,
5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI
FEATURES AND BENEFITS
DESCRIPTION
  A2-SILTM Product – device features for
The A4412 is power maanagement IC that uses a buck or
safety critical systems
buck/boost pre-regulator to efficiently convert automotive battery
 Automotive AEC-Q100 qualified
voltages into a tightly regulated intermediate voltage complete with
 Wide input voltage range, 3.8V
control, diagnostics and protections. The output of the pre-
IN to 40VIN operating range,
50V
regulator supplies a 5V/100mA protected linear regulator, a
IN maximum
 Buck or buck/boost pre-regulator (VREG)
3.3V/90m
mA linear regulator, a 5V/200mA linear regulator, a
 Adjustable 1.3V to 3.3V, 400mA synchronous buck.
5V/55mA linear regulator, a 5V/30mA linear regulator and an
 Four internal linear regulators with fold back short circuit
adjustable 400mA synchronous buck regulator. Designed to
protection, 3.3V (3V3) and three 5V (V5CAN, V5A and V5B)
supply CAN transceiver,, sensor and microprocessor power
 One internal 5V linear regulator (V5P) with fold back short
supplies in high temperature environments the A4412 is ideal for
circcuit and short-to-battery protection
under hood applications.
 Power-on reset signal indicating a fault on the synchronous

buck, 3V3 or V5A regulator outputs (NPOR)
Enable inputs to the A4412 include a logic level (ENB) and a high-

voltage (ENBAT). The A4412 also provides flexibility with disable
Window watchdog timer with fail safe features
function of the individual 5V rails through a serial peripheral
 Dual band gaps for increased safety coverage and fault
interface (SPI).
detection, BGVREF, BGFAULT

 Control and diagnostic reporting through a serial peripheral
Diagnosticc outputs from the A4412 include a power-on-reset
interface (SPI)
output (NP
POR), an ENBAT status output, and a fault flag output to
 Logic enable input (ENB) for microprocessor control
alert the microprocessor that a fault has occurred. The
 Igniition enable input (ENBAT) with status indicator output
microprocessor can read fault status through SPI. Dual band gaps,
 Frequency dithering and controlled slew rate helps reduce
one for regulation and oone for fault checking, improve safety
EMI/EMC
coverage and fault detection of the A4412.
 OV
and UV protection for all output rails

 Pin-to-pin and pin-to-ground tolerant at every pin
The A4412 contains a Window Watchdog timer with a detect

period of 22ms. The watchdog timer is activated once it receives
APPLICATIONS
valid 2mssec pulses from the processor. The watchdog can be put
 EPS modules
  CAN power supplies
into flash mode or be resset via secure SPI commands.
 Automotive power trains
  High temperature applications

Protection features include under and over voltage on all output
PACKAGE (NOT TO SCALE) 38-pin eTSSOP (LV)
rails. In case of a shorted output, all linear regulators feature fold
back over current protection. In addition, the V5P output is
protected from a short-to-battery event. Both switching regulators
include pulse-by-pulse current limit, hiccup mode short circuit
protection, LX short circuit protection, missing asynchronous diode

protection (VREG only) and thermal shutdown.

The A4412 is supplied in a low profile (1.2mm maximum height)
38-lead eTSSOP packagge (suffix “LV”) with exposed power pad.
3.3V Linear
5.0V Linear
5.0V Linear
Enable and
5.35V
Adjustable
Charge
Regulator with  Regulator  with  Regulator with
Start Up
(VREG)
1.305V to 3.3V
Pump
Foldback
Foldback
Foldback
Timing
Buck-Boost
Sync. Buck
Pre-regulator
Regulator
Protection
Protection
Protection
5.0V Linear
5.0V Protected Linear
Serial
OV/UV Detect
Clock Edge
Dual
Regulator with
Regulator with
TSD
Interface
with BIST
Window
Bandgaps
Foldback
Foldback and Short to
(SPI)
& NPOR
Watchdog
Protection
VBAT Protection

A4412 SIMPLIFIED BLOCK DIAGRAM

Preliminary Data Sheet
May 20th, 2015
Subject to Change Without Notice

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

SELECTION GUIDE
Part Number
Temp. Range
Package
Packing
Lead Frame
A4412KLVTR-T
–40 to 150°C 38-pin eTSSOP w/ thermal pad
TBD pieces per 7-in reel
100% Matte Tin
*Contact Allegro for additional packing options

ABSOLUTE MAXIMUM RATINGS*
Characteristic
Symbol
Notes
Rating
Units
VIN
VVIN

−0.3 to 50
V
With current limiting resistor**
−13 to 50
VENBAT
V
ENBAT

−0.3 to 8
IENBAT

±75
mA

−0.3 to VVIN+0.3
LX1

t < 250ns
−1.5
V
t < 50ns
VVIN+3V
VCP, CP1, CP2

−0.3 to 60
V
−1.0 to 50*
V5P
VV5P

V
*Independent of VVIN
All other pins

−0.3 to 7
V
Ambient Temperature
TA Limited by power dissipation
−40 to 140
ºC
Junction Temperature
TJ

−40 to 165
ºC
Storage Temperature Range
TS

−40 to 150
ºC
* Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical
Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for exxtended periods may affect device
reliability

** The higher ENBAT ratings (-13V and 50V) are measured at node “A” in the following circuit configuration:

Node
“A
A”
≥450Ω
ENBAT
VENBAT
4412
GND

THERMAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions*
Value
Units
Junction to ambient thermal
Rθ
eTSSOP-38 (LV) package
30
ºC/W
resistance
JA
*Additional thermal information available on the Allegro website

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
2
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

FUNCTIONAL BLOCK DIAGRAM
P
1
2
Bias LDO
VC
CP
CP
SU/SD
VCP
BUCK-BOOST PRE-REGULATOR
VIN
LDO
VIN
VCC
VIN
BG
I
VRE F
SLE W
Charge
VIN
VCP
OK
VREG
Pump
CLK1MHz
VINOK
B
BG
UCK-BOOST
BG
VCP OV/UV
VRE F
BG
FA ULT
VCP OV
Control
FA ULT
Detect
VREG ON
VCC
LDO
VDD
VCP UV
LX1
MPOR
COMP1 & SS1 Reset
Charge Pump
LX1
Oscillator
VCP UV
STOP PWM
LG
BG1_UV
CLK @ fosc
1
COMP1
COMP1
VDD
VDD
BG1
Oscillator
CLK @ fosc
FB
SS
BG
and
VRE F
CLK
Clocks
1MHz
BG
VSS1RST
SS1
DITH_DIS
FA ULT
WDOSC
BG2
BG2_UV
VREG
VREG
BUCK REGULATOR
ENABLE and START UP TIMING
VREG
ENBAT
DE-
FALLING
GLITCH
DELAY
650KΩ
SU/SD
LX2
tdFILT
tdLD O,OFF
VSS2RST
↑ 3.3VTYP
ENBATS
ON/OFF
↓ 2.6V
CLK @ fosc
TY P
SYNC.
BUCK
BUCK_ON
Controller
OV
ENB_EN
BG
(w/ Hiccup Mode)
VRE F
FB
MPOR
MPOR
COMP2 & SS2 Res
C
set
OMP2
ENB
BUCK_ON
Regulator
3V3_ON
SS2
60KΩ
SU/SD
Sequencer
LDOs_ON
V5P Regulator
TSD
TSD
OV/UV Detect
V5PDISC
Short to
VCORE_OK
FOLDBACK
VBAT
VC
CP
Protection
OV/UV
TSD
MASTER IC POR
DETECT &
VREG
NPOR
(MPOR)
DELAYS
DE-
3V3
BG
5V Linear
VRE F
V5P
GLITCH
FB
BG1_UV
V5P_D
Regula
DIS
tor
td
BG2_UV
FI LT
V5A
VCC_UV LDOs_ON
RST
ON/OFF
VCP_UV
MPOR
CLK1MHz
*VREG_OV
V5A Regulator
MASTER
REF
BGFAULT
*VCP_OV
MPOR
IC POR
FOLDBACK
VCC
*D1
VCP
(MPOR)
MISS ING
VCP
*FB_OV
DE-
VREG
FFn
VREG
*ILIM,LX2
GLITCH
BG
5V Linear
V5B
VSS1
VRE F
V5A
td
SS OK
RST
FI LT
Regulator
V5CAN
VSS2
V5A_DIS
RST
V5P
TSD
BUCK_ON
DIAG
*
V5P
indicates a latched fault
V5B Regulator
DIS C
*D1MISSING
VDD
FOLDBACK
*ILIM,LX1
VCP
WD_F
SPI
VREG
VREG_UV
5V Linear
V5A_DIS
BGVREF
V5A_UV
V5B
Regulator
V5B_DIS
V5B_DIS
V5B_UV
WINDOW WATCHDOG
V5P_DIS
LDOs_ON
V5P_UV
V5CAN_DIS
VDD
V5CAN_UV
DITH_DIS
V5CAN Regulator
3V3_UV
WD_STATE
MAX_TIMER
FB_UV
FOLDBACK
MAX_TIMER
MIN_TIMER
VCP
MIN_TIMER
VALID_COUNT
VREG_OV
WD_IN
WD Monitor
VALID_COUNT
WD_FLASH
V5A_OV
VREG
5V Linear
WD_FLASH
WD_RESTART
V5B_OV
BGVREF
V5CAN
V5P_OV
Regulator
nERROR
WD_RESTART
WD_F
V5CAN_DIS
V5CAN_OV
LDOs_ON
V5CAN_DIS
VCC_UV
3V3_OV
WD
3V3 Regulator
OS C
VCC_OV
FB_OV
FOLDBACK
POE
ENB_EN
VCP_UV
VREG_OCP
VCP
WD_F
*VCP_OV
V5A_OCP
*D1MISSING
VREG
VCORE_OK
V5B_OCP
*ILIM,LX1
V5P_OCP
BG
3.3V Linear
VRE F
*I
3V3
LIM,LX2
V5CAN_OCP
Regulator
3V3_ON
STRn
3V3_OCP
SDI
FB_OCP
SDO
TSD
SCK
ENBATS
D
D
ND
N
N
DG
AG
PG

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
3
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

TYPICAL SCHEMATIC
Buck-Boost Mode
Using a Series Diode for Reverse Battery Protection (DIN)

1.0μF
0.22μF
VBAT
P
1
2
Din
VC
CP
CP
D2
SS3P4
VIN
A4412
10μH
SS3P4
5.35VTYP
VIN
LX1
2x 4.7μF
LX1
D1
100μF
50V
0.1μF
SS3P4
50V/250mΩ
10μF
10μF
1210
0603
Q1
LG
FDS8449
or Si4446DY
2k
VCC
CVCC
COMP1
VREG
1μF
10pF
SS1
8.25k
0.47μF
CSS1
2.2nF
10μH
KEY_SW
LX2
1.3V
180mA
3V3
10μF
OV
10k
FB
NPOR
COMP2
NPOR
SS2
10pF
3V3
2.74k
CSS2
10k
4.7nF
FAULT
FFn
5V
V5P
PROTECTED
3V3
3V3
D3
100mA
90mA
MSS1P5
2.2μF
2.2μF
V5A
V5A
55mA
3.3k
V_IGN
2.2μF
ENBAT
DIAG
V5B
V5B
30mA
µP
ENABLE
2.2μF
ENB
V5
V5
CAN
CAN
200mA
STRn
2.2μF
VCC
SCK
10k
SDI
ENBATS
ENBAT
STATUS
SDO
POE
WD_IN
A4412
Buck set up for 3.3V output
nERROR
22μH
LX2
3.3V
D
D
100mA
N
ND
N
15.4k
15.4k
10μF
AG
DG
PG
OV
FB
COMP2
SS2
10pF
10k
10k
5.11k
CSS2
4.7nF

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
4
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

TYPICAL SCHEMATIC

Modifications for Buck Only Mode

1.0μF
0.22μF
VBAT
P
1
2
Din
VC
CP
CP
SS3P4
VIN
A4412
5.35VTYP
VIN
LX1
2x 4.7μF
LX1
D1
100μF
50V
0.1μF
SS3P4
50V/250mΩ
1210
0603
LG
VCC
CVCC
COMP1
1μF
VREG
C
SS1
P1
R
0.47μF
Z1
CSS1
CZ1

Using a PMOS FET for Reverse Battery Protection Instead of a Seeries Schottky Diode (DIN)
Body Diode
VBATT
MODULE

Using an NMOS FET for Reverse Battery Protection Instead of a Series Schotttky Diode (DIN)
VBATT
MODULE
Body Diode

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
5
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

PIN-OUT DIAGRAM:
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Pin No.
Name
Description
1
VCP
Charge pump reservoir capacitor
2,3
VIN
Input voltage pins
4
AGND
Analog ground pin
5
ENBAT
Ignition enable input from the key/switch via a series resistor
6
VCC
Internal voltage regulator bypass capacitor pin
7
ENBATS
Open drain ignition status output of ENBAT
8
SS1
Soft start programming pin for the bucck/boost pre-regulator
9
COMP1
Error amplifier compensation network pin for the buck/boost pre-regulator
Diagnostic pin to aid de-bug. A pulse train whose frequency depends on the fault that
10
DIAG
occurred is sent to this pin. See fault table.
11
SDI
SPI data input from the microcontrollerr
12
SDO
SPI data output to the microcontroller
13
STRn
Chip select input from the microcontrooller
14
SCK
Clock input from the microcontroller
15
NPOR
Active LOW, open-drain regulator fault detection output
16
WD_IN
Watchdog pulse train input from a miccro-controller or DSP
17
ENB
Logic enable input from a micro-controller or DSP
18
DGND
Digital ground pin
19
POE
Gate drive enable signal, goes low if a watchdog fault is detected or nERROR is llow
20
nERROR
System fault input. This fault is ANDed with the watch dog fault to create the POE signal
21
FFn
Active low fault flag, alerts the microprocessor of a fault within the regulator
22
SS2
Soft start programming pin for the adjustable synchronous buck regulator
23
FB
Feedback pin with 1.305V reference for synchronouus buck regulator
24
OV
Input to synchronous over voltage sense circuit
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
6
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

Pin No.
Name
Description
25
COMP2
Error amplifier compensation network pin for the adjustable synchronous buck regulator
26
V5P
5V protected regulator output
27
V5A
A 5V regulator output
28
V5B
A 5V regulator output
29
3V3
A 3.3V regulator output
30
5VCAN
A 5V regulator output for communications
31
VREG
Output of the pre-regulator and input too the linear regulators and synchronous buck
32
LX2
Switching node for the adjustable synchronous buck regulator
33
LG
Boost gate drive output for the buck/boost pre-regulator
34
PGND
Power ground for the adjustable synchronous regulator / gate driver
35,36
LX1
Switching node for the buck/boost pre-regulator
37
CP1
Charge pump capacitor connection
38
CP2
Charge pump capacitor connection

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
7
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)≤VIN≤40V, −40ºC≤TA=TJ≤150ºC

GENERAL SPECIFICATIONS
Characteristic
Symbol
Test Conditions
Min
Typ Max Units
General Specifications
After VVIN > VINSTART, and VENB > 2.0V
3.8
13.5 40
or VENBAT > 3.5V, Buck-Boost Mode
Operating Input Voltage
VVIN
V
After VVIN > VINSTART, and VENB > 2.0V
5.5
13.5 40
or VENBAT > 3.5V, Buck Mode
VIN UVLO START Voltage
VINSTART
VVIN rising
4.55
4.8 5.05
V
VIN UVLO STOP Voltage
V
ing, V
.8V or
VIN
VIN falli
ENBAT ≥ 3
STOP
3.25
3.5 3.75
V
VENB ≥ 2.0V, VVREG = 5.2V
VIN UVLO Hysteresis
VINHYS VINSTART ‒ VINSTOP
—
1.3
—
V
I
VVIN = 13.5V, VENBAT ≥ 3.8V or
Q
—
13
— mA
VENB ≥ 2.0V, VVREG = 5.6V (no PWM)
Supply Quiescent Current (1)
I
3.5V, VENBAT ≤ 2.2V and
Q,SLEEP
VVIN = 1
—
— 10 µA
VENB ≤ 0.8V
PWM Switching Frequency and Dithering
Switching Frequency
fOSC
Dithering disabled 3.8V(4)≤VIN≤18V
2.0
2.2 2.4 MHz
Frequency Dithering
∆fOSC
As a percent of fOSC
—
±10
— %
VINDS,ON
VIN Rising
8.5
9.0 9.55 V
Dither/Slew START Threshold

VIN Falling

17
V
VINDS,OFF
VIN Falling
7.8
8.3 8.88 V
Dither/Slew STOP Threshold

VIN Rising

18
V
VIN Dithering/Sle
ew Hysteresis

—
700
— mV
Charge Pump (VCP)
VVCP – VVIN, VVIN ≥ 5.5V, Buck Mode
4.1
6.6
— V
Output Voltage
VVCP
VVCP – VVIN, VVIN = 3.8V, VREG = 5.35
Buck Boost Mode
4.1
6.6
— V
Switching Frequency
fSW,CP

—
65
— kHz
VC
CC Pin Voltage
Output Voltage
VVCC
VVREG = 5.35V
—
4.65
— V
System Clock
Internal Clock Frequency
fSYS

—
1.00
— MHz
Internal Clock Tolerance
fSYS,TOL

-4
—
4 %
Thermal Protection
Thermal Shutdown Threshold (2)
TTSD
TJ rising
165
—
— ºC
Thermal Shutdown Hysteresis (2)
THYS

—
15
— ºC
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
8
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)≤VIN≤40V, −40ºC≤TA=TJ≤150ºC
BUCK AND BUCK-BOOST PRE-REGULATOR SPECIFICATIONS
Characteristic
Symbol
Test Conditions
Min
Typ Max Units
Output Voltage Specifications
Buck Output Voltage – Regulating VVREG
VVIN=13.5V, ENB=1, 00.1A<IVREG<1.2A
5.25
5.35 5.45 V
Pulse Width Modulation (PWM)
PWM Ramp Offset
PWM1OFFS VCOMP1 for 0% duty cycle
—
400
— mV
LX1 Rising Slew Rate Control (2) LX1RISE
VVIN = 13.5V, 10% to 90%, IVREG=1A
—
1.4
— V/ns
LX1 Falling Slew Rate (2)
LX1FALL
VVIN = 13.5V, 90% to 10%, IVREG=1A
—
1.5
— V/ns
Buck Minimum ON-time
tON,MIN,BUCK

—
85 160 ns
Buck Maximum Duty Cycle
DMAX,BUCK
VVIN < 7.8V
—
100
— %
Boost Minimum OFF-time
tON,MIN,BST

—
100 130 ns
Boost Maximum Duty Cycle
DMAX,BST
After VVIN>VINSTART, VVIN=3.8V
—
65
— %
COMP1 to LX1 Current Gain
gmPOWER1

—
4.57
— A/V
Slope Compensation (2)
SE1

1.1
1.62
2.115
A/µs
Internal MOSFET
VVIN = 13.5V, TJ = ‒40°C (2), IDS = 0.1A
—
60 75
mΩ
MOSFET On Resistance
RDSon
VVIN = 13.5V, TJ = 25°C (3), IDS = 0.1A —
85 1000
mΩ
VVIN = 13.5V, TJ = 1500°C, IDS = 0.1A
—
160 1990
mΩ
VENBAT ≤ 2.2V , VENB ≤ 00.8V, VLX1 = 0V,
—
— 10 µA
VVIN = 16V, −40°C<TJ<85°C (3)
MOSFET Leakage
IFET,LKG
VENBAT ≤ 2.2V, VENB ≤ 0.8V, VLX1 = 0V,
—
50 150 µA
VVIN = 16V, −40°C<TJ<150°C
Error Amplifier
Open Loop Voltage Gain
AVOL1
—
60
— dB
VSS1 = 750mV
520
720 920
Transconductance
gmEA1
µA/V
VSS1 = 500mV
260
360 4660
Output Current
IEA1

—
±75
— µA
VIN < 8.5V
1.2
1.52 2.1
Maximum Output Voltage
EA1VO(max)
V
VIN > 9.5V
0.9
1.22 1.7
Minimum Output Voltage
EA1VO(min)

—
— 300 mV
HICCUP1 = 1 or FAULT1 = 1 or
COMP1 Pull Down Resistance
RCOMP1
VENBAT ≤ 2.2V and VENB ≤ 0.8V,
—
1
—
kΩ
latched until VSS1 < VSS1RST
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
9
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)≤VIN≤40V, −40ºC≤TA=TJ≤150ºC
BUCK AND BUCK-BOOST PRE-REGULATOR SPECIFICATIONS (cont’d)
Characteristic
Symbol
Test Conditions
Min
Typ Max Units
Boost MOSFET (LG) Gate Driver
LG High Output Voltage
VLG,ON
VVIN=6V, VVREG=5.35V
4.6
— 5.5 V
LG Low Output Voltage
VLG,OFF
VVIN=13.5V, VVREG=5.35V
—
0.2 0.4 V
LG Source Current (1)
ILG,ON
VVIN=6V, VVREG=5.35V, VLG=1V
—
−300
— mA
LG Sink Current (1)
ILG,OFF
VVIN=13.5V, VVREG=5.35V, VLG=1V
—
150
— mA
Soft Start
SS1 Offset Voltage
VSS1OFFS
VSS1 rising due to ISS1SU
—
400
— mV
VSS1 falling due to HICCUP1 = 1 or
SS1 Fault/Hiccup Reset Voltage
VSS1RST
FAULT1 = 1 or VENBAT ≤ 2.2V and
140
200 275 mV
VENB ≤ 0.8V
SS1 Startup (Source) Current
ISS1SU
VSS1 = 1V, HICCUP1 = FAULT1 = 0
−15
−20
−25 µA
SS1 Hiccup (Sink) Current
ISS1HIC
VSS1 = 0.5V, HICCUP11 = 1
7.5
10 12.5 µA
SS1 Delay Time
tSS1,DLY
CSS1 = 22nF
—
440
— µs
SS1 Ramp Time
tSS1
CSS1 = 22nF
—
880
— µs
SS1 Pull Down Resistance
FAULT1=1 or V
≤ 2.2V
RPD
ENBAT
and
SS1
—
3
—
kΩ
VENB ≤ 0.8V, latched unntil VSS1<VSS1RST
0V ≤ VVREG < 1.34V typical and
—
f
— —
V
OSC/8
COMP1 = EA1VO(max)
0V ≤ VVREG < 1.34V typical and
—
f
— —
V
OSC/4
COMP1 < EA1VO(max)
SS1 PWM Frequency Foldback
fSW1,SS
1.34V ≤ VVREG < 2.68V typical and
—
f
— —
V
OSC/2
COMP1 < EA1VO(max)
VVREG ≥ 2.68V typical and
—
f
— —
V
OSC
COMP1 < EA1VO(max)
Hiccup Mode
Hiccup1 OCP Enable Threshold
VHIC1,EN
VSS1 rising
—
2.3
—
V
VSS1 > VHIC1,EN, VVREG < 1.95VTY,
—
30
—
PWM
VCOMP = EA1VO(max)
cycles
Hiccup1 OCP PWM Counts
tHIC1,OCP
VSS1 > VHIC1,EN, VVREG > 1.95VTYP,
—
120
—
PWM
VCOMP = EA1VO(max)
cycles
Current Protections
VIN < 8.5V
3.83
4.2
4.77
Pulse by pulse current limit
ILIM1,ton(min)
A
VIN > 9.5V
2.49
2.8
3.11
LX1 Short Circuit Current Limit
ILIM,LX1 Latched fault after 2nd detection
5.3
7.1
— A
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
10
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)≤VIN≤40V, −40ºC≤TA=TJ≤150ºC
ADJUSTABLE SYNCHRONOUS BUCK REGULATOR
Characteristic
Symbol
Test Conditions
Min
Typ
Max Units
Missing Asynchronous Diode (D1) Protection
Detection Level
VD,OPEN

−1.72
−1.4
−1.0
V
Time Filtering (2)
tD,OPEN

50
—
250
ns
Feedback Reference Voltage
Reference Voltage
VFB

1.28
1.305 1.33
V
Pulse Width Modulation (PWM)
PWM Ramp Offset
PWM2OFF
VCOMP2 for 0% duty cycle
−
440
− mV
High-Side MOSFET Minimum
t

−
65 105 ns
ON-Time
ON(MIN)
High-Side MOSFET Minimum
Does not include total gate driver
t
−
100 130 ns
OFF-Time
OFF(MIN)
non-overlap time, tNO
Gate Driver Non-Overlap Time (2)
tNO

−
15
− ns
COMP2 to LX2 Current gain
gmPOWER2

−
1.0
− A/V
Slope Compensation (2)
SE2

0.19
0.26 0.33 A/μs
Internal MOSFETs
(3)
High-Side MOSFET
TA = 25°C  , IDS = 100mA
−
450
540
mΩ
RDS
ON Resistance
ON (HS)
IDS = 100mA
−
−
780 mΩ
LX2 Node Rise/Fall Time (2)
t R/F,LX2
VVREG = 5.5V
−
12
− ns
VENBAT ≤ 2.2V, VENB ≤ 0.8V, VLX2 = 0V,
−
−
2
μA
VVREG = 5.5V, ‒40˚C < TJ < 85˚C (3)
High-Side MOSFET Leakage (1)
IDSS (HS)
VENBAT ≤ 2.2V, VENB ≤ 0.8V, VLX2=0V,
−
3
15
μA
VVREG = 5.5V, −40°C < TJ < 150°C
(3)
Low-Side MOSFET
TA = 25°C  , IDS = 100mA
−
165 195 mΩ
RDS
ON Resistance
ON (LS)
IDS = 100mA
−
−
280 mΩ
VENBAT ≤ 2.2V, VENB ≤ 0.8V,
−
−
1
μA
VLX2=5.5V,  ‒40˚C < TJ <  85˚C (3)
Low-Side MOSFET Leakage (1)
IDSS (LS)
VENBAT≤2.2V and VENB≤0.8V,
−
4
10
μA
VLX2=5.5V, −40°C <TJ < 150°C
Current Protections
ILIM2,5%
Duty Cycle = 5%
720
840
960
mA
Pulse-by-Pulse Current Limit
ILIM2,90%
Duty Cycle = 90%
480
640
800
mA
V
low for more than 60ns,
LX2 Short Circuit Protection
V
LX2 stuck
LIM,LX2
— V
— V
Hiccup mode after 2x detection
VREG - 1.2V
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
11
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)≤VIN≤40V, −40ºC≤TA=TJ≤150ºC
ADJUSTABLE SYNCHRONOUS BUCK REGULATOR (cont’d)
Characteristic
Symbol Test
Conditions
Min
Typ Max Units
Error Amplifier
V
= 0.8V,
Feeedback Input Bias Current (1)
I
COMP2
FB,ADJ
–
–150 –350 nA
VFB,ADJ regulated so thaat ICOMP2 = 0A
Open Loop Voltage Gain (2)
AVOL2
−
60
− dB
ICOMP2 = 0μA, VSS2 > 500mV
520
720 920
μA/V
Transconductance
gmEA2
0V < VSS2 < 500mV
–
250
–
μA/V
Source & Sink Current
IEA2
VCOMP2 = 1.5V
−
±50
−
μA
Maximum Output Voltage
EA2VO(max)

1.04
1.3 1.56 V
Minimum Output Voltage
EA2VO(min)

–
– 150 mV
HICCUP2 = 1 or FAULT2 = 1 or
COMP2 Pull Down Resistance
RCOMP2
VENBAT ≤ 2.2V and VENB ≤ 0.8V,
−
1.3
−
kΩ
latched until VSS2 < VSS2RST
Soft Start
SS2 Offset Voltage
VSS2OFFS
VSS2 rising due to ISS2SU
120
200 2770 mV
VSS2 falling due to HICCUP2 = 1 or
SS2 Fault/Hiccup Reset Voltage VSS2RST
FAULT2 = 1 or VENBAT ≤ 2.2V
−
100 120 mV
and VENB ≤ 0.8V
SS2 Startup (Source) Current
ISS2SU
VSS2 = 1V, HICCUP2 = FAULT2 = 0
−15
–20
−25
μA
SS2 Hiccup (Sink) Current
ISS2HIC
VSS2 = 0.5V, HICCUP2 = 1
5
10 15
μA
SS2 to Synchronous Buck Output
t
10nF
−
100
−
μs
Delay Time
SS2,DLY
CSS2 = 1
Synchronous Buck Soft Start
t
C
10nF
−
400
−
μs
Ramp Time
SS2
SS2 = 1
FAULT2=1 or V
2.2V
SS2 Pull Down Resistance
RPD
ENBAT≤2
and
SS2
−
2
−
kΩ
VENB≤0.8V, latched until VSS2<VSS2RST
VFB < 470mV typical
−
fOSC/4
−
−
SS2 PWM Frequency Foldback
fSW2,SS
470mV < VFB < 780mV typical

fOSC/2

VFB > 780mV typical
−
fOSC
−
−
Hiccup Mode
Hiccup2 OCP Enable Threshold
VHIC2,EN
VSS2 rising
—
1.2
—
V
VSS2>VHIC2,EN, VFB<470mVTYP
—
30
—
PWM
cycles
Hiccup2 OCP Counts
tHIC2,OCP
VSS2>VHIC2,EN, VFB>470mVTYP
—
120
—
PWM
cycles
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
12
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)≤VIN≤40V, −40ºC≤TA=TJ≤150ºC

LINEAR REGULATOR SPECIFICATIONS
Characteristic
Symbol
Test Conditions
Min
Typ
Max Units
V55CAN, V5A, V5B and V5P Linear Regulators
V5CAN Accuracy & Load Regulation VV5CAN 10mA
< IV5CAN < 200mA, VVREG = 5.25V 4.9  5.0
5.1 V
V5CAN Output Capacitance Range
COUT,V5CAN

1.0
—
15 µF
(2)
V5A Accuracy & Load Regulation VV5A 5mA
< IV5A < 55mA, VVREG = 5.25V
4.9
5.0
5.1 V
V5A Output Capacitance Range (2)
COUT,V5A

1.0
—
15 µF
V5B Accuracy & Load Regulation VV5B 5mA
< IV5B < 30mA, VVREG = 5.25V
4.9
5.0
5.1 V
V5B Output Capacitance Range (2)
COUT,V5B

1.0
—
15 µF
V5P Accuracy & Load Regulation VV5P 5mA
< IV5P < 100mA, VVREG = 5.25V 4.9
5.0
5.1 V
V5P Output Capacitance Range (2)
COUT,V5P

1.0
—
15 µF
V55CAN Over Current Protection
V5CAN Current Limit (1)
V5CANILIM
VV5CAN = 5V
−220
−310
— mA
V5CAN Foldback Current (1)
V5CANIFBK  VV5CAN = 0V
−40
−80
−120 mA
V55A Over Current Protection
V5A Current Limit (1)
V5AILIM
VV5A = 5V
−60
−100
— mA
V5A Foldback Current (1)
V5AIFBK
VV5A = 0V
−15
−30
−45 mA
V55B Over Current Protection
V5B Current Limit (1)
V5BILIM
VV5B = 5V
−40
−90
— mA
V5B Foldback Current (1)
V5BIFBK
VV5B = 0V
−5
−20
−35 mA
V55P Over Current Protection
V5P Current Limit (1)
V5PILIM
VV5P = 5V
−110
−155
— mA
V5P Foldback Current (1)
V5PIFBK
VV5P = 0V
−20
−40
−60 mA
V55A, V5B and V5P Startup Timing
V5CAN Startup Time (2)
t
N ≤ 2.9µF, Load = 200Ω±5%
V5CAN,START
CV5CAN
—
0.4
1.0 ms
(25mA)
V5A Startup Time (2)
tV5A,START
CV5A ≤ 2.9µF, Load = 200Ω±5% (25mA) —  0.6
1.0 ms
V5B Startup Time (2)
tV5B,START
CV5B ≤ 2.9µF, Load = 333Ω±5% (15mA) —  0.8
1.0 ms
V5P Startup Time (2)
tV5C,START
CV5P ≤ 2.9µF, Load = 100Ω±5% (50mA) —  0.5
1.0 ms
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
13
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)≤VIN≤40V, −40ºC≤TA=TJ≤150ºC

LINEAR REGULATOR SPECIFICATIONS (cont’d)
Characteristic
Symbol
Test Conditions
Min
Typ Max Units
3V3 Linear Regulator
3V3 Accuracy & Load Regulation V3V3
5mA < I3V3 < 90mA, VVREG = 5.25V
3.23
3.30 3.37 V
3V3 Output Capacitance Range (2)
COUT,3V3

1.0
— 15 µF
3V3 Over Current Protection
3V3 Current Limit (1)
3V3ILIM
V3V3 = 3.3V
−110
−155
— mA
3V3 Foldback Current (1)
3V3IFBK
V3V3 = 0V
−20
−50
−80 mA
3V3 Startup Timing
3V3 Startup Time (2)
t3V3,START
C3V3 ≤ 2.9µF, Load = 66Ω±5% (50mA) — 0.5 0.8 ms
3V3 to Synchronous Buck Start Up t
om when 3V3 = V3V3,UV,H to when
3V3,BUCK
Time fro
V
TBD
— 1.0 ms
FB = VFB,UV,H
CONTROL INPUTS
Ignition Enable (ENBAT) Input
VENBAT,H
VENBAT rising
2.9
3.1 3.5 V
ENBAT Thresholds
VENBAT,L
VENBAT falling
2.2
2.6 2.9 V
ENBAT Hysteresis
VENBAT,HYS
VENBAT,H - VENBAT,L
—
500
— mV
VENBAT = 5.5V via a 1kΩ series resistoor — 50 100
ENBAT Bias Current (1)
IENBAT,BIAS
µA
VENBAT = 0.8V via a 1kΩ series resistoor 0.5 —
5
ENBAT Pulldown Resistance
RENBAT When
VENBAT < 1.2V
—
600
—
kΩ
Logic Enable (ENB) Input
VENB,H
VENB rising
—
— 2.0 V
ENB Thresholds
VENB,L
VENB falling
0.8
—
— V
ENB Bias Current (1)
IENB,IN
VENB = 3.3V
—
— 175 µA
ENB Resistance
RENB

—
60
—
kΩ
ENB/ENBAT Filter/Deglitch
Enable Filter/Deglitch Time
EN td,FILT

10
15 20
µs
nERROR Input
VnERROR,H
VnERROR rising
—
— 2.0 V
nERROR Thresholds
VnERROR,L
VnERROR falling
0.8
—
— V
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
14
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)≤VIN≤40V, −40ºC≤TA=TJ≤150ºC

DIAGNOSTIC OUTP
PUTS
Characteristic
Symbol
Test Conditions
Min
Typ Max Units
3V3 and Synchronous Buck OV/UV Protection Thresholds
V3V3,OV,H
V3V3 rising
3.41
3.51
3.60
3V3 OV Thresholds
V
V3V3,OV,L
V3V3 falling
—
3.49
—
3V3 OV Hysteresis
V3V3,OV,HYS
V3V3,OV,H – V3V3,OV,L
10
20 40 mV
V3V3,UV,H
V3V3 rising
—
3.12
—
3V3 UV Thresholds
V
V3V3,UV,L
V3V3 falling
3.00
3.10 3.19
3V3 UV Hysteresis
V3V3,UV,HYS
V3V3,UV,H – V3V3,UV,L
10
20 40 mV
Synchronous Buck FB OV
Thresholds
VFB,OV,H
VFB rising
1.35
1.385 1.42
Synchronous Buck FB UV
VFB,UV,H
VFB rising
—
1.245
—
Thresholds
V
VFB,UV,L
VFB falling
—
1.235
—
Synchronous Buck FB UV
Hysteresis
VFBUV,HYS
VFB,UV,H – VFB,UV,L
5
15 25 mV
V55CAN, V5A, V5B and V5P OV/UV Protection Thresholds
V5CAN, V5A, V5B and V5P OV
VV5,OV,H
VV5 rising
5.15
5.33 5.50
V
Thresholds
VV5,OV,L
VV5 falling
—
5.30
—
V5CAN, V5A, V5B and V5P OV
V
– V
15
30 50 mV
Hysteresis
V5,OV,HYS
VV5,OV,H
V5,OV,L
V5CAN, V5A, V5B and V5P UV
VV5,UV,H
VV5 rising
—
4.71
—
V
Thresholds
VV5,UV,L
VV5 falling
4.50
4.68 4.85
V5CAN, V5A, V5B and V5P UV
V
– V
15
30 50 mV
Hysteresis
V5,UV,HYS
VV5,UV,H
V5,UV,L
V5P Output Disconnect Threshold VV5P,DISC
VV5P rising
—
7.2
— V
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
15
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)≤VIN≤40V, −40ºC≤TA=TJ≤150ºC
DIAGNOSTIC OUTPUTS (cont’d)
Characteristic
Symbol
Test Conditions
Min
Typ Max Units
VR
REG, VCP, and BG Thresholds
VREGOV1,H VVREG rising, LX1 PWM disabled
5.50
5.62 5.75
VREG Non-Latching OV Threshold
V
VREGOV1,L
VVREG falling, LX1 PWM enabled
—
5.53
—
VREG Non-Latching OV
Hysteresis
VREGOV1,HYS VREGOV1,H – VREGOV1,L
—
100
— mV
VREG Latching OV Threshold
VREGOV2,H VVREG rising, all regulators latched off —
6.55
— V
VREG
sing, triggers riise of 3V3 linear
UV,H
VVREG ris
4.14
4.38 4.62
VREG UV Thresholds
regulator
V
VREGUV,L
VVREG falling
—
4.28
—
VREG UV Hysteresis
VREGUV,HYS VREGUV,H – VREGUV,L
—
100
— mV
VCP OV Thresholds
VCPOV,H
VVCP rising, latches all regulators off
11.0
12.5 14.0 V
VCPUV,H
VVCP rising, PWM enabled
3.0
3.2 3.4
VCP UV Thresholds
V
VCPUV,L
VVCP falling, PWM disabled
—
2.8
—
VCP UV Hysteresis
VCPUV,HYS VCPUV,H – VCPUV,L
—
400
— mV
BGREF & BGFAULT UV Thresholds (2) BGxUV BGVREF or BGFAULT rising
1.00
1.05 1.10 V
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
16
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)<VIN<40V, −40ºC≤TA=TJ≤150ºC
DIAGNOSTIC OUTPUTS (cont’d)
Characteristic
Symbol
Test Conditions
Min
Typ Max Units
NPOR Turn-on and Turn-off Delays
Time from when 3V3, Synchronous
NPOR Turn-on Delay
tdNPOR,ON
Buck output and V5A are all in
15
20 25 ms
regulation to NPOR being asserted high
NPOR Output Voltages
NPOR Output Low Voltage
V
ENBAT high,
NPOR,L
ENB or
—
150 400 mV
VIN ≥ 2.5V, INPOR = 2mA
NPOR Leakage Current (1)
INPOR,LKG
VNPOR = 3.3V
—
—
2 µA
Fault Flag Output Voltages (FFn)
FFn Output Voltage
V
or ENBAT=1 and FFn is tripped
FF,L
ENB=1
—
150 400 mV
VVIN ≥ 2.5V, IFF = 2mA
FFn Leakage Current
IFF,LKG
VFF= 3.3V
—
—
2 µA
Ignition Status (ENBATS)
ENBATS Output Voltage
VOENBATS,LO IENBATS = 2mA, VENBAT < VENBAT,L
—
— 400 mV
ENBATS Leakage Current (1)
IENBATS
VENBATS = 3.3V
—
—
2 µA
OV Filtering/Deglitch Time
Over Voltage Detection Delay
OV td,FILT
Over voltage detection delay time
10
15 20 µs
UV Filtering/Deglitch Time
UV Filter/Deglitch Times
UV td,FILT Under
voltage detection delay time
10
15 20
µs
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
17
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ELECTRICAL CHARACTERISTICS(1) Unless otherwise noted, specifications are valid at 3.8V(4)≤VIN≤40V, −40ºC≤TA=TJ≤150ºC
COMMUNICATIONS INTERFACE
Characteristic
Symbol
Test Conditions
Min
Typ Max Units
Serial Interface (STRn, SDI, SDO, SCK)
Input low voltage
VIL

—
— 0.8 V
Input high voltage
VIH
All logic inputs
2.0
—
— V
Input hysteresis
VIhys All
logic
inputs
250
550
— mV
Input pull-down  SDI, SCK
RPDS 0<VIN<5V
—
50
—
k
Input pull-up to VCC
IPU
STRn
—
50
—
k
Output low voltage
VOL
IOL=1mA1
—
0.2 0.4 V
Output high voltage
VOH
IOL=-1mA1
2.8
VDD-0.2
— V
Output leakage1
ILK,SDO
0V < VSDO < 5.5V, STRn=1
-1
— 1 µA
Clock high time
tSCKH
A in figure 4
50
—
—
ns
Clock low time
tSCKL
B in figure 4
50
—
—
ns
Strobe lead time
tSTLD
C in figure 4
30
—
—
ns
Strobe lag time
tSTLG
D in figure 4
30
—
—
ns
Strobe high time
tSTRH
E in figure 4
TBD
—
—
ns
Data out enable time
tSDOE
F in figure 4
—
—
40 ns
Data out disable time
tSDOD
G in figure 4
—
—
30 ns
Data out valid time from clock
t
ure 4
—
—
0 ns
fallling
SDOV
H in figu

4
Data out hold time from clock
t
re 4
5
—
—
fallling
SDOH
J in figu

ns
Data in set-up time to clock rising tSDIS
K in figure 4
15
—
—
ns
Data in hold time from clock rising tSDIH
L in figure 4
10
—
—
ns
Wake up from sleep
tEN

—
—
2 ms
Notes:
1) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
2) Ensured by design and characterization, not production tested.
3) Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
4) The lowest operating voltage is only valid if the conditions VVIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
19
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

STRn
C
A
B
D
E
SCK
K
L
SDI
X
D15
X
D14
X
X
D0
X
F
J
G
SDO
Z
D15'
D14'
D0'
Z
H

Figure 1: Serial Interfacce Timing
(X = don’t care. Z = high impedance (tri-state)

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
20
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

TABLE 1: STARTUP and SHUTDOWN LOGIC (signal names consistent with block diagram):
Startup sequence to be finalized

Regulator Control Bits
A4412 Status Signals
(0=OFF, 1=ON)
A4412
SYNC
V5B,
SYNC
V5B,
MODE
VREG
3V3
BUCK
V5P &
VREG
3V3
BUCK
V5P &
EN MPOR
N
NPOR
ON
ON
& V5A
V5CAN
UV
UV
& V5A
V5CAN
TIME
ON
ON
UV
UV

RESET
0
0 0  0
0 1  0
0 0  0
0
OFF
0
0 0  0
0 0  1
1 1  1
0
STARTUP
1
0 0  0
1 0  1
1 1  1
0
↓
1
1 0  0
1 0  0
1 1  1
0
↓
1
1 1  0
1 0  0
0 1  1
0
↓
1
1 1  1
1 0  0
0 0  1
1
RUN
1
1 1  1
1 0  0
0 0  0
1
15us
1
1 1  1
0 0  0
0 0  0
0
DEGLITCH
SHUTTING
1
1 0  0
0 0  0
0 0  0
0
DOWN

↓
1
0 0  0
0 0  0
0 1  1
0
↓
0
0 0  0
0 0  0
1 1  1
0
OFF
0
0 0  0
0 0  1
1 1  1
0

X = DON’T CARE
EN = ENBAT + ENB
MPOR = VCC_UV + VCP_UV + BG1_U
UV + BG2_UV + TSD + VCP_OV (latcheed) + D1MISSING
(latched) + ILIM,LX1 (latched)

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
21
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

Startup Timing Diagram
13.5V
VIN
EN
ENB OR ENBAT = HIGH
SS
VSSOFFS
COMP
fOSC/4
fOSC/2
LX1
fOSC
tSS1
t
V
SS1,DLY
VREG,UV,H
VREG
V3V3,UV,H
3V3
1.3V
fOSC/4
fOSC/2
LX2
fOSC
tSS2
Buck
VFB,UV,H
Output
VV5A,UV,H
V5A
3V3 OK*
Buck OK*
t3V3,BUCK
V5A OK*
t3V3,V5A
NPOR ON*
td NPOR,ON
NPOR

* = internal signal
Figure 2: Start Up Timing Diagram

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
22
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

Shutdown Timing Diagram

VIN
ENtd,FILT
ENB
AND
ENBAT
3V3, Sync Buck
tOUT,FALL
or V5A UV
All Outputs
UVtd,FILT
NPOR

All outputs start to decay ENtd,FILT seconds after ENB and EBAT are low.
Time for outputs to drop to zero, tOUT,FALL, various for each output and depends on load current and capacitance.
NPOR falls when 3V3, Sync Buck or V5A reaches its UV point

Figure 3: Shutdown Timing Diagram

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
23
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

TABLE 2: SUMMARY OF FAULT MODE OPERATION
FAULT TYPE
LATCH
SYNC
RESET
and
A4412 RESPONSE TO FAULT
VCC
VCP
VREG
3V3
V5CAN
V55A
V5B
V5P
NPOR
FFn
POE
DIAG
SPI
WD
FAULT?
BUCK O/P
METHOD
CONDITION
Latching Faults
Results in an MPOR after 1
CPUMP OV
detection, so all regulators are
Yes
No effect
?
off
off
off
off
off
off
off
Low
Low
Low
100khz
On
On
None
shut off
VREG over
Check the
Results in an MPOR after 1
voltage
short/ Cycle
detection, so all regulators are
Yes
No effect
No effect
off
off
off
off
off
off
off
Low
Low
Low
200khz
On
On
VREGOV2,H <
EN or Vin /
shut off
VVREG
replace 4412
VREG
Results in an MPOR after 1
Place D1 then
asynchronous
detection, so all regulators are
Yes
No effect
No effect
off
off
off
off
off
off
off
Low
Low
Low
300kHz
xx
xx
cycle EN or
diode (D1)
shut off
VIN
missing
Asynchronous
Results in an MPOR after the high
Remove the
diode (D1) short
side MOSFET current exceeds
short then
circuited or LX1
Yes
No effect
No effect
off
off
off
off
off
off
off
Low
Low
Low
400kHz
xx
xx
ILIM,LX1 so all regulators are shut
cycle EN or
shorted to
off
VIN
ground
Check for
If OV condition persists for more
1V25 over
short circuits
than tdOV then set NPOR Low
Yes
No effect
No effect
off
off
off
off
off
off
off
Low
Low
Low
500kHz
xx
xx
voltage
then cycle EN
and shut off all regulators
or VIN
FB pin will be pulled high, LX2 will
Connect the
FB pin is open
Yes
No effect
No effect
No effect
Low
off
off
off
off
off
Low
Low
Low
600kHz
xx
xx
stop switching
FB pin
Non Latching Faults
Vin UVLO
4412 is in reset state
No
Ramping Vin
off off off off off off  off  Low Low Low Low xx xx  None
BG1 UVLO
4412 is in reset state
No
Ramping Vin
off off off off off off  off  Low Low Low Low xx xx  None
BG2 UVLO
4412 is in reset state
No
Ramping Vin
off off off off off off  off  Low Low Low Low xx xx  None
VCC UVLO
4412 is in reset state
No
ON Vin  off off off off off off  off  Low Low Low Low xx xx  None
VCC short Ilimit
4412 is in reset state
No
UVLO Vin  off off off off off off  off  Low Low Low Low xx xx  None
CPUMP UVLO
4412 is in reset state
No
ON Ramping  off off off off off off  off  Low Low Low Low xx xx  None
VREG over
Low if 3V3,  Low if V5
voltage
Stop PWM switching of LX1
No
No effect
No effect
No effect
No effect  No effect No
effect No
effect  No effect
No effecct  1V25 or V5A or V5P are Low
Low No effect No effect
None
VREGOV1,H <
are too Low
too Low
VVREG
VREG will decay to 0V, LX1 will
switch at maximum duty cycle so
VREG pin open
Connect the
the voltage on the output
No
No effect
No effect
off off off off off off  off  Low Low Low Low
No effect No effect
circuit
VREG pin
capacitors will be very close to
VBAT
VREG shorted
to ground
Continue to PWM but turn off LX1
Low if 3V3,
VSS1<VHIC1,EN,
off if Vreg  off if Vreg  off if Vreg  off if Vreg  off if Vreg  off if Vreg
Remove the
when the high side MOSFET
No
No effect
No effect
Shorted
1V25 or V5A
Low
Low Low
No effect No effect
VREG<1.95V,
<UVLO
<UVLO
<UVLO
<UVLO
<UVLO
<UVLO
short circuit
current exceeds ILIM1
are too Low
VCOMP1≠EA1
VO(MAX)
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
24
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

FAULT TYPE
LATCH
SYNC
RESET
and
A4412 RESPONSE TO FAULT
VCC
VCP
VREG
3V3
V5CAN
V55A
V5B
V5P
NPOR
FFn
POE
DIAG
SPI
WD
FAULT?
BUCK O/P
METHOD
CONDITION
VREG over
current
Low if 3V3,
VSS1>VHIC1,EN,
Enters hiccup mode after 30 OCP
off if Vreg  off if Vreg  off if Vreg  off if Vreg  off if Vreg  off if Vreg
Decrease the
No
No effect
No effect
Shorted
1V25 or V5A
Low
Low Low
No effect No effect
VREG<1.95V,
faults
<UVLO
<UVLO
<UVLO
<UVLO
<UVLO
<UVLO
load
are too Low
VCOMP1=EA1
VO(MAX)
VREG over
current
Low if 3V3,
VSS1>VHIC1,EN,
Enters hiccup mode after 120
off if Vreg  off if Vreg  off if Vreg  off if Vreg  off if Vreg  off if Vreg
Decrease the
No
No effect
No effect
Shorted
1V25 or V5A
Low
Low Low
No effect No effect
VREG>1.95V,
OCP faults
<UVLO
<UVLO
<UVLO
<UVLO
<UVLO
<UVLO
load
are too Low
VCOMP1=EA1
VO(MAX)
Closed loop control will try to raise
FB/OV under
the voltage but may be
Decrease the
No
No effect
No effect
No effect
Low
No effect  No effect  No effect  No effect
No effecct Low  Low  Low Low
No effect No effect
voltage
constrained by the foldback or
load
pulse- by-pulse current limit
SYNC Buck
over current
Enters hiccup mode after 120
Decrease the
No
No effect
No effect
No effect
Low
No effect No
effect No
effect  No effect
No effecct Low  Low  Low Low
No effect No effect
VSS2>VHIC2,EN,
OCP faults
load
V1V25>470mV
FB shorted  to
Continue to PWM but turn off LX2
ground
Remove the
when the high side MOSFET
No
No effect
No effect
No effect
Low
No effect No
effect No
effect  No effect
No effecct Low  Low  Low Low
No effect No effect
VSS2<VHIC2,EN,
short circuit
current exceeds ILIM2
V1V25<470mV
Closed loop control will try to raise
3V3 under
the voltage but may be
Decrease the
No
No effect
No effect
No effect
No effect
Low
No effect  No effect  No effect
No effecct Low  Low  Low Low
No effect No effect
voltage
constrained by the foldback or
load
pulse- by-pulse current limit
3V3 over
If OV condition persists for more
>
Check for
No
No effect
No effect
No effect
No effect
No effect  No effect  No effect
No effecct Low  Low  Low Low
No effect No effect
voltage
than tdOV then set NPOR Low
V3V3,OV,H
short circuits
3V3 over
Foldback current limit will reduce
Low if 3V3  Low if 3V3 Low if 3V3
Decrease the
No
No effect
No effect
No effect
No effect
Falling
No effect  No effect  No effect
No effecct
Low No effect No effect
current
the output voltage
< V3V3,UV,L  < V3V3,UV,L < V3V3,UV,L
load
Closed loop control will try to raise
V5P under
the voltage but may be
Decrease the
No
No effect
No effect
No effect
No effect  No effect  No effect  No effect  No effect
UVLO
No effect
Low
No effect
Low
No effect No effect
voltage
constrained by the foldback
load
current limit
V5P over
Check for
If OV condition persists for more
>
voltage or
No
No effect
No effect
No effect
No effect  No effect  No effect  No effect  No effect
No effect
Low
No effect
Low
No effect No effect  short circuits
than tdOV then set FF Low
V
shorted to Vbatt
V5P,OV,H
H
on V5P
V5P over
Foldback current limit will reduce
Low if  V5P
Decrease the
No
No effect
No effect
No effect
No effect  No effect  No effect  No effect  No effect
Falling
No effect
No effect
Low
No effect No effect
current
the output voltage
are too Low
load
Closed loop control will try to raise
V5A under
the voltage but may be
Decrease the
No
No effect
No effect
No effect
No effect  No effect  No effect
Low
No effect
No effecct Low  Low  Low Low
No effect No effect
voltage
constrained by the foldback
load
current limit
Check for
V5A over
If OV condition persists for more
No
No effect
No effect
No effect
No effect  No effect  No effect  >V
ct
Low
Low
Low
Low
No effect No effect  short circuits
voltage
than tdOV then set POK5V Low
V5A,OV,H
No effect
No effec
on V5A
V5A over
Foldback current limit will reduce
Low if V5A <  Low if V5A  Low if V5A
Decrease the
No
No effect
No effect
No effect
No effect  No effect  No effect
Falling
No effect
No effecct
Low
No effect No effect
current
the output voltage
VV5A3,UV,L  < VV5A3,UV,L < VV5A3,UV,L
load
Check for
V5CAN over
If OV condition persists for more
>
No
No effect
No effect
No effect
No effect  No effect
No effect  No effect
No effecct
No effect
Low
No effect
Low
No effect No effect  short circuits
voltage
than tdOV then set POK5V Low
VV5CAN,OV,H
on V5CAN
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
255
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

TIMING DIAGRAM (not to scale): * is for “and”, + is for “or”
ENB+ENBAT HIGH
EN
VHICx,EN
VHICx,EN
VHICx,EN
SSx
VSSxOFFS
VSSx
VSSx
VSSx
RST
OFFS
VSSxRST
OFFS
EN_HICx
HICx
30x
30x
30x
OCPx
OCP
OCP
OCP
EAxVO(MAX)
PWMxOFFS
COMPx
FOSC/4
FOSC/4
FOSC/4
LXx
VREG
1.3V
(VFB)
(0.47V)
Figure 4: Hiccup Mode Operation with VREG or Synchronous Buck Shorted to GND (RLOAD<550mΩ)
ENB+ENBAT HIGH
EN
VHICx,EN
VHICx,EN
SSx
VSSxOFFFS
VSSx
VSSx
RST
OFFS
HICx
120x OCP
120x OCP
OCPx
EAxVO(MAX)
PWMxOFFS
COMPx
FOSC/4 FOSC/2
FOSC
FOSC/4 FOSC/2
FOSC
LXx
2.7V
(0.78V)
VREG
1.3V
(VFB)
(0.47V)

Figure 5: Hiccup Mode Operation with VREG or Synchronous Buck Over Loaded (RLOAD≈0.5Ω)
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
27
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

FUNCTIONAL DESCRIPTION
Overview
Chaarge Pump
The A4412 is a power management IC designed for safety
A charge pump doubler provides the voltage necessary to
critical applications. It contains seven DC/DC regulators to
drive high side n-channel MOSFETs in the pre-regulator and
create the voltages necessary for typical automotive
linear regulators. Two external capacitors are required for
applications such as electrical power steering.
charge pump operation. During the first cycle of the charge
pump action the fflying capacitor, between pins CP1 and CP2,
The A4412 pre-regulator can be configured as a buck
is charged either ffrom VIN or VREG, whichever is highest.
converter or buck boost. Buck boost is suitable for when
During the second cycle the voltage on the flying capacitor
applications need to work with extremely Low battery voltages.
charges the VCP capacitor. The VCP minus VIN voltage is
This pre-regulator generates a fixed 5.35V and can deliver up
reggulated to around 6.6V
to 1.2A to power the internal or external post regulators. These
post regulators generate the various voltage levels for the end
The charge pump incorporates some safety features
system.
1. Under
voltage and over voltage detection and
The A4412 includes six internal post regulators. Five linear
reporting
regulators and one adjustable output synchronous buck
regulator.
2. Over
current safe mode protection
Pre-Regulator
Band Gap
The pre-regulator incorporates an internal high side buck
Dual band gaps are implemented within the A4412. One band
switch and a boost switch gate driver. An external
gap is dedicated to the voltage regulation loops within each of
freewheeling diode and LC filter are required to complete the
the  regulators, VCC, VCP, VREG and the six post regulators.
buck converter. By adding a MOSFET and boost diode the
The second is dedicated to the monitoring function of all the
pre-regulator can now maintain all outputs with input voltages
reggulators under and over voltage. This improves safety
down to 3.8V.
coverage and fault reporting from the A4412.
The pre-regulator provides many protection and diagnostic
Should the regulation band gap fail then the outputs will be out
functions.
of specification and the monitoring band gap will report the
fault.
1. Pulse
by pulse and hiccup mode current limit
If the monitoring band gap fails the outputs will remain in
2. Under
voltage and over voltage detection and
reggulation but thee monitoring circuits will report the outputs as
reporting
out t of specificatioon and trip the fault flag.
3. Shorted
switch node to ground
The band gap circuits include two other band gaps that are
used to monitor the under voltage state of the main band
4. Open
freewheeling diode protection
gaps.
5. High
voltage rating for load dump
Enable
Bias Supply
Two enable pins are available on the A4412. A high signal on
The bias supply (VCC) is generated by an internal linear
either of these pins enables the regulated outputs of the
regulator. This supply is the first rail to start up. Most of the
A4412. One enable (ENB) is logic level compatible. The
internal control circuitry is powered by this supply. The bias
second enable (ENBAT), is battery level rated and can be
supply includes some unique features to ensure safe
connected to the ignition switch through a resistor.
operation of the A4412. These features include
A logic level battery enable status (ENBATS) pin provides the
1. Input
voltage under voltage lockout
user with a Low level signal of what the ENBAT input is doing.
2. Output
under voltage and over voltage detection and
Synchronous Buck
reporting
The A4412 integraates both the high side and Low side
3. Over
current and short circuit limit
switches necessary for implementing a synchronous buck
converter. It is powered by the pre-regulator output. A 1.305V
4. Dual
input, VIN and VREG, for Low battery voltage
feedback pin is provided to allow adjustment of the output from
operation
1.305V to 3.3V. A simple voltage divider sets the output
5. Short
protection of the series pass device. If the
voltage. If 1.305V is required then no divider is necessary and
internal linear regulator shorts to VIN this protection
the  converter output can be connected directly to the feedback
will ensure that the A4412 enters a safe mode
pin. If the synchronous buck converter is configured as 1.305V
then a minimum load of 100uA is required. This can either be
the  system load or an additional 10kΩ from 1.305V output to
ground.
The synchronous buck requires an LC filter onn its switch node
to compete the regulation function
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
28
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

Protection and safety functions provided by the synchronous
Startup Self-Test
buck are:
The A4412 includes self-test which is performed during the
1. Pulse
by pulse and hiccup mode current limit
startup sequence. This self-test verifies the operation of the
under voltage and over voltage detect circuits for the main
2. Under
voltage and over voltage detection and
outtputs.
reporting
In tthe event the self-test fails the A4412 will report the failure
3. Shorted
switch node to ground
through SPI.
4. Open
feedback pin protection
Und
der Voltage Detect Self-Test
5. Shorted
high side switch protection, OVP shuts down
The under voltage (UV) detectors are verified during startup of
pre-regulator
the  A4412. A voltage that is higher than the under voltage
Linear Regulators
threshold is applied to each UV comparator, this should cause
the relative under voltage fault bit in the diagnostic registers to
The A4412 has five linear regulators, one 3.3V, three 5V and
change state. If the diagnostic UV register bits change state
one protected 5V.
the corresponding verify register bits will latch high. When the
All linear regulators provide the following protection features
test of all UV detectors is complete the verify reegister bits will
remain high if the test passed. If any UV bits in the verify
1. Current
limit with fold back
reggisters, after test, are not set high then the verification has
2. Under
voltage and over voltage detection and
failed. The following UV detectors are tested, VREG, 3V3,
reporting
V5A, V5B, V5P, V5CAN and the synchronous buck.

The protected 5V regulator includes protection against
Over Voltage Deetect Self-Test
connection to the battery voltage. This makes this output most
suitable for powering remote sensors or circuitry were short to
The over voltage (OV) detectors are verified during startup of
battery is possible.
the  A4412. A voltage is applied to each OV comparator that is
higher than the overvoltage threshold, this should cause the
The pre-regulator powers these linear regulators which
relative over voltage fault bit in the diagnostic registers to
reduces power dissipation and temperature.
change state. If the diagnostic OV register bits change state
the  corresponding verify register bits will latch high. When the
Fault Detection and Reporting
test of all OV detectors is complete the verify register bits will
There is extensive fault detection within the A4412. Most have
remain high if the test passed. If any OV bits in the verify
been discussed previously. There are two fault reporting
reggisters, after test, are not set high then the verification has
mechanisms used by the A4412. One is through hardwired
failed. The following OV detectors are tested, VREG, 3V3,
pins and second reporting through a serial communications
V5A, V5B, V5P, V5CAN and the synchronous buck.
interface (SPI).

Oveer Temperature Shutdown Self-Test
Two hardwired pins on the A4412 are used for fault reporting.
The first pin, NPOR, reports on the status of the 3V3, the V5A
The over temperature shutdown (TSD detector is verified on
and synchronous buck outputs. This signal goes Low if either
startup of the A4412. A voltage is applied to the comparator
of these outputs is out of regulation. The second pin, FFn
that is Lower than the over temperature threshold and should
(Active Low fault flag), reports on all other faults. FFn goes
cause the general fault flag to be active and an over
Low if a fault within the A4412 exists. The FFn pin can be
temperature fault bit, TSD, to be latched in the Verify Result
used by the processor as an alert to check the status of the
reggister 0. When the test is complete the general fault flag will
A4412 via SPI and see where the fault occurred.
be cleared and the over temperature fault will remain in the
Verify Result register 0 until reset. If the TSD bit is not set then
The A4412 also includes a diagnostic pin, DIAG, to aid system
the  verification has failed.
debug in the event of a failure. A series of pulses with 50%

duty cycle will be sent to this pin. Their frequency will indicate
Power On Enablee Self-Test
what fault occurred within the A4412.
The A4412 also incorporates continuous self-testing of the
Fault
DIAG
power on enable (POE) output. It compares the status of the
POE pin with the internal demanded status. If they differ for
Charge pump over voltage
102 kHz
any reason an FFn is set and the POE_OK in SPI diagnostic
VREG over voltage VREG
reggister goes Low.
OV2,H2 < VVREG
204 kHz

Watchdog
VREG asynchronous diode (D1) missing
315 kHz
The watchdog circuit within the A4412 will monitor a temporal
Asynchronous diode (D1) short circuited
409 kHz
signal from a processor for its period between pulses. If the
or LX1 shorted to ground
signal does not meet the requirements, the A4412 watchdog
Synchronous buck over voltage
512 kHz
will  put the system into a safe state. It does this by setting the

power on enable (POE) pin Low, removing enabling function
of ENB pin for the A4412 and disabling the V5CAN output.
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
29
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

See figure 4 for a simplified block diagram of the watchdog
100
circuit.
1
100  fSYS,TOL

The watchdog function, see figure 5, uses two timers and two
counters to validate the incoming temporal signal. The user
100
1
has some programmability of the counters and timer windows,
100  fSYS,TOL
through SPI.
The watchdog also has provision to be placed in “flash mode”.
The first counter counts the rising edges of the temporal
While in flash mode the watchdog keeps the POE signal Low
signal. If the correct count is completed after the minimum
but t does not disable the V5CAN or the ENB function. This is
timer expires and before the maximum timer expires then the
reqquired should the processor need to be re-flashed. Flash
second (valid) counter is incremented. Once the valid counter
mode is accessed through secure SPI commands. To exit
has incremented the programmed number of counts the
“flash mode” the watchdog must be restarted via separate
watchdog issues a watchdog OK (WD_IN_OK) signal. This
secure SPI commands. If the A4412 has not lost power during
signal, along with NPOR, 3V3 enable, synchronous buck
flash mode then the watchdog will restart with the previous
enable and nERROR enables the POE.
configuration. If power was lost during flash mode then the
If the edge count reaches its final value before the minimum
watchdog configuration will be reset to default.
timer or after the maximum timer expires the valid counter
On start up the watchdog (WD_IN) must receive a series of
decrements. Once the valid counter reaches zero the
valid and qualified pulse trains, per the programmed
watchdog fault signal issues a fault has occurred. The POE is
EDGE_COUNT and VALID_COUNT registers, followed by a
driven Low, after a time out period the V5CAN output is
series of invalid qualified pulses. Once a second series of valid
disabled and after a further timeout enabling of the A4412 via
and qualified pulse are received before the power supply
the ENB pin is no longer possible.
disable time (tPS_DISABLE) expires, then the watchdog enters the
If insufficient edges are received before the maximum timer
active state and the WD_F signal on SPI becomes active, see
expires the valid counter decrements and the minimum and
figure 6. During the test state WD_F is not active and FFn
maaximum counters are reset and start to count again. If an
does not alert a watchdog fault. When the watchdog is waiting
edge is subsequently received the timers reset once again to
for the second series of pulse on WD_IN, it sets the valid
synchronize on the incoming pulses. The valid counter is not
counter to one half its programmed value. This aids in
decremented in this instance, see figure 5.
speeding up startup of a system using the A4412. Once the
WD_IN pulses have met all criteria and POE is released, then
The number of edge counts, valid counts and timer windows
the valid counter reverts to its correct programed value. If the
can be programmed through SPI. The min and max timer
second series of pulses is not received before the tPS_DISABLE
nominal values in milliseconds are calculated by the following
timee then the watchdog will enter watchdog fault mode. It will
equations:
set the POE signal low, will disable the V5CAN after tPS_DISABLE
and will remove enable control via ENB after tPS_DISABLE.
t
 k
 2  WD _ MIN 
MIN
EDGE

WD ,

If the watchdog has indicated invalid WD_IN pulses it latches
t
 k
 2  WD _ MAX 
MAX
EDGE

WD ,
the POE signal Loow. Once the power supply disable time
(t
es then the watchdog will disable the V5CAN.
Where k
PS,DISABLE) expire
EDGE is the edge count number programmed
After the anti-latch up time out, t
hen the
through SPI, default is 2
ANTI_LATCHUP, t
watchdog will remove enable control via the ENB pin. The only
WD_MIN is the min timer adjust value in milliseconds
way to prevent this would be to restart the watcchdog either
programmed in SPI, default is -0.12ms
through SPI or shutting down and restarting the A4412.
WD_MAX is the min timer adjust value in milliseconds
The processor can restart the watchdog by using a secure SPI
programmed in SPI, default is 0.12ms
command.
Tolerance on tWD,MIN and tWD,MAX is related to the system clock
tolerance, fSYS,TOL in %, by the following equations:
tANTI_LATCHUP
ENB_EN
POE Test
tPS,DISABLE
V5CAN_EN
nERROR
BUCK_ON
POE
3V3_ON
NPOR
Signal
WD_Enable_Output
WD_IN
Watchdog Monitor
Qualifier
WD_IN_OK
MIN_TIMER MAX_TIMER POE_OK POE_S
WD_F
WD_State
EDGE_COUNT
VALID_COUNT
WD_Restart
Flash Mode

SPI Signals

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
30
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

Figure 6: Watchdog Block Diagram

NPOR
WDWINDOW
WD_IN
Minimum Timer
Maximum Timer
Edge Count = 5
Valid Count = 2
WD_IN_OK
Figure 7: Watchdog Valid Signal Timing Diagram
NPOR
WD Test
WD Run
WD_IN_OK
POE
< tPS,DISABLE
WD_F
V5CAN Enable
tPS,DISABLE
tPS,DISABLE
Timer
tANTI_LATCHUP
Anti Latch Up

Figure 8: Watchdog Timing at Start Up
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
31
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

Serial Communication Interface
five bits is output. In all cases the first bit output on SDO will
always be the FF bit from the Diagnostic Register.
The A4412 provides the user with a three wire synchronous
serial interface that is compatible with SPI (Serial Peripheral
The A4412 has 12 register banks. Bit <15:11> represents the
Interface). A fourth wire can be used to provide diagnostic
register address for read and write. Bit <10> detects the read
feedback and read back of the register content.
and write operation. For write operation Bit <10> = 1 and for
read operation bit value is logic Low. Bit <9> is an unused bit.
The serial interface timing requirements are specified in the
Maximum data size is eight bits so bit<8:1> represents the
electrical characteristics table and illustrated in the Serial
data word. Last bit in serial transfer, Bit<0> is parity bit that is
Interface Timing diagram (figure 1). Data is received on the
set tto ensure odd parity in the complete 16 bit word. Odd
SDI terminal and clocked through a shift register on the rising
parity means that the total number of 1s in any transmission
edge of the clock signal input on the SCK terminal. STRn is
should always be an odd number. This ensures that there is
normally held high, and is only brought Low to initiate a serial
always at least one bit set to 1 and one bit set to 0 and allows
transfer. No data is clocked through the shift register when
detection of stuck-at faults on the serial input and output data
STRn is high allowing multiple SDI slave units to use common
connections. The pparity bit is not stored but generated on
SDI, SCK and SDO connections. Each slave then requires an
each transfer.
independent STRn connection.
Register data is output on the SDO terminal MSB first while
When 16 data bits have been clocked into the shift register,
STRn is Low and changes to the next bit on each falling edge
STRn must be taken high to latch the data into the selected
of the SCK. The firrst bit which is always the FF bit from the
register. When this occurs, the internal control circuits act on
status register, is output as soon as STRn goes Low.
the new data and the Diagnostic register is reset.
If thhere are more tthan 16 rising edges on SCL or if STRn
If there are more than 16 rising edges on SCK or if STRn
goees high and there are fewer than 16 rising edges on SCK
goes high and there are fewer than 16 rising edges on SCK
the write will be cancelled without writing data to the registers.
the write will be cancelled without writing data to the registers.
In aaddition the diagnostic register will not be reset the SE bit
In addition the Diagnostic register will not be reset and the SE
will be set to indicate a data transfer error
(serial error) bit will be set to indicate a data transfer error.
SDI: Serial data logic input with pull down. 16 bit serial word
Diagnostic information or the contents of the configuration
input MSB first.
and control registers is output on the SDO terminal MSB first
while STRn is Low and changes to the next bit on each falling
SCK: Serial clock logic input with pull down. Data is latched in
edge of SCK. The first bit, which is always the FF (fault flag)
from SDI on the rising edge of SC
CL. There must be 16 rising
bit ffrom the Diagnostic register, is output as soon as STRn
edges per write and SCK must be held high when STRn
goes Low.
changes.
Each of the programmable (configuration and control)
STRn: Serial data strobe and serial access enable logic input
registers has a write bit, WR (bit 10), as the first bit after the
with pull-up. When STRn is high any activity on SCK or SDI is
register address. This bit must be set to 1 to write the
ignored and SDO is high impedance allowing multiple SDI
subsequent bits into the selected register. If WR is set to 0,
slaves to have common SDI, SCK and SDO connections.
then the remaining data bits (bits 9 to 0) are ignored. The
state of the WR bit also determines the data output on SDO. If
SDO: Serial Data output. High impedance when STRn is
WR is set to 1 then the Diagnostic register is output. If WR is
high. Output bit 15 of the status register, the fault flag (FF) as
set to 0 then the contents of the register selected by the first
soon as STRn goes Low

Pattern at SDI pin
MSB

LSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A4
A3
A2
A1
A0
W/R
NU
D7
D6
D5
D4
D3
D2
D1
D0
P
5 bit Address


8 bit data

Pattern at SDO pin
MSB

LSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FFn
SE
TBD
TBD
TBD
TBD
TBD
D7
D6
D5
D4
D3
D2
D1
D0
P
Diagnostics
8 bit data


Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
32
Worcester, MA 01615-0036  USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

Register Mapping
 Charge
pump voltage
Status registers
 Pre-regulator voltage
The A4412 provides 3 status registers. These registers are
 Over
temperature
read only. They provide real time status of various functions
within the A4412.
 Watchdog output
These registers report on the status of all six system rails.
 Shorts
on LX pins or open diode on pree-regulator
They also report on internal rail status, including the charge
Note some of these faults will cause the A4412 to shut down
pump, VREG, VCC and VDD rails. The general fault flag and
which might shutdown the microprocessor monitoring the SPI.
watchdog fault state are found in these status registers.
In thhis event the only way to read the fault would be to have
The logic that creates the power on enable and power reset
alterative power to the microprocessor so it can read the
status are reported through these registers.
registers. If VCC of the A4412 shuts down all stored register
information is lost and the registers revert back to default
Configuration Registers
valuees.
The A4412 allows configuration of the window watchdog
Other diagnostic registers store more detail on each fault, this
timing and pulse validation parameters.
includes
An edge counter increments on every rising edge received at
 Over
voltage on a particular output or internal rail
WD_IN. The EDGE_COUNT register stores the number of
edges that must occur after the minimum timer has expired
 Under
volltage on a particular output or internal rail
and before the maximum timer has expired. The valid counter
increments upwards on a successful edge count or
 Over
curreent on a rail
decrements on an unsuccessful edge count. Once the valid
The diagnostic registers are latch registers and will hold data if
counter reaches the VALID_COUNT upward counts the pulses
a fault has occurreed but recovered. So during start up these
on WD_IN are considered valid and the watchdog fault,
registers will record a UV event on all outputs. On first read
WD_F, goes Low.
these UV events will be reported. It is recommended to reset
The number of watchdog edges counted before incrementing
these registers after start up to ensure full fault reporting.
the valid counter can be selected. This also sets the timer
These registers are reset by writing a 1 to them.
value. The minimum and maximum timers are adjusted from
Disable Register
nominal in 0.01ms steps. The number of positive counts
before the valid signal state changes can also be set.
The disable register provides the user control of the 5V
outputs. Two bits must be set high to disable an output. If only
EDGE_COUNT [0:1], 2-bit integer to set the number of
one bit is high then the 5V outputs remain on.
edges before the valid counter is incremented.
Watchdog Mode Key Register
MIN_TIMER [0:2], 3-bit integer to adjust the minimum timer
nominal value in 0.01ms steps.
At times it may be necessary to re-flash or restart the
processor. To do this the user must put the watchdog into
MAX_TIMER [0:2], 3-bit integer to adjust the maximum
“Flash Mode” or “restart. This is done by setting the writing a
tiimer nominal value in 0.1ms steps
sequence of key words to the “watchdog_mode_key” register.
VALID_COUNT [0:1] 2-bit integer to set the number of up
If the correct word sequence is not received then the
counts on the valid counter before declaring a valid pulse
sequence must restart.
trrain on WD_IN.
Oncee flash is complete the processor must send the restart
The watchdog can only be configured during idle state. This
sequence of key words for the watchdog to exit “Flash Mode”.
occurs when the A4412 is initially enabled or the watchdog is
If VCC has not been removed from the A4412 the watchdog
restarted through SPI.
will restart with thee current configuration.
The A4412 uses frequency dithering for the two switching
Verify Result Registers
regulators to help reduce EMC noise. The user can disable
On every start up the A4412 performs a self-test of the UV and
this ffeature through the SPI. Default is enabled.
OV detect circuits. This test should cause the diagnostic
Diagnostic Registers
registers to toggle state. If the diagnostic register successfully
changes state the verify result register will latch high. Upon
There are multiple diagnostic registers in the A4412. These
completion of start up the systems microprocessor can check
registers can be read to evaluate the status of the A4412. The
the verify result registers to see if the self-test passed.
high level registers will tell which area a fault has occurred.
Logic high on a data bit in this register implies that no fault has
occurred. The follo
owing are monitored by these registers

All six outputs
 A4412
bias voltage
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
33
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

TABLE 2. Register Map
HEX
Register
DEC
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Type
Address
Name
Address
7
6
5
4
3
2
1
0
0x00
status_0
0
RO
FF
POE_OK
VCC_OK
VDD_OK
V5P_OK
V5B_OK
V5A_OK
V5CAN_OK
0x01
status_1
1
RO

NPOR_OK
WD_F
TSD_OK
VCP_OK
VREG_OK
3V3_OK
BUCK_OK
0x02
status_2
2
RO
CLK_Hi
CLK_Lo
NPOR_S
POE_S
EN
NBATS
WD_STATE
0x03
diag_0
3
RW1C
V5A_OV
V5A_UV
V5CAN_OV
V5CAN_UV
V5PP_OV
V5P_UV
V5B_OV
V5B_UV
0x04
diag_1
4
RW1C
VDD_OV
VDD_UV
VREG_OV
VREG_UV
3V33_OV
3V3_UV
BUCK_OV
BUCK_UV
0x05
diag_2
5
RW1C

LX2_OK
LX1_OK
D1_OK
VCCC_OV
VCC_UV
VCP_OV
VCP_UV
0x06
output_disable
6
RW
V5P_DIS1
V5A_DIS1
V5B_DIS1
V5CAN_DIS1
V5P_DIS0
V5A_DIS0
V5B_DIS0
V5CAN_DIS0
WO
Keycode Entry (Write Only)
0x07
watchdog_mode_key
7
RO
0
0
0
0
0
0
0
Unlocked
0x08
config_0
8
RW

MAX_TIMER
MIN_TIMER
0x09
config_1
9
RW
DITH_DIS
VALID_COUNT
EDGE_COUNT
0x0A
verify_result_0
10
RW1C
V5A_OV_OK
V5A_UV_OK
V5CAN_OV_OK
V5CAN_UV_OK
V5P_OV_OK
V5P_UV_OK
V5B_OV_OK
V5B_UV_OK
0x0B
verify_result_1
11
RW1C
BIST_PASS
TSD_OK
VREG_OV_OK
VREG_UV_OK
3V3_OV_OK
3V3_UV_OK
BUCK_OV_OK
BUCK_UV_OK

Register Types:
RO = Read Only
RW = Read or Write
RW1C = Read or Write 1 to clear
WO = Write Only
Preliminary Data Sheet
Allegro MiicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
34
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.50000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

0x00. Status Register 0:

D7
D6
D5
D4
D3
D2
D1
D0
FF
POE_OK
VCC_OK
VDD_OK
V5P_OK
V5B_OK
V5A_OK
V5CAN_OK
0
0
0
0
0
0
0
0

Address 00000
Read only register
Data
FF [D7]: Fault flag. 0 = no fault, 1 = fault
POE_OK [D6]: Power on enable signal matches what A4412 is demanding, 0 = fault, 1 = no fault
VCC_OK [D5]: Internal VCC rail is OK, 0 = fault, 1 = no fault
VDD_O
OK [D4]: Internal VDD rail is OK, 0 = fault, 1 = no fault
V5P_OK [D3]: Protected 5V rail is OK, 0 = fault, 1 = no fault
V5B_OK [D2]: 5V rail B is OK, 0 = fault, 1 = no fault
V5A_OK [D1]: 5V rail A is OK, 0 = fault, 1 = no fault
V5CAN_OK [D10]: CAN bus 5V rail is OK, 0 = fault, 1 = no fault

0x01. Status Register 1:

D7
D6
D5
D4
D3
D2
D1
D0

WD_F
TSD_OK
VCP_OK
VREG_OK
3V3_OK
BUCK_OK
0
0
0
0
0
0
0
0

Address 00001
Read only register
Data
WD_F [D5]: Watchdog is active, 0 = watchdog off or no fault, 1 = watchdog fault
TSD_OK [D4]: Thermal shutdown status, 0 = over temperature event, 1 = tempeerature OK
VCP_OK [D3]: Charge pump rail is OK, 0 = fault, 1 = no fault
VREG_OK [D2]: Pre-regulator voltage is OK, 0 = fault, 1 = no fault
3V3_OK [D1]: 3.3V rail is OK, 0 = fault, 1 = no fault
BUCK_OK [D0]: Synchronous buck adjustable rail is OK, 0 = faullt, 1 = no fault

0x02. Status Register 2:

D7
D6
D5
D4
D3
D2
D1
D0
CLK_Hi
CLK_Lo
NPOR_S
POE_S
ENBATS WD_state_2 WD_state_1 WD_state_0
0
0
0
0
0
0
0
0

Address 00010
Read only register
Data
CLK_Hi [D7]: indicates if watchdog clock input is stuck high, 0 = CLK is not stuck high, 1 = clock is stuck high
CLK_Lo [D7]: indicates if watchdog clock input is stuck low, 0 = CLK is not stuck low, 1 = clock is stuck low
NPOR_S [D5]: Power on reset internal logic status, 0 = NPOR is Low, 1 = NPOR is high
POE_S
S [D4]: Power on enable internal logic status, 0 = POE is Loow, 1 = POE is high
ENBATS [D3]: Battery enable status, reports the status of the high voltage enable pin ENBAT on the A4412, 0 = ENBAT
is Low, 1 = ENBAT is high
WD_state_x [D2:D0]: Shows the state that the watchdog is currently in, see table for the different states.

WD_state_2
WD_state_1
WD_state_0
Watchdog State
0
0
0
Idle
0
0
1
Flash
0
1
0
Test Hunt
0
1
1
Test Lock
1
0
0
Test Complete
1
0
1
Running Hunt
1
1
0
Running
1
1
1
Watchdog

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
35
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

0x03. Diagnostic Register 0:

D7
D6
D5
D4
D3
D2
D1
D0
V5A_OV
V5A_UV  V5CAN_OV  V5CAN_UV  V5P_OV
V5P_UV
V5B_OV
V5B_UV
0
0
0
0
0
0
0
0

Address 00011
Read register, write 1 to clear
Data
V5A_OV [D7]: 5V rail A over voltage occurred, 0 = rail OK, 1 = over voltage occurred
V5A_UV [D6]: 5V rail A under voltage occurred, 0 = rail OK, 1 = under voltage occurred
V5CAN_OV [D5]: 5V CAN bus rail over voltage occurred, 0 = rail OK, 1 = over voltage occurred
V5CAN_UV [D4]: 5V CAN bus rail under voltage occurred, 0 = rail OK, 1 = under voltage occurred
V5P_OV [D3]: Protected 5V rail over voltage occurred, 0 = rail OK, 1 = over voltage occurred
V5P_UV [D2]: Protected 5V rail under voltage occurred, 0 = rail OK, 1 = under voltage occurred
V5B_OV [D1]: 5V rail B over voltage occurred, 0 = rail OK, 1 = over voltage occurred
V5B_UV [D0]: 5V rail B under voltage occurred, 0 = rail OK, 1 = under voltage occurred

0x04. Diagnostic Register 1:

D7
D6
D5
D4
D3
D2
D1
D0
VDD_OV
VDD_UV  VREG_OV  VREG_UV  3V3_OV
3V3_UV  BUCK_OV BUCK_UV
0
0
0
0
0
0
0
0

Address 00100
Read register, write 1 to clear
Data
VDD_OV [D7]: Internal VDD rail over voltage occurred, 0 = rail OK, 1 = over voltage occurred
VDD_UV [D6]: Internal VDD rail under voltage occurred, 0 = rail OK, 1 = under voltage occurred
VREG_OV [D5]: Pre-regulator voltage rail over voltage occurred,  0 = rail OK, 1 = over voltage occurred
VREG_UV [D4]: Pre-regulator voltage rail under voltage occurred, 0 = rail OK, 1 = under voltage occurred
3V3_OV [D3]: 3.3V rail over voltage occurred, 0 = rail OK, 1 = ovver voltage occurred
3V3_UV [D2]: 3.3V rail under voltage occurred, 0 = rail OK, 1 = uunder voltage occurred
BUCK_OV [D1]: Synchronous buck adjustable voltage rail over vvoltage occurred, 0 = rail OK, 1 = over voltage occurred
BUCK_UV [D0]: Synchronous buck adjustable voltage rail under voltage occurred, 0 = rail OK, 1 = under voltage occurred

0x05. Diagnostic Register 2:

D7
D6
D5
D4
D3
D2
D1
D0

LX2_OK
LX1_OK
D1_OK
VCC_OV
VCC_UV
VCP_OV
VCP_UV
0
0
0
0
0
0
0
0

Address 00101
Read register, write 1 to clear
Data
LX2_OK [D6]: Adjustable synchronous buck switch node is OK, 0 = fault on LX1, 1 = LX2 is working correctly
LX1_OK [D5]: Pre-regulator switch node is OK, 0 = fault on LX1, 1 = LK1 is working correctly
D1_OK [D4]: Pre-regulator freewheeling diode is OK, 0 = diode is open circuit, 11 = diode is working correctly
VCC_OV [D3]: Internal VCC rail over voltage occurred, 0 = rail OK, 1 = over voltage occurred
VCC_UV [D2]: Internal VCC rail under voltage occurred, 0 = rail OK, 1 = under voltage occurred
VCP_OV [D1]: Charge pump voltage rail over voltage occurred, 0 = rail OK, 1 = over voltage occurred
VCP_UV [D0]: Charge pump voltage rail under voltage occurred,  0 = rail OK, 1 = under voltage occurred

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
36
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

0x06. Output Disable Register:

D7
D6
D5
D4
D3
D2
D1
D0
V5P_DIS1  V5P_DIS0  V5A_DIS1  V5A_DIS0  V5B_DIS1
V5B_DIS0  V5CAN_DIIS1 V5CAN_DIS0
0
0
0
0
0
0
0
0

Address 00110
Read or write register
Data
V5P_DIS [D7:D6]: Disable protected 5V output, 11 = disabled, x0 = enabled, 0x = enabled
V5A_DIS [D5:D4]: Disable 5V rail A output, 11 = disabled, x0 = enabled, 0x = enabled
V5B_DIS [D3:D2]: Disable 5V rail B output, 11 = disabled, x0 = enabled, 0x = enabled
V5CAN
N_DIS [D1:D0]: Disable 5V CAN bus rail, 11 = disabled, x0  = enabled, 0x  = enabled

0x07. Watchdog Mode Key Register

D7
D6
D5
D4
D3
D2
D1
D0
KEY_7
KEY_6
KEY_5
KEY_4
KEY_3
KEY_2
KEY_1
KEY_0
0
0
0
0
0
0
0
0

Address 00111
Write register
Data
KEY [D7:D0]: Three 8 bit words must be sent in the correct order
r to enable flash mode or resttart the watchdog. If an
incorrect word is received then the register resets and the first word has to be resent.

Flash Mode
Restart
WORD1
0xD3
0xD3
WORD2
0x33
0x33
WORD3
0xCC
0xCD

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
37
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

0x08. Configuration Register 0:

D7
D6
D5
D4
D3
D2
D1
D0
WD_MAX_2 WD_MAX_1  WD_MAX_0 WD_MIN_2 WD_MIN_1 WD_MIN_0
0
0
1
0
0
1
0
0

Address 01000
Read or Write register
Data
WD_MAX [D5:D3]: 3-bit word to adjust the watchdog maximum tiimer set point
WD Typical
WD_MAX_2
WD_MAX_1
WD_MAX_0
Maximum Timer
Maximum Pulse
0
0
0
+0.08ms
2.08ms
f0
0
1
+0.09ms
2.09ms
0
1
0
+0.10ms
2.10ms
0
1
1
+0.11ms
2.11ms
1
0
0
+0.12ms
2.12ms
1
0
1
+0.13ms
2.13ms
1
1
0
+0.14ms
2.14ms
1
1
1
+0.15ms
2.15ms

WD_MIN [D2:D0]: 3-bit word to adjust the watchdog minimum timer set point
WD Typical
WD_MIN_2
WD_MIN_1
WD_MIN_0
Minimum Timer
Minimum Pulse
0
0
0
‐0.08ms
1.92ms
0
0
1
‐0.09ms
1.90ms
0
1
0
‐0.10ms
1.89ms
0
1
1
‐0.11ms
1.88ms
1
0
0
‐0.12ms
1.86ms
1
0
1
‐0.13ms
1.87ms
1
1
0
‐0.14ms
1.86ms
1
1
1
‐0.15ms
1.85ms

0x09. Configuration Register 1:

D7
D6
D5
D4
D3
D2
D1
D0



DITH_DIS
VALID_1
VALID_0
EDGE_1
EDGE_0
0
0
0
0
0
0
0
0

Address 01001
Read or Write register
Data
DITH_DIS [D4]: This bit allows the user to disable the dither function for the switching converters, 0 = dither enabled, 1=
dither disabled.
VALID [D3:D2]: 2-bit counter to set the number of counts before a valid watchdog signal is set or reset
Valid
VALID_1
VALID_0
Counts
0
0
2
0
1
4
1
0
6
1
1
8

EDGE [D1:D0]: 2-bit counter to set the number of edges to count t before increm
menting the VALID counter. The EDGE
value also sets the minimum and maximum nominal timers. The minimum and maximum timers will be based on the
number of edge counts times 2ms plus the delta stored in WD_MIN and WD_MAX.
Edge
EDGE_1
EDGE_0
Nominal Timer
Counts
0
0
4
8ms
0
1
6
12ms
1
0
8
16ms
1
1
10
20ms
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
38
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

0x0A. Verify Result Register 0:

D7
D6
D5
D4
D3
D2
D1
D0
V5A_OV_OK V5A_UV_OK V5CAN_OV_OK V5CAN_UV_OK 3V3_OV_OK 3V3_UV_OK BUCK_OV_OK BUCK_UV_OK
0
0
0
0
0
0
0
0

Address 01010
Read register, write 1 to clear
Data
V5A_OV_OK [D7]: 5V rail A over voltage self-test passed, 0 = test failed, 1 = test passed
V5A_UV_OK [D6]: 5V rail A under voltage self-test passed, 0 = test failed, 1 = ttest passed
V5CAN_OV_OK [D5]: 5V CAN bus rail over voltage self-test passed, 0 = test failed, 1 = test passed
V5CAN
N_UV_OK [D4]: 5V CAN bus rail under voltage self-test passed, 0 = test failed, 1 = test passed
3V3_OV_OK [D3]: 3.3V rail over voltage self-test passed, 0 = test failed, 1 = test passed
3V3_UV_OK [D2]: 3.3V rail under voltage self-test passed, 0 = test failed, 1 = test passed
BUCK_OV_OK [D1]: Synchronous buck adjustable voltage rail over voltage self-test passed, 0 = test failed, 1 = test
passed
BUCK_UV_OK [D0]: Synchronous buck adjustable voltage rail under voltage self-test passed, 0 = test failed, 1 = test
passed

0x0B. Verify Result Register 1:

D7
D6
D5
D4
D3
D2
D1
D0
BIST_PASS TSD_OK VREG_OV_OK VREG_UV_OK
V5P_OV_OK
V5P_UV_OK
V5B_OV_OK
V5B_UV_OK
0
0
0
0
0
0
0
0

Address 01011
Read register, write 1 to clear
Data
BIST_PASS [D7]: Self-test status, 0 = self-test failed, 1 = self-testt passed
TSD_OK [D6]: Thermal shutdown circuit passed self-test, 0 = tesst failed, 1 = test passed
VREG_OV_OK [D5]: Pre-regulator voltage rail over voltage self-ttest passed, 0 = test failed, 1 = test passed
VREG_UV_OK [D4]: Pre-regulator voltage rail under voltage self-test passed, 0 = test failed, 1 = test passed
V5P_OV_OK [D3]: Protected 5V rail over voltage self-test passed, 0 = test failed, 1 = test passed
V5P_UV_OK [D2]: Protected 5V rail under voltage self-test passed, 0 = test failed, 1 = test passed
V5B_OV_OK [D1]: 5V rail B over voltage self-test passed, 0 = test failed, 1 = test passed
V5B_UV_OK [D0]: 5V rail B under voltage self-test passed, 0 = test failed, 1 = ttest passed

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
39
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

APPLICATIONS

The following section briefly describes the component

selection procedure for the A4412.
SE1 is in A/µs, fSW is in kHz, and L will be in µH

Settting up the Pre Regulator
This section discusses the component selection for the A4412
(VREG  V )
2  (VREG  V )
F
 L1
F

(2)
pre-regulator. It covers the charge pump circuit, inductor,
S
S
diodes, boost MOSFET, and input and output capacitors. It
E1
E1
will also cover soft start and loop compensation.

If equations 2 yield an inductor value that is not a standard
Charge Pump Capacitors
value then the next closest available value should be used.
The charge pump requires two capacitors: a 1µF connected
The  final inductor value should allow for 10% − 20% of initial
from pin VCP to VIN and 0.22µF connected between pins
tolerance and 20% − 30% for inductor saturation.
CP1 and CP2 These capacitors should be a high-quality

ceramic capacitor, such as an X5R or X7R, with a voltage
Due to topology and frequency switching of the A4412 pre-
rating of at least 16V.
regulator the inductor ripple current varies with input voltage

per ffigure 10 below.
PWM Switching Frequency
2
The switching frequency of the A4412 is fixed at 2.2MHz
1.8
nominal. The A4412 includes a frequency foldback scheme
that starts when VIN is greater than 18V. Between 18V and
1.6
36V the switching frequency will foldback from 2.2MHz typical
) 1.4
to 1MHz typical. The switching frequency for a given input
t (A
en
volttage above 18V and below 36V is
rr 1.2
1.2
ak Cu
1

f
 3.4 
VIN (MHz)  (1)
r Pe
SW
0.8
18
to

duc 0.6
In
2.2
0.4
0.2
2
z)
0
0
5
10
15
20
25
30
35
40
(MH()
cy
Input Voltage (V)
n 1.8

ue
eq
Figure 10. Typical Peak Inductor Current versus Input
g Fr 1.6
g
Voltage for 0.8A Output Current and 10uH Inductor
hin

tcc
The  inductor should not saturate given the peak operating
St 1.4
l Swi
currrent during overload. Equation 3 calculates this current. In
ica
yp
equation 3 V
is the maximum continuous input voltage,
T
IN,MAX
1.2
such as 16V, and VF is the asynchronous diodes forward
voltage.
1

0
5
10
15
20
25
30
35
40
S  (VREG V )
Input Voltage (V)

1
E
F

I
 4 6
.
E
A
  (3)
1
PEAK
Figure 9. Typical Switching Frequency versus Input
9
.
0  f
(V
V )
SW
IN ,MA
AX
F
Voltage

Afteer an inductor is chosen it should be tested during output
Pre-Regulator Output Inductor (L1)
overload and short circuit conditions. The inductor current
For peak current mode control it is well known that the system
should be monitored using a current probe. A good design
will become unstable when the duty cycle is above 50%
should sure the inductor or the regulator are not damaged
without adequate Slope Compensation (SE). However, the
when the output is shorted to ground at maximum input
slope compensation in the A4412 is a fixed value. Therefore,
voltage and the highest expected ambient temperature.
it’s important to calculate an inductor value so the falling slope

of the inductor current (SF) will work well with the A4412’s
Inductor ripple current can be calculated using equation 4, for
slope compensation.
buck mode and equation 5 for buck-boost mode.

Equations 2 can be used to calculate a range of values for the
) 
output inductor for the buck-boost. In equation 2, slope
V VREG
VREG
I

IN
 (

(4)
compensation can be found in the electrical characteristic
L1
f
 L1V
table, and V
SW
IN
F is the asynchronous diodes forward voltage.
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
40
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre
re-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

V  D
obtain acceptable gain and phase margins.  Selection of the

I
IN


BOOST
(5)
compensation components (R C
cussed in more
B / B
Z, CZ, CP) are dis
f
 1
L
detail in the Compensation Components section of this data
SW

sheet.

Pre-Regulator Output Capacitors
Ceramic Input Capacitors
The output capacitors filter the output voltage to provide an
The  ceramic input capacitor(s) must limit the voltage ripple at
accceptable level of ripple voltage. They also store energy to
the VIN pin to a relatively low volttage during maximum load.
help maintain voltage regulation during a load transient. The
Equation 9 can be  used to calcullate the minimum input
volttage rating of the output capacitors must support the output
capacitance,
volttage with sufficient design margin.

I
 0.25
VREG , MAX
The output voltage ripple (∆V
C
M


(9)
OUT) is a function of the output
IN
capacitors parameters: Co, ESR
0.90  f
 50mV
Co, ESLCo.
SW

V

 I
  ESR 
Where IVREG,MAX is the maximum current from the pre-
OUT
L1
CO
regulator,
V  VREG

IN
 ESL 
(6)
L1
CO
IVREG,MAX
I


L1

6.7 I
)
I
 I

SYNC _ BUCK 
(10
20mA
8  f
Co
LINEAR
AUX
SW
VSYNC _ BUCK

Where I
e sum of all the internal linear regulators
The type of output capacitors will determine which terms of
LINEAR is the
output currents, I
current drawn from the
equation 6 are dominant. For ceramic output capacitors the
AU
UX is any extra
VREG output to power other devices external to the A4412.
ESRCO and ESLCO are virtually zero so the output voltage
I
e output current and voltage
ripple will be dominated by the third term of equation 6.
SYNC_BUCK and VSYNC_BUCK are the
of the synchronous buck convertter.

I

A good design should consider the dc-bias effect on a ceramic

VREG 
L1

(7)
capacitor – as the applied voltage approaches the rated value,
8 f
Co
SW
the capacitance value decreases. The X5R and X7R type

capacitors should be the primary choices due to their stability
To reduce the voltage ripple of a design using ceramic output
versus both DC bias and temperature. For all ceramic
capacitors simply increase the total capacitance, reduce the
capacitors, the DC bias effect is even more pronounced on
inductor current ripple (i.e. increase the inductor value), or
smaller case sizes so a good design will use the largest
increase the switching frequency.
afforrdable case size.

The transient response of the regulator depends on the
Also for improved noise performance it is recommended to
number and type of output capacitors. In general, minimizing
add smaller sized capacitors close to the input pin and the D1
the ESR of the output capacitance will result in a better
anode. Use a 0.1uF, 0603 capacitor
transient response. The ESR can be minimized by simply

adding more capacitors in parallel or by using higher quality
Buck-Boost Asynchronous Diode (D1)
capacitors. At the instant of a fast load transient (di/dt), the
The  highest peak current in the asynchronous diode (D1)
output voltage will change by the amount
occurs during overload and is limited by the A4412. Equation

3 can be used to calculate this current.
di

VREG  I
 ESR 
ESL

(8)
The  highest average current in the asynchronous diode
LOAD
CO
dt
CO
occurs when VIN is at its maximum, DBOOST=0%, and

DBUCK=minimum (10%),
After the load transient occurs, the output voltage will deviate

from its nominal value for a short time. This time will depend


(11)
on the system bandwidth, the output inductor value, and
I
0.9 I
AVG
VREG , MAX
output capacitance. Eventually, the error amplifier will bring

the output voltage back to its nominal value.
Where IVREG,MAX is calculated using equation 10.

The speed at which the error amplifier will bring the output
Boost MOSFET (Q1)
volttage back to its set point will depend mainly on the closed-
The  RMS current iin the boost MOSFET (Q1) occurs when
loop bandwidth of the system. A higher bandwidth usually
VIN is at its minimuum and both the buck and boost operate at
results in a shorter time to return to the nominal voltage.
their maximum duty cycles (approximately 64% and 58%,
However, a higher bandwidth system may be more difficult to
respectively),
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
41
Worcester, MA 01615-0036  USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre
re-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

ISS1
 t
SU
SS1
I

C

(14)
Q ,
1 RMS
SS1
0.8
If a nnon-standard capacitor value for C
lculated, the



SS1 is ca
I


I
  (12)
B / B 2
next larger value should be used.
D
 I

 
B / B 
T


BOOST
 PK,B/ B


2

12 
The  voltage at the soft start pin will start from 0V
V and will be

charged by the soft start current, ISS1SU. However, PWM
Where I
switching will not begin instantly because the voltage at the
PK,B/B and ∆IB/B are derived using equations 3 and 5,
respectively.
soft start pin must rise above the soft start offset voltage

(VSS
S1OFFS). The soft start delay (tSS1,DELAY) can be calculated
Boost Diode (D2)
using equation 13,
In buck mode this diode will simply conduct the output current.

However, in buck boost mode the peak currents in this diode
VSS1

may increase quite a bit. The A4412 limits the peak current to
t
 C 
OFFS   (15)
the value calculated using equation 4. The average current is
SS ,
1 DELAY
SS1
 ISS1

simply the output current
SU

Pre-Regulator Soft Start and Hiccup Mode Timing (C
When the A4412 is in hiccup mode, the soft start capacitor
SS1)
The soft start time of the buck-boost converter is determined
sets the hiccup period. During a startup attempt, the soft start
by the value of the capacitance at the soft start pin, C
pin charges the soft start capacittor with ISS1SU and
SS1.

discharges the same capacitor with ISS1HIC between startup
If the A4412 is starting into a very heavy load a very fast soft
attem
mpts.
start time may cause the regulator to exceed the pulse-by-

pulse over current threshold. This occurs because the total of
Pre-Regulator Compensation Components (RZ, CZ, CP)
the full load current, the inductor ripple current, and the
Although the A44112 can operate in Buck-Boost mode at low
additional current required to charge the output capacitors
input voltages it still can be considered a buck converter when
(I
looking at the control loop. With that said the following
CO=CO x VOUT / tSS) is higher than the pulse-by-pulse current
threshold, as shown in figure 11.
equations can be used to calculate the compensation

components.

Firstly we need to select the target cross over frequency for
ILIM
}
our ffinal system. While we are switching at over 2MHz the
ILOAD
cross over is really governed by the required phase margin.
Since we are using a type II com
mpensation scheme we are
Output
limited to the amount of phase we can add. Hence we select a
cross over frequency, fC, in the region of 55kHz. The total
capacitor
system phase will drop off at higher cross over frequencies.
current, I
The  R
s based on the gain required at the cross
CO
Z selection is
over frequency andd can be calculated by the following
tSS
simplified equation.

Figure 11: Output current (I
 

CO) during startup
36
.
13

f
Co
C

R
(16)
Z

To avoid prematurely triggering hiccup mode the soft start
gm
gm
POWE 1
R
1
EA
time, t

SS1, should be calculated according to equation 13,

The  series capacitor, CZ, along with the resistor, RZ, set the
Co
location of the compensation zero. This zero should be placed

t
 VREG 

(13)
no lower than ¼ the cross over frequency and should be kept
SS1
I
to minimum value. Equation 17 can be used to estimate this
CO

capacitor value.
Where VOUT is the output voltage, COUT is the output

4
capacitance, I
C
(17)
CO is the amount of current allowed to charge
Z

2 
the output capacitance during soft start (recommend 0.1A <
R  f
Z
C
ICO < 0.3A). Higher values of ICO result in faster soft start time

and lower values of ICO insure that hiccup mode is not falsely
Determine if the second compensation capacitor (CP) is
triggered. We recommend starting the design with an ICO of
required. It is required if the ESR zero of the output capacitor
0.1A and increasing it only if the soft start time is too slow.
is loocated at less than half of the switching frequency or the

following relationship is valid:
Then CSS1 can be selected based on equation 14,

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
42
Worcester, MA 01615-0036  USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre
re-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

1
f
A4412

SW


(18)
L2
2  Co  ESR
2
VSYNC_BUCK
CO
LX2

R
R
OV1
FB1
If this is the case, then add the second compensation
Co
OV
capacitor (CP) to set the pole fP3 at the location of the ESR
FB
zero. Determine the CP value by the equation:


ROV2
RFB2

C
ESR
OU
C 
UT

(19)
P
R

Z

Figure 13: Prog
graming the A4412 Synchronous Buck
Finally, we take a look at the combined bode plot of both the
Output
conntrol-to-output and the compensated error amp – see the

red curves shown in figure 12. Careful examination of this plot
The  resistors can be selected based on the following
shows that the magnitude and phase of the entire system are
equation, set RFB2 = ROV2 = 10kΩ
simply the sum of the error amp response (blue) and the
VSYNC _ BUCK
conntrol to output response (green). As shown in figure 12, the
R
 R

 R
 R
(20)
FB1
OV 1
FB 2
FB 2
bandwidth of this system (fc) is 50kHz, the phase margin is
VFB
71.5 degrees, and the gain margin is 30dB.

Synchronous Bucck Output Inductor (L2)
Total System
Equation 21 can be used to calculate a range of values for the
80
180
output inductor for  the synchronous buck regulator. In
f
equation 21, slope compensation can be found  in the
Z2=8.8kHz
60
f
135
P3≈2MHz
electrical characteristic table

40
PM=71.5°
90
SE2 is in A/µs, fSW is in kHz, and L will be in µH
20
45

Pha
dB
fc=50kHz
V
2 V
‐
s
SYNC , BUCK
SYNC , BUCK
0
0
e


(21)
‐
L2
Gain
°
S
S
GM=30dB
E 2
E 2
‐20
‐45

If equation 21 yields an inductor value that is not a standard
‐40
‐90
value then the next closest available value should be used.
‐60
Total Gain
E/A Gain
‐135
The  final inductor value should allow for 10% − 20% of initial
C to O Gain
Total Phase
E/A Phase
C to O Phase
tolerance and 20% − 30% for inductor saturation.
‐80
‐180
0.3
0.1
1
10
100
1000
Frequency ‐ Hz

0.25
Figure 12: Bode plot of the complete system (red curve)
)
RZ = 8.25kΩ, CZ = 2.2nF, CP = 10pF
t (A 0.2
Lo = 10uH, Co = 2x 10uF Ceramic
n
rre

Synchronous Buck Component Selection
k Cu 0.15
Similar design methods can be used for the synchronous
r Pea
to
buck, however the complexity of variable input voltage and
duc 0.1
boost operation and removed.
In

0.05
Settting the Output Voltage, RFB1 and RFB2
VSYNC_BUCK=1.3V
If the output of the synchronous buck is connected directly to
VSYNC_BUCK=3.3V
the FB pin then the output will be regulated to VFB or 1.305V
0
nominal. The OV pin should also be connected to the output
0
5
10
15
20
25
30
35
40
Input Voltage (V)
to provide open feedback protection.

Fiigure 14: Typical Peak Inductor Current versus Input
The A4412 also allows the user to program the output voltage.
Voltage for 0.18A Output Current and 10uH Inductor
This is achieved by adding a resistor divider from its output to

ground and connecting the center point to FB, see figure 15
The  inductor should not saturate given the peak current at
below.
overload according to equation 22.


Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
43
Worcester, MA 01615-0036  USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre
re-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

S
V
If thiis is the case, then add the second compensation
E 2
SYNC,BUCK

I
 4
.
2 A 

(22)
capacitor (CP) to set the pole fP3 at the location of the ESR
PEAK2
0 9
.  f
VREG
zero. Determine the CP value by the equation:
SW

After an inductor is chosen it should be tested during output
C
 ESR
OUT
C 

(28)
short circuit conditions. The inductor current should be
P
R
monitored using a current probe. A good design should be
Z

sure the inductor or the regulator are not damaged when the
Finally, we take a look at the combined bode plot of both the
output is shorted to ground at maximum input voltage and the
control-to-output and the compensated error amp – see the
highest expected ambient temperature.
red curves shown in figure 15. The bandwidth of this system

(fc) is 51kHz, the phase margin is 75°, and the gain margin is
Once inductor value is known the ripple current can be
>30ddB.
calculated

(VREG V
) V

I


SYN
NC, BUCK
SYNC,SYNC  (23)
Total System
L2
80
180
f
 L2VREG
SW

60
135
Synchronous Buck Output Capacitors
Similar criteria as the pre-regulator can be used in selecting
40
PM=75°
90
the output capacitors. Ceramic output capacitors should be
20
45
used so for a given output voltage ripple the minimum output
Ph
dB
ase
capacitor value can be calculated using equation 25.
‐ 0
n
fc=51kHz
0
‐

Gai
°

GM>30dB
I

‐20
‐45

Co 
L2

(24)
8  f
 V

‐40
‐90
SW
SYNC, BUCK

‐60
Total Gain
E/A Gain
‐135
Synchronous Buck Compensation Components
C to O Gain
Total Phase
E/A Phase
C to O Phase
Again similar techniques as used with the pre-regulator can
‐80
‐180
be used to compensate the synchronous buck.
0.1
1
10
100
1000

Frequency ‐ Hz

For the synchronous buck we select a cross over frequency,

f
Figure 15: Bode plot of the Complete System (red curve)
C, in the region of 50kHz. The RZ selection is based on the
gain required at the cross over frequency and can be
RZ = 22.74kΩ, CZ = 4.7nF, CP = 10pF
calculated by the following simplified equation.
Lo = 10uH, Co = 10uF Ceramic

Synchronous Bucck Soft Start and Hiccup Mode Timing
V
 2  f  Co

The  soft start time of the synchronous buck is determined by
R  SYNC _ BUCK

C
(25)
Z
V
 gm
 gm
the value of the capacitance at the soft start pin, CSS2.
FB
POWER 2
EA2

If thee A4412 is starting into a very heavy load a very fast soft
The series capacitor, CZ, along with the resistor, RZ, set the
start time may cause the regulator to exceed the pulse-by-
location of the compensation zero. This zero should be placed
pulse over current threshold. To avoid prematurely triggering
no lower than ¼ the cross over frequency and should be kept
hiccup mode the soft start time, tSS2, should be calculated
to minimum value. Equation 26 can be used to estimate this
according to equation 30,
capacitor value.

4

C 

(26)
Co

Z

t
 V
(29)
2  R  f
SS 2
SYNC _ BUCK
Z
C
ICO

Dettermine if the second compensation capacitor (CP) is
Where VOUT is the output voltage, Co is the output
required. It is required if the ESR zero of the output capacitor
capacitance, ICO is the amount of current allowed to charge
is located at less than half of the switching frequency or the
the output capacitance during soft start (recommend 20mA <
following relationship is valid:
ICO < 30mA). Higher values of ICO result in faster soft start

time and lower values of ICO insure that hiccup mode is not
1
f
falsely triggered. We recommend starting the design with an

SW


(27)
ICO of 20mA and increasing it only if the soft start time is too
2  Co  ESR
2
CO
slow.

Then CSS1 can be selected based on equation 30,
Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
44
Worcester, MA 01615-0036  USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre
re-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

PCB Layout Guidelines
ISS1
 t
The  input ceramic capacitors must be located as close as

C

SU
SS1
(30)
possible to the VIN pins. In general, the smaller capacitors
SS1
0 8
.
(0402, 0603) must be placed very close to the VIN pin. The

larger capacitors should be placed within 0.5 innches of the
If a non-standard capacitor value for CSS1 is calculated, the
VIN pin. There muust not be any vias between the input
next larger value should be used.
capacitors and the VIN pins.

The voltage at the soft start pin will start from 0V and will be
The  pre-regulator input ceramic capacitors, A4412 VIN and
charged by the soft start current, ISS2SU. However, PWM
LX1, and asynchronous diode (D1), must be routed on one
switching will not begin instantly because the voltage at the
layer. This loop shhould be as small as possible, see below.
soft start pin must rise above the soft start offset voltage
The  snubber (RN11 and CN1) should be placed close to D1. A
(VSS2OFFS). The soft start delay (tSS2,DELAY) can be calculated
single star point ground connected to the ground plane using
using equation 31,
multiple vias is recommended.

VSS2


t
 C 
OFFS
(31)
SS 2, DELAY
SS 2


 ISS2SU 

When the A4412 is in hiccup mode, the soft start capacitor
sets the hiccup period. During a startup attempt, the soft start
pin charges the soft start capacitor with ISS1SU and
discharges the same capacitor with ISS1HIC between startup
attempts.

Linear Regulators
The five linear regulators only require an ceramic capacitor to
ensure stable operation. The capacitor any be any value
between 1μF and 15μF. A 2.2μF capacitor per regulator is
recommended.

Also, since the V5P is used to power remote circuitry it’s load
cann include long cables. The inductance of these cables may

cause negative spikes on the V5P pin if a short occurs. It is

recommended to use a small diode to clamp this negative
The  pre-regulator ooutput inductor (L1) should be located close
spike. A MSS1P5 is recommended.
to the LX1 pins. The LX1 trace widths (to L1, D1) should be

relatively wide and preferably on the same layer as the IC.
Internal Bias, (VCC)

The internal bias voltage should be decoupled at the VCC pin
The  pre-regulators output ceramic capacitors should be
using a 1μF ceramic capacitor. It is not recommended to use
located near the VREG pin. There must be 1 or 2 smaller
this pin as a source.
ceramic capacitors as close as possible to the VREG pin.

Signal Pins, (NPOR, ENBATs, FFn, POE, DIAG)
The A4412 has many signal level pins. The NPOR, FFn and
ENBATS are open drain outputs and require external pull up
resiistors. The DIAG and POE signals are push-pull outputs
and do not require external pull up resistors.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
45
Worcester, MA 01615-0036  USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre
re-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

The synchronous buck output inductor should be located near
the LX2 pins. The trace from the LX2 pins to the output
inductor (L2) should be relatively wide and preferably on the
same layer as the IC.

The two synchronous buck feedback resistors (RFB1, RFB2)
must be located near the FB pin. The output capacitors should
be located near the load. The output voltage sense trace (to
RFB1) must connect at the load for the best regulation, trace

A in figure below goes to load.

The two charge pump capacitors must be placed as close as

possible to VCP and CP1/CP2.

The ceramic capacitors for the LDOs (3V3, V5A, V5B, V5P,
The thermal pad uunder the A4412 must connect to the ground
and V5CAN) must be placed near their output pins. The V5P
plane(s) with multiple vias.
output must have a 1 A/40 V Schottky diode (D3) located very

close to its pin to limit negative voltages.

The VCC bypass capacitor must be placed very close to the
VCC pin.

The COMP network for both buck regulators (CZx, RZx, CPx)
must be located very close to the COMPx pin.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
46
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre
re-Regulator with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

The boost MOSFET (Q1) and the boost diode (D2) must be
placed very close to each other. Q1 should have thermal vias
to a polygon on the bottom layer. Also, there should be “local”
bypass capacitors from D2 anode to Q1 source.

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
47
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

INPUT/OUTPUT STRUCTURES (to be confirmed)

FFn, DIAG, NPOR, 3V3, V5A, V5B, V5CAN,
VCP, CP1, CP2
VREG, ENB, ENBAT, ENBATS, FB, OV,
CP1
COMP1, COMP2, SS1, SS2, WD_IN,
nERROR, VC
CC, LG, POE
CP2
PIN
VCP
9V
58V
LX2
LX1
VREG
VIN
552V
9V
LX2
LX1
SDO
SDI, SCK
VDD
VDD
50Ω
SDO
2k
PIN
9V
9V
9V
50k
STRn Input
V5P
AGND, PGND
VDD
VDD
50k
2k
PIN
V5P
52V
9V
9V
AGND
PGND

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
48
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

A4412
Buck or Buck/Boost Pre-Regulattor with a Synchronous Buck,

5 Internal Linear Regulators, Pulse Width Watchdog Timer, and SPI

PACKAGE INFORMATION – (LV) eTSSOP-38

Preliminary Data Sheet
Allegro MicroSystems, Inc.
Subject to Change Without Notice
115 Northeast Cutoff
49
Worcester, MA 01615-0036 USA
May20th, 2015

1.508.853.5000; www.allegromicro.com

5 - AUTOSAR_SWS_SPIHandlerDriver

Specification of SPI Handler/Driver

6 - AUTOSAR_SWS_SPIHandlerDriver_ind

Outline
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7 - AUTOSAR_SWS_SPIHandlerDrivers

Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
Document Title
Specification of SPI Han-
dler/Driver
Document Owner
AUTOSAR
Document Responsibility
AUTOSAR
Document Identification No
038
Document Classification
Standard

Document Version
3.2.0
Document Status
Final
Part of Release
4.0
Revision
3

Document Change History
Date
Version  Changed by
Change Description
24.11.2011
3.2.0
AUTOSAR
•  Rephrased: requirement SPI002, SPI046,
Administration
SPI129, SPI233, SPI163, SPI 171,
SPI172, SPI289 and SPI290, block 2 in
chapter 7.2.2
•  Removed: requirement SPI083; SPI132,
SPI284 and SPI107 removed from state-
ment
•  Corrected:Dem_EventStatusType in
SPI191, Spi_SyncTransmit Syn/Async
changed to Synchronous,
SPI_E_PARAM_POINTER in SPI371,
•  Reference to MCU in SPI244 and SPI342
•  Added: requirement SPI140, chapter 10 -
SpiCsSelection, SPI194 -
SPI_JOB_QUEUED state introduced,
SPI195 with error table update
•  Modified: SPI114 and SPI135, chapter 10
- SpiEnableCs
12.11.2010
3.1.0
AUTOSAR
•  Added SPI369, SPI371, SPI370
Administration
•  Removed SPI190, SPI094
•  Updated configuration: base on min-max
value for defined parameter; SpiHwUnit
belongs to SpiExternalDevice Container;
updated SpiTimeClk2Cs
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
Document Change History
Date
Version  Changed by
Change Description
11.12.2009
3.0.0
AUTOSAR
•  Splitting and refinement of several re-
Administration
quirements
•  Removal of redundant requirements
•  Introduction of new IDs to allow imple-
mentation of debugging concept
•  Inserted UML diagram in chapter 9
•  Updating of Chapter 10 with the inclusion
of 2 new container and the definition of
the Chip Select configuration
•  Legal disclaimer revised
23.06.2008
2.2.1
AUTOSAR
•  Legal disclaimer revised
Administration
12.12.2007
2.2.0
AUTOSAR
•  Updated Chapter 10 with the inclusion of
Administration
CS configuration
•  Document meta information extended
•  Small layout adaptations made
31.01.2007
2.1.0
AUTOSAR
•  Configuration Specification updating
Administration
•  General rephrasing for clarification
•  Syntax error
•
•  Legal disclaimer revised
•  Release Notes added
•  “Advice for users” revised
•  “Revision Information” added
28.04.2006
2.0.0
AUTOSAR
Document structure adapted to common Re-
Administration
lease 2.0 SWS Template.
•  Major changes in chapter 10
•  Structure of document changed partly
•  Other changes see chapter 13
09.06.2005
1.0.0
AUTOSAR
Initial Release
Administration
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
Disclaimer

This specification and the material contained in it, as released by AUTOSAR is for
the purpose of information only. AUTOSAR and the companies that have contributed
to it shall not be liable for any use of the specification.

The material contained in this specification is protected by copyright and other types
of Intellectual Property Rights. The commercial exploitation of the material contained
in this specification requires a license to such Intellectual Property Rights.

This specification may be utilized or reproduced without any modification, in any form
or by any means, for informational purposes only.
For any other purpose, no part of the specification may be utilized or reproduced, in
any form or by any means, without permission in writing from the publisher.

The AUTOSAR specifications have been developed for automotive applications only.
They have neither been developed, nor tested for non-automotive applications.

The word AUTOSAR and the AUTOSAR logo are registered trademarks.

Advice for users

AUTOSAR Specification Documents may contain exemplary items (exemplary refer-
ence models, "use cases", and/or references to exemplary technical solutions, devic-
es, processes or software).

Any such exemplary items are contained in the Specification Documents for illustra-
tion purposes only, and they themselves are not part of the AUTOSAR Standard.
Neither their presence in such Specification Documents, nor any later documentation
of AUTOSAR conformance of products actually implementing such exemplary items,
imply that intellectual property rights covering such exemplary items are licensed un-
der the same rules as applicable to the AUTOSAR Standard.
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
1  Introduction and functional overview

The SPI Handler/Driver provides services for reading from and writing to devices
connected via SPI busses. It provides access to SPI communication to several users
(e.g. EEPROM, Watchdog, I/O ASICs). It also provides the required mechanism to
configure the onchip SPI peripheral.

This specification describes the API for a monolithic SPI Handler/Driver. This soft-
ware module includes handling and driving functionalities. Main objectives of this
monolithic SPI Handler/Driver are to take the best of each microcontroller features
and to allow implementation optimization depending on static configuration to fit as
much as possible to ECU needs.

Hence, this specification defines selectable levels of functionalities and configurable
features to allow the design of a high scalable module that exploits the peculiarities of
the microcontroller.

To configure the SPI Handler/Driver these steps shall be followed:
•  SPI Handler/Driver Level of Functionality shall be selected and optional fea-
tures configured.
•  SPI Channels shall be defined according to data usage, and they could be
buffered inside the SPI Handler/Driver (IB) or provided by the user (EB).
•  SPI Jobs shall be defined according to HW properties (CS), and they will con-
tain a list of channels using those properties.
•  As a final step, Sequences of Jobs shall be defined, in order to transmit data
in a sorted way (priority sorted).

The general behaviour of the SPI Handler/Driver can be asynchronous or synchro-
nous according to the Level of Functionality selected.

The specification covers the Handler/Driver functionality combined in one single
module. One is the SPI handling part that handles multiple access to busses that
could be located in the ECU Abstraction layer. The other part is the SPI driver that
accesses the microcontroller hardware directly that could be located in the Microcon-
troller Abstraction layer.

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
2  Acronyms and abbreviations

Acronyms and abbreviations which have a local scope and therefore are not con-
tained in the AUTOSAR glossary must appear in a local glossary.

Acronym:
Description:
DET
Development Error Tracer – module to which development errors are reported.
DEM
Diagnostic Event Manager – module to which production relevant errors are report-
ed.
SPI
Serial Peripheral Interface. It is exactly defined hereafter in this document.
CS
Chip Select
MISO
Master Input Slave Output
MOSI
Master Output Slave Input

Abbreviation:  Description:
EB
Externally buffered channels. Buffers containing data to transfer are outside the SPI
Handler/Driver.
IB
Internally buffered channels. Buffers containing data to transfer are inside the SPI
Handler/Driver.
ID
Identification Number of an element (Channel, Job, Sequence).

Definition:
Description:
Channel
A Channel is a software exchange medium for data that are defined with the same
criteria: Config. Parameters, Number of Data elements with same size and data
pointers (Source & Destination) or location.
Job
A Job is composed of one or several Channels with the same Chip Select (is not
released during the processing of Job). A Job is considered atomic and therefore
cannot be interrupted by another Job. A Job has an assigned priority.
Sequence
A Sequence is a number of consecutive Jobs to transmit but it can be rescheduled
between Jobs using a priority mechanism. A Sequence transmission is interruptible
(by another Sequence transmission) or not depending on a static configuration.

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
3  Related documentation

3.1  Input documents

[1]    Layered Software Architecture
AUTOSAR_EXP_LayeredSoftwareArchitecture.pdf

[2]    General Requirements on SPAL
AUTOSAR_SRS_SPALGeneral.pdf

[3]    General Requirements on Basic Software Modules
AUTOSAR_SRS_BSWGeneral.pdf

[4]    Specification of Development Error Tracer
AUTOSAR_SWS_DevelopmentErrorTracer.pdf

[5]    Specification of ECU Configuration
AUTOSAR_TPS_ECUConfiguration.pdf

[6]    Requirements on SPI Handler/Driver
AUTOSAR_SRS_SPIHandlerDriver.pdf

[7]    Specification of Diagnostic Event Manager
AUTOSAR_SWS_DiagnosticEventManager.pdf

[8]    Glossary
AUTOSAR_TR_Glossary.pdf

[9]    Specification of MCU Driver
AUTOSAR_SWS_MCUDriver .pdf

[10]  Specification of PORT Driver
AUTOSAR_SWS_PORTDriver

[11]
Basic Software Module Description Template,
    AUTOSAR_TPS_BSWModuleDescriptionTemplate.pdf

[12]  List of Basic Software Modules
AUTOSAR_TR_BSWModuleList

[13]  Specification of Standard Types,
AUTOSAR_SWS_StandardTypes.pdf

3.2  Related standards and norms

Not related.

4  Constraints and assumptions

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
4.1 Limitations

[SPI040] ⌈The SPI Handler/Driver handles only the Master mode.⌋()

[SPI050] ⌈The SPI Handler/Driver only supports full-duplex mode.⌋()

[SPI108] ⌈The LEVEL 2 SPI Handler/Driver is specified for microcontrollers that have
to provide, at least, two SPI busses using separated hardware units. Otherwise, us-
ing this level of functionality does not make sense.⌋()

4.2 Applicability to car domains

No restrictions.

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
5  Dependencies to other modules

[SPI239]  ⌈SPI peripherals may depend on the system clock, prescaler(s) and PLL.
Thus, changes of the system clock (e.g. PLL on  PLL off) may also affect the clock
settings of the SPI hardware. ⌋()

[SPI244]  ⌈The SPI Handler/Driver module does not take care of setting the registers
which configure the clock, prescaler(s) and PLL in its init function. This has to be
done by the MCU module [9].⌋()

[SPI342]    ⌈Depending on microcontrollers, the SPI peripheral could share registers
with other peripherals. In this typical case, the SPI Handler/Driver has a relationship
with MCU module [9] for initialising and de-initialising those registers.⌋()

[SPI343]  ⌈If Chip Selects are done using microcontroller pins the SPI Handler/Driver
has a relationship with PORT module [10]. In this case, this specification assumes
that these microcontroller pins are directly accessed by the SPI Handler/Driver mod-
ule without using APIs of DIO module.
Anyhow, the SPI depends on ECU hardware design and for that reason it may de-
pend on other modules.⌋()

5.1  File structure

5.1.1  Code file structure

[SPI095]  ⌈The code file structure shall not be defined within this specification com-
pletely.⌋(BSW00380, BSW00419, BSW158)

[SPI277]  ⌈The code-file structure shall include the file named Spi_Lcfg.c – for link
time and Spi_PBcfg.c – for post build time configurable parameters.⌋()

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
5.1.2  Header file structure

[SPI092]  ⌈The SPI module shall adhere to the following include file structure: Spi.c
shall include Spi.h, MemMap.h, Det.h and SchM_Spi.h.

⌋(BSW00412, BSW00415, BSW00435, BSW00436)

[SPI272]  ⌈Spi.h shall include Std_Types.h.⌋()

[SPI273]  ⌈Spi.h shall include Spi_Cfg.h.⌋()

[SPI274]  ⌈Spi_Xcfg.c shall include Spi.h.⌋()

[SPI275]  ⌈Spi_Xcfg.c shall include MemMap.h.⌋()

[SPI276]  ⌈Spi_Irq.c file could exist depending upon implementation and also it could
or not include Spi.h.⌋()

[SPI158]  ⌈The SPI module shall optionally include the Dem.h  file if any production
error will be issued by the implemetation. By this inclusion the APIs to report errors
as well as the required Event Id symbols are included.⌋(BSW00384)

[SPI159]  ⌈The DEM configuration tool shall assign ECU dependent values to the
Event Id symbols and publish the symbols in Dem_IntErrId.h.⌋(BSW00384)
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3

The names of the Event Id symbols which are provided by XML to the DEM configu-
ration tool are specified in this document.

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
6 Requirements traceability

Requirement
Satisfied by
-
SPI292
-
SPI160
-
SPI244
-
SPI164
-
SPI255
-
SPI137
-
SPI332
-
SPI080
-
SPI310
-
SPI308
-
SPI361
-
SPI349
-
SPI316
-
SPI309
-
SPI249
-
SPI154
-
SPI151
-
SPI161
-
SPI088
-
SPI307
-
SPI299
-
SPI243
-
SPI171
-
SPI293
-
SPI112
-
SPI183
-
SPI175
-
SPI236
-
SPI287
-
SPI186
-
SPI267
-
SPI256
-
SPI040
-
SPI343
-
SPI170
-
SPI275
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
-
SPI185
-
SPI341
-
SPI117
-
SPI143
-
SPI030
-
SPI363
-
SPI297
-
SPI037
-
SPI326
-
SPI131
-
SPI302
-
SPI188
-
SPI129
-
SPI322
-
SPI036
-
SPI368
-
SPI269
-
SPI023
-
SPI270
-
SPI140
-
SPI239
-
SPI152
-
SPI184
-
SPI176
-
SPI311
-
SPI286
-
SPI246
-
SPI328
-
SPI086
-
SPI108
-
SPI300
-
SPI150
-
SPI342
-
SPI156
-
SPI344
-
SPI364
-
SPI260
-
SPI133
-
SPI289
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
-
SPI278
-
SPI128
-
SPI146
-
SPI195
-
SPI354
-
SPI116
-
SPI301
-
SPI238
-
SPI313
-
SPI280
-
SPI303
-
SPI182
-
SPI028
-
SPI258
-
SPI370
-
SPI330
-
SPI145
-
SPI265
-
SPI336
-
SPI325
-
SPI350
-
SPI317
-
SPI242
-
SPI130
-
SPI254
-
SPI187
-
SPI345
-
SPI371
-
SPI366
-
SPI177
-
SPI331
-
SPI281
-
SPI272
-
SPI123
-
SPI240
-
SPI166
-
SPI320
-
SPI126
-
SPI049
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
-
SPI295
-
SPI355
-
SPI157
-
SPI347
-
SPI196
-
SPI334
-
SPI277
-
SPI082
-
SPI012
-
SPI179
-
SPI266
-
SPI285
-
SPI169
-
SPI359
-
SPI138
-
SPI189
-
SPI027
-
SPI358
-
SPI081
-
SPI172
-
SPI141
-
SPI290
-
SPI114
-
SPI262
-
SPI250
-
SPI264
-
SPI288
-
SPI155
-
SPI362
-
SPI136
-
SPI360
-
SPI261
-
SPI321
-
SPI351
-
SPI282
-
SPI304
-
SPI338
-
SPI273
-
SPI144
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
-
SPI305
-
SPI339
-
SPI233
-
SPI142
-
SPI274
-
SPI252
-
SPI356
-
SPI296
-
SPI011
-
SPI017
-
SPI268
-
SPI263
-
SPI168
-
SPI271
-
SPI365
-
SPI051
-
SPI115
-
SPI251
-
SPI335
-
SPI367
-
SPI192
-
SPI327
-
SPI346
-
SPI333
-
SPI024
-
SPI173
-
SPI191
-
SPI348
-
SPI194
-
SPI353
-
SPI324
-
SPI276
-
SPI329
-
SPI291
-
SPI245
-
SPI193
-
SPI085
-
SPI241
-
SPI237
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
-
SPI352
-
SPI314
-
SPI253
-
SPI178
-
SPI298
-
SPI257
-
SPI259
-
SPI337
-
SPI165
-
SPI318
-
SPI294
-
SPI167
-
SPI319
-
SPI323
-
SPI149
-
SPI181
-
SPI312
-
SPI306
-
SPI279
-
SPI180
-
SPI139
-
SPI340
-
SPI357
-
SPI315
-
SPI283
-
SPI135
-
SPI050
BSW00301
SPI999
BSW00302
SPI999
BSW00306
SPI999
BSW00307
SPI999
BSW00308
SPI999
BSW00309
SPI999
BSW00312
SPI999
BSW00323
SPI029, SPI060, SPI031, SPI032
BSW00324
SPI999
BSW00325
SPI999
BSW00326
SPI999
BSW00327
SPI004
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
BSW00328
SPI999
BSW00330
SPI999
BSW00331
SPI999
BSW00334
SPI999
BSW00335
SPI019, SPI061, SPI062
BSW00336
SPI022, SPI021
BSW00337
SPI098, SPI097, SPI007, SPI004
BSW00338
SPI100
BSW00339
SPI099, SPI006
BSW00341
SPI999
BSW00342
SPI999
BSW00343
SPI999
BSW00344
SPI009
BSW00347
SPI999
BSW00350
SPI005
BSW00355
SPI999
BSW00357
SPI174
BSW00359
SPI048
BSW00360
SPI048
BSW00369
SPI029, SPI006, SPI005, SPI048
BSW00375
SPI999
BSW00380
SPI095
BSW00384
SPI159, SPI158
BSW00385
SPI007, SPI004
BSW00386
SPI029, SPI005
BSW00399
SPI999
BSW004
SPI069, SPI369
BSW00400
SPI999
BSW00401
SPI999
BSW00405
SPI013, SPI008
BSW00406
SPI015, SPI046
BSW00407
SPI102, SPI101
BSW00409
SPI097
BSW00411
SPI102
BSW00412
SPI092
BSW00413
SPI999
BSW00415
SPI092
BSW00416
SPI999
BSW00417
SPI999
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
BSW00419
SPI095
BSW00420
SPI999
BSW00421
SPI099, SPI006
BSW00422
SPI999
BSW00423
SPI999
BSW00424
SPI999
BSW00426
SPI999
BSW00427
SPI999
BSW00428
SPI999
BSW00429
SPI999
BSW00431
SPI999
BSW00432
SPI999
BSW00433
SPI999
BSW00434
SPI999
BSW00435
SPI092
BSW00436
SPI092
BSW005
SPI999
BSW006
SPI999
BSW009
SPI999
BSW010
SPI999
BSW101
SPI013, SPI015
BSW12024
SPI008, SPI063
BSW12025
SPI009, SPI008, SPI052, SPI053, SPI063
BSW12026
SPI009
BSW12032
SPI009, SPI066
BSW12033
SPI009, SPI066
BSW12037
SPI014, SPI124, SPI127, SPI059
BSW12056
SPI009, SPI054, SPI064, SPI044
BSW12057
SPI013, SPI015
BSW12063
SPI999
BSW12064
SPI025, SPI021
BSW12067
SPI999
BSW12068
SPI999
BSW12069
SPI999
BSW12075
SPI053
BSW12077
SPI999
BSW12078
SPI999
BSW12092
SPI999
BSW12093
SPI010, SPI009, SPI034, SPI041
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
BSW12094
SPI009, SPI066
BSW12099
SPI016, SPI020, SPI162, SPI163
BSW12101
SPI018, SPI020, SPI162, SPI163
BSW12103
SPI020, SPI058, SPI053, SPI067, SPI162, SPI163
BSW12104
SPI025, SPI026, SPI039
BSW12108
SPI120, SPI118, SPI119, SPI057
BSW12125
SPI013, SPI009, SPI008
BSW12129
SPI999
BSW12150
SPI093, SPI009, SPI064
BSW12152
SPI016, SPI134
BSW12153
SPI018, SPI134
BSW12154
SPI134
BSW12163
SPI022, SPI021
BSW12170
SPI084, SPI042
BSW12179
SPI003, SPI009, SPI064, SPI065
BSW12180
SPI003, SPI065
BSW12181
SPI055, SPI065
BSW12197
SPI063
BSW12198
SPI077, SPI053
BSW12199
SPI003, SPI064, SPI065
BSW12200
SPI077, SPI003, SPI053, SPI065, SPI035
BSW12201
SPI077, SPI003, SPI065, SPI035
BSW12202
SPI078, SPI053
BSW12253
SPI078, SPI052
BSW12256
SPI009, SPI008, SPI034
BSW12257
SPI010, SPI009, SPI008, SPI066, SPI065, SPI063, SPI034
BSW12258
SPI003, SPI009, SPI065
BSW12259
SPI009
BSW12260
SPI093, SPI014, SPI002, SPI009, SPI059, SPI064
BSW12261
SPI003, SPI053, SPI065
BSW12262
SPI078, SPI003, SPI053, SPI065
BSW12265
SPI999
BSW12267
SPI999
BSW13400
SPI110
BSW13401
SPI109, SPI121, SPI122, SPI125, SPI111
BSW157
SPI075, SPI073, SPI026, SPI057, SPI071, SPI038, SPI039, SPI042
BSW158
SPI095
BSW161
SPI999
BSW164
SPI999
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V3.2.0
R4.0 Rev 3
BSW168
SPI999
BSW170
SPI999
BSW172
SPI999

Document: AUTOSAR requirements on Basic Software, general

Requirement
Satisfied by
[BSW003] Version identification
SPI068 SPI089
[BSW004] Version check
SPI369
[BSW00300] Module naming convention
Chapter 5.1
[BSW00301] Limit imported information
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW00302] Limit exported information
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW00304] AUTOSAR integer data types
Chapters 5.1.2, 8.2, 10.2 and 10.3
[BSW00305] Self-defined data types naming con-
Chapter 8.2
vention
[BSW00306] Avoid direct use of compiler and
Not applicable
platform specific keywords
(requirement on implementation, not on specifica-
tion)
[BSW00307] Global variables naming convention   Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW00308] Definition of global data
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW00309] Global data with read-only constraint   Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW00310] API naming convention
Chapter 8.3
[BSW00312] Shared code shall be reentrant
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW00314] Separation of interrupt frames and
Chapter 5.1
service routines
[BSW00318] Format of module version numbers
SPI068
[BSW00321] Enumeration of module version
SPI068
numbers
[BSW00323] API parameter checking
SPI029 SPI031 SPI032 SPI060
[BSW00324] Do not use HIS I/O Library
Not applicable
(requirement on AUTOSAR architecture, not a
single module)
[BSW00325] Runtime of interrupt service routines   Not applicable
(Cannot be detailed at this point of time, because
this depends on module implementation.)
[BSW00326] Transition from ISRs to OS tasks
Not applicable
(Cannot be detailed at this point of time, because
this depends on module implementation.)
[BSW00327] Error values naming convention
SPI004
[BSW00328] Avoid duplication of code
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW00329] Avoidance of generic interfaces
Chapter 8
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
[BSW00330] Usage of macros / inline functions
Not applicable
instead of functions
(requirement on implementation, not on specifica-
tion)
[BSW00331] Separation of error and status values   Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW00333] Documentation of callback function
Chapters 8.6.3.1 and 8.6.3.2
context
[BSW00334] Provision of XML file
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW00335] Status values naming convention
SPI061 SPI062 SPI019
[BSW00336] Shutdown interface
SPI021 SPI022
[BSW00337] Classification of errors
SPI004 SPI007 SPI097 SPI098
[BSW00338] Reporting of development errors
SPI100
[BSW00339] Reporting of production relevant
SPI006 SPI099 and Chapter 8.6.2
error status
[BSW00341] Microcontroller compatibility docu-
Not applicable
mentation
(requirement on implementation, not on specifica-
tion)
[BSW00342] Usage of source code and object
Not applicable
code
(requirement on implementation, not on specifica-
tion)
[BSW00343] Specification and configuration of
Not applicable
time
(requirement on implementation, not on specifica-
tion)
[BSW00344] Reference to link-time configuration
SPI009 SPI091
[BSW00345] Pre-compile-time configuration
SPI056
[BSW00347] Naming separation of different in-
Not applicable
stances of BSW drivers
(requirement on implementation, not on specifica-
tion)
[BSW00348] Standard type header
Chapter 8.1
[BSW00350] Development error detection
SPI005 SPI103 SPI056
keywords
[BSW00353] Platform specific type header
Chapter 8.1
[BSW00355] Do not redefine AUTOSAR integer
Not applicable
data types
(requirement on implementation, not on specifica-
tion)
[BSW00357] Standard API return type
SPI174 Chapter 8.3
[BSW00358] Return type of init() functions
Chapter 8.3.1
[BSW00359] Return type of callback functions
SPI048
[BSW00360] Parameters of callback functions
SPI048
[BSW00361] Compiler specific language exten-
Chapter 5.1.2
sion header
[BSW00369] Do not return development error
SPI005 SPI029 SPI048 SPI006
codes via API
[BSW00370] Separation of callback interface from  Chapter 8.4
API
[BSW00371] Do not pass function pointers via API   Chapters 8.6.3, 10.2
[BSW00373] Main processing function naming
Chapter 8.5
convention
[BSW00374] Module vendor identification
SPI068 SPI089
[BSW00375] Notification of wake-up reason
Not applicable.
(Only master mode is supported. Master mode
does not provide wake up events.)
[BSW00376] Return type and parameters of main  Chapter 8.5
processing functions
[BSW00377] Module specific API return types
Chapters 0, 8.2.3 and 8.2.4
[BSW00378] AUTOSAR boolean type
SPI105
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
[BSW00379] Module identification
SPI068 SPI089
[BSW00380] Separate C-Files for configuration
SPI095
parameters
[BSW00381] Separate configuration header file
SPI103
for pre-compile time parameters
[BSW00383] List dependencies of configuration
Chapter 5
files
[BSW00384] List dependencies to other modules   Chapter 5, SPI158 SPI159
[BSW00385] List possible error notifications
SPI004 SPI007
[BSW00386] Configuration for detecting an error
SPI005 SPI029
[BSW00387] Specify the configuration class of
Chapters 8.4 and 8.6.3
callback function
[BSW00388] Introduce containers
SPI103 SPI091 SPI104 SPI105 SPI106
[BSW00389] Containers shall have names
SPI103 SPI091 SPI104 SPI105 SPI106
[BSW00390] Parameter content shall be unique
SPI103 SPI091 SPI104 SPI105 SPI106 SPI068
within the module
[BSW00391] Parameter shall have unique names   SPI103 SPI091 SPI104 SPI105 SPI106 SPI068
[BSW00392] Parameters shall have a type
SPI103 SPI091 SPI104 SPI105 SPI106
[BSW00393] Parameters shall have a range
SPI103 SPI091 SPI104 SPI105 SPI106
[BSW00394] Specify the scope of the parameters   SPI103 SPI091 SPI104 SPI105 SPI106
[BSW00395] List the required parameters (per
SPI103 SPI091 SPI104 SPI105 SPI106
parameter)
[BSW00396] Configuration classes
SPI056 SPI076 SPI103 SPI091 SPI104 SPI105
SPI106
[BSW00397] Pre-compile-time parameters
SPI056 SPI103
[BSW00398] Link-time parameters
SPI076 SPI091 SPI104 SPI105 SPI106
[BSW00399] Loadable Post-build time parameters   Non applicable
(Cannot be detailed at this point of time, because
this depends on ECU integration.)
[BSW004] Version check
SPI069
[BSW00400] Selectable Post-build time parame-
Non applicable
ters
(Cannot be detailed at this point of time, because
this depends on ECU integration.)
[BSW00401] Documentation of multiple instances  Not applicable
of configuration parameters
(requirement on implementation, not on specifica-
tion)
[BSW00402] Published information
SPI068 SPI089
[BSW00404] Reference to post build time
SPI148
configuration
[BSW00405] Reference to multiple configuration
SPI008 SPI013 SPI076 SPI148
sets
[BSW00406] Check module initialization
SPI015 SPI046
[BSW00407] Function to read out published pa-
SPI101 SPI102
rameters
[BSW00408] Configuration parameter naming
Chapter 10.2
convention
[BSW00409] Header files for production code
SPI097
error IDs
[BSW00410] Compiler switches shall have de-
SPI103
fined values
[BSW00411] Get version info keyword
SPI102
[BSW00412] Separate H-File for configuration
SPI092
parameters
[BSW00413] Accessing instances of BSW mod-
Not applicable
ules
(requirement on implementation, not on specifica-
tion)
[BSW00414] Parameter of init function
Chapter 8.3.1
[BSW00415] User dependent include files
SPI092
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
[BSW00416] Sequence of Initialization
Not applicable
(this is a general software integration requirement)
[BSW00417] Reporting of Error Events by Non-
Not applicable
Basic Software
(applies only for non BSW modules)
[BSW00419] Separate C-Files for pre-compile
SPI095
time configuration parameters
[BSW00420] Production relevant error event rate
Not applicable
detection
(applies only for DEM)
[BSW00421] Reporting of production relevant
SPI006 SPI099 and Chapter 8.6.2
error events
[BSW00422] Debouncing of production relevant
Not applicable
error status
(applies only for DEM)
[BSW00423] Usage of SW-C template to describe  Not applicable
BSW modules with AUTOSAR Interfaces
(EEPROM driver has no Autosar Interface)
[BSW00424] BSW main processing function task
Not applicable
allocation
(this is a general software integration requirement)
[BSW00425] Trigger conditions for schedulable
Chapter 8.5
objects
[BSW00426] Exclusive areas in BSW modules
Not applicable
(Cannot be detailed at this point of time, because
this depends on module implementation.)
[BSW00427] ISR description for BSW modules
Not applicable
(Cannot be detailed at this point of time, because
this depends on module implementation.)
[BSW00428] Execution order dependencies of
Not applicable
main processing functions
(Cannot be detailed at this point of time, because
this depends on module implementation.)
[BSW00429] Restricted BSW OS functionality
Not applicable
access
(requirement on implementation, not on specifica-
tion)
[BSW00431] The BSW Scheduler module imple-
Not applicable
ments task bodies
(SPI Handler/Driver Module is not the BSW
Scheduler)
[BSW00432] Modules should have separate main  Not applicable
processing functions for read/receive and
(requirement on implementation, not on specifica-
write/transmit data path
tion)
[BSW00433] Calling of main processing functions   Not applicable
(this is a general software integration requirement)
[BSW00434] The Schedule Module shall provide
Not applicable
an API for exclusive areas
(SPI Handler/Driver Module is not the BSW
Scheduler)
[BSW00435] Module Header File Structure for the  SPI092
Basic Software Scheduler
[BSW00436] Module Header File Structure for the  SPI092
Memory Mapping
[BSW005] No hard coded horizontal interfaces
Not applicable
within MCAL
(requirement on AUTOSAR architecture, not a
single module)
[BSW006] Platform independency
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW007] HIS MISRA C
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW009] Module User Documentation
Not applicable
(requirement on implementation, not on specifica-
tion)
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V3.2.0
R4.0 Rev 3
[BSW010] Memory resource documentation
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW101] Initialization interface
SPI013 SPI015
[BSW158] Separation of configuration from im-
SPI103 SPI091 SPI089 SPI095
plementation
[BSW159] Tool-based configuration
Both static and runtime configuration parameters
are located outside the source code of the mod-
ule. This is the prerequisite for automatic configu-
ration.
[BSW160] Human-readable configuration data
Requirement on configuration methodology and
tools
[BSW161] Microcontroller abstraction
Not applicable
(requirement on AUTOSAR architecture, not a
single module)
[BSW162] ECU layout abstraction
Not applicable
(requirement on AUTOSAR architecture, not a
single module)
[BSW164] Implementation of interrupt service
Not applicable
routines
(Cannot be detailed at this point of time, because
this depends on module implementation.)
[BSW167] Static configuration checking
Requirement on configuration tool
[BSW168] Diagnostic Interface of SW
Not applicable (no use case)
components
[BSW170] Data for reconfiguration of AUTOSAR
Not applicable
SW-Components
(requirement on SW Component)
[BSW171] Configurability of optional functionality
Conflicts partly with SPAL requirement
[BSW12263] Configuration after compile time.
[BSW172] Compatibility and documentation of
Not applicable
scheduling strategy
(requirement on implementation, not on specifica-
tion)

Document: AUTOSAR requirements on Basic Software, cluster SPAL

Requirement
Satisfied by
[BSW12263] Object code compatible
SPI076
configuration concept
[BSW12056] Configuration of notification mecha-
SPI009 SPI064 SPI044 SPI054
nisms
[BSW12267] Configuration of wake-up sources
Not applicable. (
Only master mode is supported. Master mode
does not provide wake up events.)
[BSW12057] Driver module initialization
SPI013 SPI015
[BSW12125] Initialization of hardware resources
SPI013 SPI008 SPI009
[BSW12163] Driver module deinitialization
SPI021 SPI022
[BSW12461] Responsibility for register
See chapter 5
initialization
[BSW12462] Provide settings for register
Cannot be detailed at this point of time, because
initialization
this depends on SPI hardware and implementa-
tion.
[BSW12463] Combine and forward settings for
Cannot be detailed at this point of time (see
register initialization
above)
[BSW12068] MCAL initialization sequence
Not applicable
(this is a general software integration requirement)
[BSW12069] Wake-up notification of ECU State
Not applicable
Manager
(the SPI does not cause any wake-ups)
[BSW157] Notification mechanisms of drivers and  SPI026 SPI038 SPI039 SPI042 SPI057 SPI071
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
handlers
SPI073 SPI075
[BSW12169] Control of operation mode
Chapter 9.2
[BSW12063] Raw value mode
Not applicable (no I/O functionality)
[BSW12075] Use of application buffers
SPI053
[BSW12129] Resetting of interrupt flags
No Applicable to the Handler API but shall be
define for the Driver API.
[BSW12064] Change of operation mode during
Chapter 9.2, SPI025 SPI021
running operation
[BSW12448] Behavior after development error
Chapters 7.5.1 and 7.5.2
detection
[BSW12067] Setting of wake-up conditions
Not applicable (the SPI resource does not cause
any wake-ups)
[BSW12077] Non-blocking implementation
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW12078] Runtime and memory efficiency
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW12092] Access to drivers
Not applicable
(requirement on implementation, not on specifica-
tion)
[BSW12265] Configuration data shall be kept
Not applicable
constant
(requirement on implementation, not on specifica-
tion)
[BSW12264] Specification of configuration items
Chapter 10.2

Document: AUTOSAR requirements on Basic Software, SPI Handler/Driver

Requirement
Satisfied by
[BSW12093] SPI Channel support
SPI009 SPI010 SPI034 SPI041
[BSW12094] Chip select
SPI009 SPI066
[BSW12256] Support of all Controller Peripherals
SPI008 SPI009 SPI034
[BSW12257] Support of chained HW devices
SPI008 SPI063 SPI009 SPI010 SPI034 SPI065
SPI066
[BSW13400] Scalable functionality
SPI110 Chapters 7.2.1 and 7.2.4
[BSW12025] Configuration of SPI general SW
SPI008 SPI009 SPI063 SPI052 SPI053
and HW properties
[BSW12179] SPI Channel linkage
SPI009 SPI003 SPI064 SPI065
[BSW12026] Assignment of SPI Channel to SPI
SPI009
HW Unit
[BSW12197] Definition of data width
SPI063
[BSW13401] Statically configurable functionali-
SPI109 SPI111 SPI121 SPI122 SPI125
ties
[BSW12258] Data shall be accessible device
SPI003 SPI065 SPI009
individually
[BSW12259] Support of different timing and HW
SPI009
parameters
[BSW12260] Support of different priorities of
SPI009 SPI064 SPI002 SPI014 SPI059 SPI093
sequences
[BSW12180] Handling of single SPI channels
SPI003 SPI065
[BSW12181] Handling of linked SPI channels
SPI065 SPI055
[BSW12032] Chip select mode – normal mode
SPI009 SPI066
[BSW12033] Chip select mode – hold mode
SPI009 SPI066
[BSW12198] Transfer one short data sequence
SPI053 SPI077
with variable data
[BSW12253] Transfer one short data sequence
SPI052 SPI078
with constant data
[BSW12199] Transfer data to several devices in
SPI065 SPI003 SPI064
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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
one Sequence
[BSW12200] Read large data sequences from
SPI053 SPI065 SPI003 SPI035 SPI077
one slave device using dummy send data
[BSW12261] Read large data sequences from
SPI053 SPI065 SPI003
one slave device using variable send data
[BSW12201] Read large data sequences from
SPI065 SPI003 SPI035 SPI077
several slave devices using dummy send data
[BSW12262] Read large data sequences from
SPI053 SPI065 SPI003 SPI078
several slave devices using variable send data
[BSW12202] Support of variable data length
SPI053 SPI078
[BSW12024] Configuration of SPI HW Unit
SPI008 SPI063
[BSW12150] Configuration of SPI asynchronous
SPI009 SPI064 SPI093
SW and HW properties
[BSW12108] Callback notification
Chapter 8.6.3 SPI057 SPI118 SPI119 SPI120
[BSW12099] Asynchronous Read Functionality
SPI020 SPI162 SPI163 SPI016 SPI020
[BSW12101] Asynchronous Write Functionality
SPI020 SPI162 SPI163 SPI018 SPI020
[BSW12103] Asynchronous Read-Write Func-
SPI020 SPI053 SPI058 SPI067
tionality
[BSW12037] Job Management Strategy – Priority  Chapter 7.2.3, 7.2.4 and 7.3 SPI014 SPI059
controlled
SPI124 SPI127
[BSW12104] SPI status functionality
SPI025 SPI026 SPI039
[BSW12170] Concurrent Channel access
SPI042 SPI084
[BSW12152] Synchronous Read Function
Chapter 7.2.2 SPI134 SPI016
[BSW12153] Synchronous Write Function
Chapter 7.2.2 SPI134 SPI018
[BSW12154] Synchronous Write-Read Function
Chapter 7.2.2 SPI134
[BSW12151] Job Management Strategy – Order
Chapter 7.2.2
of requests

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
7  Functional specification

The SPI (Serial Peripheral Interface) has a 4-wire synchronous serial interface. Data
communication is enabled with a Chip select wire (CS). Data is transmitted with a 3-
wire interface consisting of wires for serial data output (MOSI), serial data input (MI-
SO) and serial clock (CLOCK).

7.1  Overall view of functionalities and features

This specification is based on previous specification experiences and also based on
predominant identified use cases. The intention of this section is to summarize how
the scalability of this monolithic SPI Handler/Driver allows getting a simple software
module that fits simple needs up to a smart software module that fits enhanced
needs.
Scalability of funct
unc ionali
onal ties
SPI API standardized
F
F
eat
eat
#1
…
#k
F
F
eat
eat
ur
ur
F
F
e
e
ur
…
ur
eat
eat
HAL
e #
e #m
ur
…
ur
1
e #
e #
1
n
SPI Hand
I Han ler/Driver
MCAL
µC
Simple SP
e S I
Queued SPI
DMA SPI

This document specifies the following 3 Levels of Scalable Functionality for the SPI
Handler/Driver:
•  LEVEL 0, Simple Synchronous SPI Handler/Driver:  the communication is
based on synchronous handling with a FIFO policy to handle multiple access-
es. Buffer usage is configurable to optimize and/or to take advantage of HW
capabilities.
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•  LEVEL 1, Basic Asynchronous SPI Handler/Driver: the communication is
based on asynchronous behavior and with a Priority policy to handle multiple
accesses. Buffer usage is configurable as for “Simple Synchronous” level.
•  LEVEL 2, Enhanced (Synchronous/Asynchronous) SPI Handler/Driver:
the communication is based on asynchronous behavior or synchronous han-
dling, using either interrupts or polling mechanism selectable during execution
time and with a Priority policy to handle multiple accesses. Buffer usage is
configurable as for other levels.

[SPI109]  ⌈The SPI Handler/Driver’s level of scalable functionality shall always be
statically configurable, i.e. configured at pre-compile time to allow the best source
code optimisation.⌋(BSW13401)

[SPI110] ⌈The SpiLevelDelivered parameter shall be configured with one of the
3 authorized values according to the described levels (0, 1 or 2) to allow the selection
of the SPI Handler/Driver’s level of scalable functionality.⌋(BSW13400)

To improve the scalability, each level has optional features which are configurable
(ON / OFF) or selectable. These are described in detail in the dedicated chapters.

7.2  General behaviour

This chapter, on the one hand, introduces common behavior and configuration for all
levels. On the other, it specifies the behavior of each level and also the allowed op-
tional features.

[SPI041]  ⌈The SPI Handler/Driver interface configuration shall be based on Chan-
nels, Jobs and Sequences as defined in this document (see chapter 2).⌋(BSW12093)

[SPI034]    ⌈The SPI Handler/Driver shall support one or more  Channels, Jobs and
Sequences to drive all kind of SPI compatible HW devices.⌋(BSW12093, BSW12256,
BSW12257)

[SPI255]    ⌈Data transmissions shall be done according to Channels, Jobs and Se-
quences configuration parameters.⌋()

[SPI066]  ⌈The Chip Select (CS) is attached to the Job definition.⌋(BSW12094,
BSW12257, BSW12032, BSW12033)

[SPI263]  ⌈Chip Select shall be handled during Job transmission and shall be re-
leased at the end of it. This Chip Select handling shall be done according to the Job
configuration parameters.⌋()
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[SPI370]  ⌈It shall be possible to define if the Chip Select handling is managed au-
tonomously by the HW peripheral, without explicit chip select control by the driver, or
the SPI driver shall drive the chip select lines explicitly as DIO (see SPI212_Conf).⌋()

Example of CS handling:  Set the CS active at the beginning of Job transmission;
maintain it until the end of transmission of all Channels belonging to this Job after-
wards set the CS inactive.

A Channel is defined one time but it could belong to several Jobs according to the
user needs and this software specification.

[SPI065]    ⌈A Job shall contain at least one Channel.⌋(BSW12257,  BSW12179,
BSW12258,  BSW12180, BSW12181, BSW12199,  BSW12200, BSW12261,
BSW12201, BSW12262)

[SPI368]  ⌈Each Channel shall have an associated index which is used for specifying
the order of the Channel within the Job.⌋()

[SPI262]  ⌈If a Job contains more than one Channel, all Channels contained have the
same Job properties during transmission and shall be linked together statically.⌋()

A Job is defined one time but it could belong to several Sequences according to the
user needs and this software specification.

[SPI003]    ⌈A Sequence shall contain at least one Job.⌋(BSW12179,  BSW12258,
BSW12180, BSW12199, BSW12200, BSW12261, BSW12201, BSW12262)

[SPI236]  ⌈If it contains more than one, all Jobs contained have the same Sequence
properties during transmission and shall be linked together statically.⌋()

A Channel used for a transmission should have its parameters configured but it is
allowed to pass Null pointers as source and destination pointers to generate a dum-
my transmission (See also [SPI028] & [SPI030]).

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
Sequence a
linkage
Job n
Job m
Channel x
Channel y
Channel z
CLOCK
MOSI
D
D
D
D
D
D D
D
D
D
D
D
D
D
D
D
MISO
D
D
D
D
D
D D
D
D
D
D
D
D
D
D
D
CSn
CSm
...
CSo
l
s
ng
al
i
s
di
ing
t
I c
v
x
n i
or
done
P
ed by
s
s
ei
ed
c
i
ed by
A
ob
ithout
ed
trat
j
he bus
ity
trat
ion of
s
e a i
ia
v
bi
ranc
hannel
eas
the nex
eas
of
ed w
bi
el
ing ac
ior
el
is
ar
C
v
ing t
r
ar
r
m
ed
s
the t
ei
s
s
s
i
hed,
i
a of
s
i
i
tiat
eas
hedul
ob pr
equenc
ter
hannel
c
trans
S
ini
bus
job n
af
dat
fini
C
tranc
rel
bus
s
to j
bus
job m
bus

Channel data may differ from the hardware handled and user (client application) giv-
en. On the client side the data is handled in 8, 16 or 32bits mode (see chapter 8.2.5).
On the microcontroller side, the hardware may handle between 1 and 32bits or may
handle a fixed value (8 or 16bits) and this width is configurable for each Channel (see
SpiDataWidth).

[SPI149]    ⌈The SPI Handler/Driver shall take care of the differences between the
width of channel data handled by the user and those handled by the hardware.⌋()

[SPI289]  ⌈If width of channel data handled by the user and handled by the hardware
is exactly the same (8 or 16 or 32 bits), the SPI Handler/Driver can send and receive
data without any bit changes straightforward.⌋()

[SPI290]  ⌈If width of channel data handled by the hardware is superior to data width
handled by the user, means that the data transmitted through the SPI Handler/Driver
shall send the lower part extended with zero. Receive the lower part, ignoring the
upper part.⌋()

[SPI291]    ⌈If width of channel data handled by the hardware inferior to data width
handled by the user means the data transmitted through the SPI Handler/Driver shall
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be according to the memory alignment separate the data as two part and send and
receive one by one.⌋()

This ensures that the user always gets the same interface.

7.2.1  Common configurable feature: Allowed Channel Buffers

In order to allow taking advantages of all microcontroller capabilities but also to allow
sending/receiving of data to/from a dedicated memory location, all levels have an
optional feature with respect to the location of Channel Buffers.

Hence, two main kinds of channel buffering can be used by configuration:
•  Internally buffered Channels (IB): The buffer to transmit/receive data is provid-
ed by the Handler/Driver.
•  Externally buffered Channels (EB): The buffer to transmit/receive is provided
by the user (statically and/or dynamically).

Both channel buffering methods may be used depending on the 3 use cases de-
scribed below:
•  Usage 0: the SPI Handler/Driver manages only Internal Buffers.
•  Usage 1: the SPI Handler/Driver manages only External Buffers.
•  Usage 2: the SPI Handler/Driver manages both buffers types.

[SPI111]  ⌈The SpiChannelBuffersAllowed parameter shall be configured with one of
the 3 authorized values (0, 1 or 2) according to the described usage.⌋(BSW13401)

[SPI279]    ⌈The SpiChannelBuffersAllowed parameter shall be configured to select
which Channel Buffers the SPI Handler/Driver manages.⌋()

7.2.1.1  Behaviour of IB channels

The intention of Internal Buffer channels is to take advantage of microcontrollers in-
cluding this feature by hardware. Otherwise, this feature should be simulated by
software.

[SPI052] ⌈For the IB Channels, the Handler/Driver shall provide the buffering but it is
not able to take care of the consistency of the data in the buffer during transmission.
The size of the Channel buffer is fixed.⌋(BSW12025, BSW12253)

[SPI049] ⌈The channel data received shall be stored in 1 entry deep internal buffers
by channel. The SPI Handler/Driver shall not take care of the overwriting of these
“receive” buffers by another transmission on the same channel.⌋()

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[SPI051]  ⌈The channel data to be transmitted shall be copied in 1 entry deep inter-
nal buffers by channel.⌋()

[SPI257]  ⌈The SPI Handler/Driver is not able to prevent the overwriting of these
“transmit” buffers by users during transmissions.⌋()

7.2.1.2  Behaviour of EB channels

The intention of External Buffer channels is to reuse existing buffers that are located
outside. That means the SPI Handler/Driver does not monitor them.

[SPI053] ⌈For EB Channels the application shall provide the buffering and shall take
care of the consistency of the data in the buffer during transmission.⌋(BSW12075,
BSW12025, BSW12198, BSW12200, BSW12261, BSW12262, BSW12202,
BSW12103)

[SPI112]  ⌈The size of the Channel buffer is either fixed or variable. A maximum size
for the Channel buffer shall be defined by the configuration.⌋()

[SPI280]    ⌈The buffer provided by the application for the SPI Handler Driver may
have a different size.⌋()

7.2.1.3  Buffering channel usage

The following table provides information about the Channel characteristics:

IB Channels
It provides…
•  A more abstracted concept (buffering mechanisms are hidden)
•  Actual and future optimal implementation taken profit of HW buffer facili-
ties (Given size of 256 bytes covers nowadays requirements).
Suggested
•  Daisy-chain implementation.
use …
•  Small data transfer devices (up to 10 Bytes).
EB Channels
It provides…
•  Efficient mechanism to support large stream communication.
•  Send constant data out of ROM tables and spare RAM size.
•  Send various data tables each for a different device (highly complex
ASICS with several integrated peripheral devices, also mixed signal
types, could exceed IB HW buffer size)
Suggested use
•  Large streams communication.
…
•  EEPROM communication.
•  Control of complex HW Chips .

7.2.2  LEVEL 0, Simple Synchronous behaviour

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The intention of this functionality level is to provide a Handler/Driver with a reduced
set of services to handle only simple synchronous transmissions. This is often the
case for ECU including simple SPI networks but also for ECU using high speed ex-
ternal devices.

A simple synchronous transmission means that the function calling the transmission
service is blocked during the ongoing transmission until the transmition is finished.

[SPI160]    ⌈The LEVEL 0 SPI Handler/Driver shall offer a synchronous transfer ser-
vice for SPI busses.⌋()

[SPI161] ⌈ For an SPI Handler/Driver operating in LEVEL 0, when there is no on go-
ing Sequence transmission, the SPI Handler/Driver shall be in the idle state
SPI_IDLE.⌋()

[SPI294]  ⌈This monolithic SPI Handler/Driver is able to handle one to n SPI buses
according to the microcontroller used.⌋()

Then SPI buses are assigned to Jobs and not to Sequences. Consequently, Jobs, on
different SPI buses, could belong to the same Sequence. Therefore:

[SPI114]
⌈The LEVEL 0 SPI Handler/Driver shall  accept concurrent
Spi_SyncTransmit(),  if the sequences to be transmitted use different bus and pa-
rameter  SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT  is enabled. This feature
shall be disabled per default. That means during a Sequence on-going transmission,
all requests to transmit another Sequence shall be rejected.⌋()

[SPI115] ⌈The LEVEL 0 SPI Handler/Driver behaviour shall include the common fea-
ture: Allowed Channel Buffers, which is selected.⌋()

[SPI084] ⌈If different Jobs (and consequently also Sequences) have common Chan-
nels, the SPI Handler/Driver’ environment shall ensure that read and/or write func-
tions are not called during transmission.⌋(BSW12170)

Read and write functions can not guarantee the data integrity while Channel data is
being transmitted.

7.2.3  LEVEL 1, Basic Asynchronous behavior

The intention of this functionality level is to provide a Handler/Driver with a reduced
set of services to handle asynchronous transmissions only. This is often the case for
ECU with functions related to SPI networks having different priorities but also for
ECU using low speed external devices.
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An asynchronous transmission means that the user calling the transmission service
is not blocked when the transmission is on-going. Furthermore, the user can be noti-
fied at the end of transmission1.
[SPI162]  ⌈The LEVEL 1 SPI Handler/Driver shall offer an asynchronous transfer
service for SPI buses. An asynchronous transmission means that the user calling the
transmission service is not blocked when the transmission is on going.⌋(BSW12099,
BSW12101, BSW12103)

[SPI295]  ⌈The LEVEL 1 SPI Handler/Driver shall offer an asynchronous transfer
service for SPI buses. Furthermore, the user can be notified at the end of transmis-
sion.⌋()

[SPI163]  ⌈For an SPI Handler/Driver operating in LEVEL 1, when there is no on-
going  Sequence transmission, the SPI Handler/Driver shall be in the idle state
(SPI_IDLE).⌋(BSW12099, BSW12101, BSW12103)

This Handler/Driver will be used by several software modules which may be inde-
pendent from each other and also may belong to different layers. Therefore, priorities
will be assigned to Jobs in order to figure out specific cases of multiple accesses.
These cases usually occur within real time systems based on asynchronous mecha-
nisms.

[SPI002] ⌈Jobs have priorities assigned. Jobs linked in a Sequence shall have same
or de-creasing priorities. That means the first Job shall have the equal priority or the
highest priority of all Jobs within the Sequence.⌋(BSW12260)

[SPI093]  ⌈Priority order of jobs shall be from the lower to the higher value defined,
higher value higher priority (from 0, the lower to 3, the higher, limited to 4 priority lev-
els see [SPI009]).⌋(BSW12260, BSW12150)

With reference to Jobs priorities, this Handler/Driver needs rules to make a decision
in these specific cases of multiple accesses.

[SPI059] ⌈The SPI Handler/Driver scheduling method shall schedule Jobs in order to
send the highest priority Job first.⌋(BSW12260, BSW12037)

This monolithic SPI Handler/Driver is able to handle one to n SPI busses according
to the microcontroller used. But SPI busses are assigned to Jobs and not to Se-
quences. Consequently, Jobs on different SPI buses could belong to the same Se-
quence. Therefore:

1 This basic asynchronous behaviour might be implemented either by using interrupt or by polling
mechanism. This software design choice is not in the scope of this document, but only solution is re-
quired for the LEVEL 1.
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[SPI116]  ⌈The LEVEL 1 SPI Handler/Driver may allow transmitting more than one
Sequence at the same time. That means during a Sequence transmission, all re-
quests to transmit another Sequence shall be evaluated in order to accept to start a
new sequence or to reject it accordingly to the lead Job.⌋()

[SPI117] ⌈The LEVEL 1 SPI Handler/Driver behaviour shall include the common fea-
ture: Allowed Channel Buffers, which is selected, and the configured asynchronous
feature: Interruptible Sequence (see next chapter).⌋()

[SPI267]  ⌈When a hardware error is detected, the SPI Handler/Driver shall stop the
current Sequence, report an error to the DEM as configured and set the state of the
Job to SPI_JOB_FAILED and the state of the Sequence to SPI_SEQ_FAILED.⌋()

[SPI118]    ⌈If Jobs are configured with a specific end notification function,  the SPI
Handler/Driver shall call this notification function at the end of the Job transmis-
sion.⌋(BSW12108)

[SPI281]  ⌈If Sequences are configured with a specific end notification function, the
SPI Handler/Driver shall call this notification function at the end of the Sequence
transmission.⌋()

[SPI119] ⌈When a valid notification function pointer is configured (see [SPI071]), the
SPI Handler/Driver shall call this notification function at the end of a Job transmission
regardless of the result of the Job transmission being either SPI_JOB_FAILED  or
SPI_JOB_OK (rational: avoid deadlocks or endless loops).⌋(BSW12108)

[SPI120] ⌈When a valid notification function pointer is configured (see [SPI073]), the
SPI Handler/Driver shall call this notification function at the end of a Sequence
transmission regardless of the result of the Sequence transmission being either
SPI_SEQ_FAILED,  SPI_SEQ_OK  or  SPI_SEQ_CANCELLED  (rational: avoid dead-
locks or endless loops).⌋(BSW12108)

7.2.4  Asynchronous configurable feature: Interruptible Sequences

In order to allow taking advantages of asynchronous transmission mechanism, level
1 and level 2 of this SPI Handler/Driver have an optional feature with respect to sus-
pending the transmission of Sequences.

Hence two main kinds of sequences can be used by configuration:
•  Non-Interruptible Sequences, every Sequence transmission started is not
suspended by the Handler/Driver until the end of transmission.
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•  Mixed Sequences, according to its configuration, a Sequence transmission
started may be suspended by the Handler/Driver between two of their consec-
utives Jobs.

[SPI121]
⌈The SPI Handler/Driver’s environment shall configure the
SpiInterruptibleSeqAllowed  parameter (ON  /  OFF) in order to select which
kind of Sequences the SPI Handler/Driver manages.⌋(BSW13401)

7.2.4.1  Behavior of Non-Interruptible Sequences

The intention of the Non-Interruptible Sequences feature is to provide a simple soft-
ware module based on a basic asynchronous mechanism, if only non blocking
transmissions should be used.

[SPI122]  ⌈Interruptible Sequences are not allowed within levels 1 and 2 of the
SPI/Handler/Driver when  the  SpiInterruptibleSeqAllowed  parameter is
switched off (i.e. configured with value “OFF”). ⌋(BSW13401)

[SPI123]    ⌈When the SPI Handler/Driver is configured not allowing interruptible Se-
quences, all Sequences declared are considered as Non-Interruptible Sequences2.⌋()

[SPI282]    ⌈When the SPI Handler/Driver is configured not allowing interruptible Se-
quences  their dedicated parameter SpiInterruptibleSequence can be omitted or the
FALSE value should be used as default.⌋()

[SPI124] ⌈According to [SPI116] and [SPI122] requirements, the SPI Handler/Driver
is not allowed to suspend a Sequence transmission already started in favour of an-
other Sequence.⌋(BSW12037)

7.2.4.2  Behavior of Mixed Sequences

The intention of the Mixed Sequences feature is to provide a software module with
specific asynchronous mechanisms, if, for instance, very long Sequences that could
or should be suspended by others with higher priority are used.

[SPI125]  ⌈Interruptible Sequences are allowed within levels 1 and 2 of SPI Han-
dler/Driver  when  the  SpiInterruptibleSeqAllowed  parameter is switched on
(i.e. configured with value “ON”).⌋(BSW13401)

2  The intention of this requirement is not to enforce any implementation solution in comparison with
another one. But, it is only to ensure that anyhow, all Sequences will be considered as Non Interrupti-
ble Sequences.
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[SPI126]  ⌈When  the SPI Handler/Driver is configured allowing interruptible Se-
quences, all Sequences declared shall have their dedicated parameter
SpiInterruptibleSequence  (see  SPI064  &  SPI106) to identify whether the Se-
quence can be suspended during transmission.⌋()

[SPI014] ⌈In case of a Sequence configured as Interruptible Sequence and accord-
ing to [SPI125] requirement, the SPI Handler/Driver is allowed to suspend an already
started Sequence transmission in favour of another Sequence with a higher priority
Job (see SPI002 & SPI093). That means, at the end of a Job transmission (that be-
longs to the interruptible sequence) with another Sequence transmit request pending,
the SPI Handler/Driver shall perform a rescheduling in order to elect the next Job to
transmit.⌋(BSW12260, BSW12037)

[SPI127] ⌈In case of a Sequence configured as Non-Interruptible Sequence and ac-
cording to  requirement  [SPI125],  the SPI Handler/Driver is not allowed to suspend
this already started Sequence transmission in favour of another Se-
quence.⌋(BSW12037)

[SPI080] ⌈When using Interruptible Sequences, the caller must be aware that if the
multiple Sequences access the same Channels, the data for these Channels may be
overwritten by the highest priority Job accessing each Channel.⌋()

7.2.5  LEVEL 2, Enhanced behaviour

The intention of this functionality level is to provide a Handler/Driver with a complete
set of services to handle synchronous and asynchronous transmissions. This could
be the case for ECU with a lot of functions related to SPI networks having different
priorities but also for ECU using external devices with different speeds.

Handling asynchronous and synchronous transmissions means that the microcontrol-
ler for which this software module is dedicated has to provide more than one SPI bus
(see [SPI108]). In fact, the goal is to support SPI buses using a so-called synchro-
nous driver and to support other SPI buses using a so-called asynchronous driver.

[SPI128]    ⌈The LEVEL 2 SPI Handler/Driver shall offer a synchronous transfer ser-
vice for a dedicated SPI bus and it shall also offer an asynchronous transfer service
for other SPI buses.⌋()

[SPI283]  ⌈In LEVEL 2 if there is no on going Sequence transmission, the SPI Han-
dler/Driver shall be in idle state (SPI_IDLE).⌋()

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[SPI129] ⌈The SPI bus dedicated for synchronous transfers is prearranged. It means,
that the bus is selected for synchronous transfers. The selected bus shall be pub-
lished by supplier of this software module.⌋()

This functionality level, based on a mixed usage of synchronous transmission on one
prearranged SPI bus and asynchronous transmission on others, generates re-
strictions on configuration and usage of Sequences and Jobs.

[SPI130]  ⌈The so-called  synchronous Sequences shall only be composed of Jobs
that are associated to the prearranged SPI bus. These Sequences shall be used with
synchronous services3 only.⌋()

[SPI131]  ⌈Jobs associated with the prearranged SPI bus  shall not belong to Se-
quences containing Jobs associated with another SPI bus. In other words, mixed Se-
quences (synchronous with asynchronous Jobs) shall not be allowed.⌋()

Usually, depending on software design, asynchronous end transmission may be de-
tected by polling or interrupt mechanisms. This level of functionality proposes both
mechanisms that are selectable during execution time.

[SPI155] ⌈The SPI Handler/Driver LEVEL 2 shall implement one polling mechanism
mode and one interrupt mechanism mode for SPI busses handled asynchronously.⌋()

[SPI156] ⌈Both the polling mechanism and interrupt mechanism modes for SPI bus-
ses shall be selectable during execution time (see [SPI188]).⌋()

[SPI140] ⌈If SpiHwUnitSynchronous is set to "Synchronous" for a job, the associ-
ated bus defined by SpiHwUnit behave same as prearranged bus. It means that all
requirements valid for prearranged bus will be valid also for the bus assigned to this
job.⌋()

The requirements for LEVEL 0 apply to synchronous behaviour.
The requirements for LEVEL 1 apply to asynchronous behaviour.

7.3  Scheduling Advices

For asynchronous levels, LEVEL 1 and LEVEL 2, the SPI Handler/Driver can call end
notification functions at the end of a Job and/or Sequence transmission (see
[SPI118]). In a second time, in case of interruptible Sequences (that could be sus-
pended), if another Sequence transmit request is pending, a rescheduling is also

3 The second part of this requirement is aim at SPI Handler/Driver users. But, it is up to the software
module supplier to implement mechanisms in order to prevent potential misuses by users.
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done by the SPI Handler/Driver in order to elect the next Job to transmit (see
[SPI014]).

[SPI088]  ⌈For asynchronous levels, LEVEL 1 and LEVEL 2, the SPI Handler/Driver
can call end notification functions at the end of a Job.⌋()

[SPI268]  ⌈For asynchronous levels, LEVEL 1 and LEVEL 2, the SPI Handler/Driver
can call end notification functions at the end of a Sequence transmission.⌋()

[SPI269]    ⌈For asynchronous levels, LEVEL 1 and LEVEL 2 in case of interruptible
Sequences, if another Sequence transmit request is pending, a rescheduling is also
done by the SPI Handler/Driver in order to elect the next Job to transmit.⌋()

[SPI270]    ⌈In case call end notification function and rescheduling are fully done by
software, the order between these shall be first scheduling and then the call of end
notification function executed.⌋()

[SPI271]    ⌈In case call end notification function and rescheduling are fully done by
hardware, the order could not be configured as required; the order shall be complete-
ly documented.⌋()

7.4  Error classification

[SPI004]
⌈SPI Handler/driver shall be able to detect the error
SPI_E_PARAM_CHANNEL(0x0A) when API service called with wrong parame-
ter.⌋(BSW00327, BSW00337, BSW00385)

[SPI237]
⌈SPI Handler/driver shall be able to detect the error
SPI_E_PARAM_JOB(0x0B) when API service called with wrong parameter.⌋()

[SPI238]
⌈SPI Handler/driver shall be able to detect the error
SPI_E_PARAM_SEQ(0x0C) when API service called with wrong parameter.⌋()

[SPI240]
⌈SPI Handler/driver shall be able to detect the error
SPI_E_PARAM_LENGTH(0x0D) when API service called with wrong parameter.⌋()

[SPI241]
⌈SPI Handler/driver shall be able to detect the error
SPI_E_PARAM_UNIT(0x0E) when API service called with wrong parameter.⌋()

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[SPI242] ⌈SPI Handler/driver shall be able to detect the error SPI_E_UNINIT(0x1A)
when API service used without module initialization.⌋()

[SPI243]
⌈SPI Handler/driver shall be able to detect the error
SPI_E_SEQ_PENDING(0x2A) when services called in a wrong sequence.⌋()

[SPI245]
⌈SPI Handler/driver shall be able to detect the error
SPI_E_SEQ_IN_PROCESS(0x3A) when synchronous transmission service called at
wrong time.⌋()

[SPI246]
⌈SPI Handler/driver shall be able to detect the error
SPI_E_ALREADY_INITIALIZED(0x4A) when API SPI_Init service called while the
SPI driver has already been initialized time.⌋()

[SPI195]
⌈SPI  Handler/driver shall be able to detect the error
SPI_E_HARDWARE_ERROR  when an hardware error occur during asynchronous
transmit. Please see also SPI267.⌋()

The table below summarize the errors that the SPI Handler/Driver shall be able to
detect.

Type or error
Relevance
Related error code
Value(hex)
API service called  Development  SPI_E_PARAM_CHANNEL
0x0A
with wrong param-
SPI_E_PARAM_JOB
0x0B
SPI_E_PARAM_SEQ
0x0C
eter
SPI_E_PARAM_LENGTH
0x0D
SPI_E_PARAM_UNIT
0x0E
APIs called with a  Development  SPI_E_PARAM_POINTER
0x10
Null Pointer

API service used
Development  SPI_E_UNINIT
0x1A
without module

initialization
Services called in
Development  SPI_E_SEQ_PENDING
0x2A
a wrong sequence
Synchronous
Development  SPI_E_SEQ_IN_PROCESS
0x3A
transmission ser-
vice called at
wrong time
API SPI_Init ser-
Development  SPI_E_ALREADY_INITIALIZED
0x4A
vice called while
the SPI driver has
already been ini-
tialized
Hardware error
Production
SPI_E_HARDWARE_ERROR
Assigned
detected during
by DEM
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asynchronous
transmit

[SPI097] ⌈Values for production code Event Ids are assigned externally by the con-
figuration of the Dem. They are published in the file Dem_IntErrId.h and included via
Dem.h.⌋(BSW00337, BSW00409)

[SPI007]  ⌈Additional errors that are detected because of specific implementation
and/or specific hardware properties shall be added to the SPI device specific imple-
mentation description.⌋(BSW00337, BSW00385)

[SPI098] ⌈Development error values are of type uint8.⌋(BSW00337)

7.5  Error detection

[SPI005]    ⌈The detection of all development errors is configurable at pre-compile
time.⌋(BSW00350, BSW00369, BSW00386)

[SPI249]    ⌈The detection of all development errors is configurable as (ON/OFF) by
the switch SpiDevErrorDetect.⌋()

[SPI250]  ⌈The switch SpiDevErrorDetect shall activate or deactivate the detection of
all development errors.⌋()

[SPI029] ⌈ If the switch SpiDevErrorDetect is enabled API parameter checking is
also enabled. The detailed description of the detected errors can be found in chapter
7.5.1. ⌋(BSW00323, BSW00369, BSW00386)

[SPI099]  ⌈The detection of production code errors cannot be switched
off.⌋(BSW00339, BSW00421)

7.5.1  API parameter checking

[SPI031] ⌈The API parameter Channel shall have a value within the defined chan-
nels in the initialization data structure, and the correct type of channel (IB or EB) has
to be used with services. Related error value: SPI_E_PARAM_CHANNEL. Otherwise,
the service is not done and the return value shall be E_NOT_OK. ⌋(BSW00323)

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[SPI032]  ⌈The API parameters Sequence and Job shall have values within the spec-
ified range of values. Related errors values: SPI_E_PARAM_SEQ or
SPI_E_PARAM_JOB.⌋(BSW00323)

[SPI254]  ⌈If the Sequence and Job related service is not done and, depending on
services, either the return value shall be E_NOT_OK or a failed result
(SPI_JOB_FAILED or SPI_SEQ_FAILED).⌋()

[SPI060]  ⌈The API parameter Length of data shall have a value within the specified
buffer maximum value. Related error value: SPI_E_PARAM_LENGTH.⌋(BSW00323)

[SPI258]  ⌈  If the API parameter Length related service is not done and the return
value shall be E_NOT_OK.⌋()

[SPI143]  ⌈The API parameter HWUnit shall have a value within the specified range
of values. Related error value: SPI_E_PARAM_UNIT.⌋()

[SPI288]    ⌈If HWUnit related service is not done and the return value shall be
SPI_UNINIT.⌋()

7.5.2  SPI state checking

[SPI046]  ⌈If development error detection for the SPI module is enabled and the SPI
Handler/Driver’s environment calls any API function before initialization, an error
should be reported to the DET with the error value SPI_E_UNINIT according to the
configuration.⌋(BSW00406)

[SPI256]    ⌈The SPI Handler/Driver shall not process the invoked function but, de-
pending on the invoked function, shall either return the value E_NOT_OK or a failed
result (SPI_JOB_FAILED or SPI_SEQ_FAILED).⌋()

[SPI233] ⌈
If development error detection for the SPI module is enabled, the calling of the rou-
tine SPI_Init() while the SPI driver is already initialized will cause a development error
SPI_E_ALREADY_INITIALIZED  and the desired functionality shall be left without
any action.⌋()

7.6  Error notification

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[SPI100] ⌈Detected development errors shall be reported to the error hook of the De-
velopment Error Tracer (DET) if the pre-processor switch SpiDevErrorDetect  is
set (see chapter 10).⌋(BSW00338)

[SPI006] ⌈Production relevant errors shall be reported to the Diagnostic Event Man-
ager (DEM). They shall not be used as the return value of the called func-
tion.⌋(BSW00339, BSW00369, BSW00421)

7.7  Version check

[SPI069] ⌈Spi.c shall check if the correct version of Spi.h is included. This shall be
done by a pre-processor check.⌋(BSW004)

[SPI369]  ⌈The  SPI module  shall avoid the integration of incompatible files by the
following pre-processor checks:
for included (external) header files,
  <MODULENAME>_AR_RELEASE_MAJOR_VERSION
  <MODULENAME>_AR_RELEASE_MINOR_VERSION
shall be verified.⌋(BSW004)

7.8  Debugging

[SPI363]  ⌈Each variable that shall be accessible by AUTOSAR Debugging, shall be
defined as global variable.⌋()

[SPI364]  ⌈All type definitions of variables which shall be debugged, shall be acces-
sible by the header file Spi.h.⌋()

[SPI365]  ⌈The declaration of variables in the header file shall be such, that it is pos-
sible to calculate the size of the variables by C-"sizeof".⌋()

[SPI366]    ⌈Variables available for debugging shall be described in the respective
Basic Software Module Description⌋()

[SPI367]  ⌈The states SPI_UNINIT, SPI_IDLE, SPI_BUSY shall be available for de-
bugging.⌋()
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8  API specification

8.1  Imported types

In this chapter all types included from the following files are listed:

[SPI174]  ⌈Dem_EventIdType shall be imported from Dem_Types.h.⌋(BSW00357)

[SPI296]  ⌈Std_VersionInfoType shall be imported from Std_Types.h.⌋()

[SPI297]  ⌈Std_ReturnType shall be imported from Std_Types.h.⌋()

Module
Imported Type
Dem
Dem_EventIdType
Dem_EventStatusType
Std_Types
Std_ReturnType
Std_VersionInfoType

8.2  Type definitions

8.2.1  Spi_ConfigType

Name:
Spi_ConfigType
Type:
Structure
Range:
Implementation  The contents of the initialization data structure are SPI spe-
Specific
cific.
Description:
This type of the external data structure shall contain the initialization data for the
SPI Handler/Driver.

[SPI344]  ⌈The description of the type Spi_ConfigType is implementation specific and
it shall be provided for external use.⌋()

[SPI008]  ⌈The type Spi_ConfigType is an external data structure and shall con-
tain the initialization data for the SPI Handler/Driver. It shall contain:
•  MCU dependent properties for SPI HW units
•  Definition of Channels
•  Definition of Jobs
•  Definition of Sequences⌋(BSW00405, BSW12125, BSW12256, BSW12257,
BSW12025, BSW12024)

[SPI063] ⌈For the type Spi_ConfigType, the definition for each Channel shall con-
tain:
•  Buffer usage with EB/IB Channel
•  Transmit data width (1 up to 32 bits)
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•  Number of data buffers for IB Channels (at least 1) or it is the maximum of da-
ta for EB Channels (a value of 0 makes no sense)
•  Transfer start LSB or MSB
•  Default transmit value⌋(BSW12257, BSW12025, BSW12197, BSW12024)

[SPI009]  ⌈For the type Spi_ConfigType, the definition for each Job shall contain:
•  Assigned SPI HW Unit
•  Assigned Chip Select pin (it is possible to assign no pin)
•  Chip select functionality on/off
•  Chip select pin polarity high or low
•  Baud rate
•  Timing between clock and chip select
•  Shift clock idle low or idle high
•  Data shift with leading or trailing edge
•  Priority (4 levels are available from 0, the lower to 3, the higher)
•  Job finish end notification function
•  MCU dependent properties for the Job (only if needed)
•  Fixed link of Channels (at least one)⌋(BSW00344, BSW12056, BSW12125,
BSW12093, BSW12094, BSW12256, BSW12257, BSW12025, BSW12179,
BSW12026, BSW12259, BSW12258, BSW12260, BSW12032, BSW12033,
BSW12150)

[SPI064] ⌈For the type Spi_ConfigType, the definition for each Sequence shall
contain:
•  Collection of Jobs (at least one)
•  Interruptible or not interruptible after each Job
•  Sequence finish end notification function⌋(BSW12056, BSW12179,
BSW12260, BSW12199, BSW12150)

[SPI010]  ⌈For the type Spi_ConfigType, the configuration will map the Jobs to the
different SPI hardware units and the devices.⌋(BSW12093, BSW12257)

8.2.2  Spi_StatusType

Name:
Spi_StatusType
Type:
Enumeration
Range:
SPI_UNINIT
The SPI Handler/Driver is not initialized or not usable.

SPI_IDLE
The SPI Handler/Driver is not currently transmitting any Job.
SPI_BUSY
The SPI Handler/Driver is performing a SPI Job (transmit).

Description:
This type defines a range of specific status for SPI Handler/Driver.

[SPI061]  ⌈The type Spi_StatusType defines a range of specific status for SPI Han-
dler/Driver. It informs about the SPI Handler/Driver status or specified SPI Hardware
microcontroller peripheral.⌋(BSW00335)
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[SPI259]  ⌈The type Spi_StatusType can be obtained calling the API service
Spi_GetStatus.⌋()

[SPI260]  ⌈The type Spi_StatusType can be obtained calling the API service
Spi_GetHWUnitStatus.⌋()

[SPI011] ⌈After reset, the type Spi_StatusType shall have the default value
SPI_UNINIT with the numeric value 0.⌋()

[SPI345] ⌈ API service Spi_GetStatus shall return SPI_UNINIT when the SPI Han-
dler/Driver is not initialized or not usable.⌋()

[SPI346]  ⌈API service Spi_GetStatus shall return SPI_IDLE when The SPI Han-
dler/Driver is not currently transmitting any Job.⌋()
[SPI347]  ⌈API service Spi_GetStatus shall return SPI_BUSY when The SPI Han-
dler/Driver is performing a SPI Job transmit.⌋()

[SPI348]  ⌈Spi_GetHWUnitStatus function shall return SPI_IDLE when The SPI
Hardware microcontroller peripheral is not currently transmitting any Job,⌋()

[SPI349]  ⌈Spi_GetHWUnitStatus function shall return SPI_BUSYwhen The SPI
Hardware microcontroller peripheral is performing a SPI Job transmit.⌋()

8.2.3  Spi_JobResultType

Name:
Spi_JobResultType
Type:
Enumeration
Range:
SPI_JOB_OK
The last transmission of the Job has been finished success-
fully.

SPI_JOB_PENDING
The SPI Handler/Driver is performing a SPI Job. The mean-
ing of this status is equal to SPI_BUSY.

SPI_JOB_FAILED  The last transmission of the Job has failed.

SPI_JOB_QUEUED  An asynchronous transmit Job has been accepted, while
actual transmission for this Job has not started yet.

Description:
This type defines a range of specific Jobs status for SPI Handler/Driver.

[SPI062]  ⌈The type Spi_JobResultType defines a range of specific Jobs status for
SPI Handler/Driver.⌋(BSW00335)

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[SPI261]  ⌈The type Spi_JobResultType it informs about a SPI Handler/Driver Job
status and can be obtained calling the API service Spi_GetJobResult with the Job
ID.⌋()

[SPI012] ⌈After reset, the type Spi_JobResultType shall have the default value
SPI_JOB_OK with the numeric value 0.⌋()

[SPI350]  ⌈The function Spi_GetJobResult shall return SPI_JOB_OK when the last
transmission of the Job has been finished successfully.⌋()

8.2.4  Spi_SeqResultType

Name:
Spi_SeqResultType
Type:
Enumeration
Range:
SPI_SEQ_OK
The last transmission of the Sequence has been finished
successfully.

SPI_SEQ_PENDING  The SPI Handler/Driver is performing a SPI Sequence. The
meaning of this status is equal to SPI_BUSY.

SPI_SEQ_FAILED  The last transmission of the Sequence has failed.

SPI_SEQ_CANCELED
The last transmission of the Sequence has been canceled
by user.

Description:
This type defines a range of specific Sequences status for SPI Handler/Driver.

[SPI351]  ⌈The type Spi_SeqResultType defines a range of specific Sequences sta-
tus for SPI Handler/Driver and can be obtained calling the API service
Spi_GetSequenceResult, it shall be provided for external use.⌋()

[SPI019]  ⌈The type Spi_SeqResultType defines the range of specific Sequences
status for SPI Handler/Driver.⌋(BSW00335)

[SPI251]  ⌈The type Spi_SeqResultType defines about SPI Handler/Driver Sequence
status and can be obtained calling the API service Spi_GetSequenceResult with the
Sequence ID.⌋()

[SPI017] ⌈After reset, the type Spi_SeqResultType shall have the default value
SPI_SEQ_OK with the numeric value 0.⌋()

[SPI352]  ⌈Spi_GetSequenceResult function shall return SPI_SEQ_OK when the last
transmission of the Sequence has been finished successfully.⌋()

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[SPI353]  ⌈Spi_GetSequenceResult function shall return SPI_SEQ_PENDING when
the SPI Handler/Driver is performing a SPI Sequence. The meaning of this status is
equal to SPI_BUSY.⌋()

[SPI354]  ⌈Spi_GetSequenceResult function shall return SPI_SEQ_FAILED when
the last transmission of the Sequence has failed.⌋()

8.2.5  Spi_DataType

Name:
Spi_DataType
Type:
uint
Range:
8..32 bit
--
This is implementation specific but not all values may be
valid within the type.This type shall be chosen in order to
have the most efficient implementation on a specific mi-
crocontroller platform.
Description:
Type of application data buffer elements.

[SPI355]  ⌈Spi_DataType This defines the type of application data buffer elements.
Type is uint8,uint16,uint32 and Range is 8 to 32 bit. it shall be provided for external
use.⌋()

[SPI164] ⌈The type Spi_DataType refers to application data buffer elements.⌋()

8.2.6  Spi_NumberOfDataType

Name:
Spi_NumberOfDataType
Type:
uint16
Description:
Type for defining the number of data elements of the type Spi_DataType to send
and / or receive by Channel

[SPI165] ⌈The type Spi_NumberOfDataType is used for defining the number of
data elements of the type Spi_DataType to send and / or receive by Channel.⌋()

8.2.7  Spi_ChannelType

Name:
Spi_ChannelType
Type:
uint8
Description:
Specifies the identification (ID) for a Channel.

[SPI356]  ⌈The type Spi_ChannelType specifies the identification (ID) for a Chan-
nel.⌋()

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[SPI166] ⌈The type Spi_ChannelType is used for specifying the identification (ID)
for a Channel.⌋()

8.2.8  Spi_JobType

Name:
Spi_JobType
Type:
uint16
Description:
Specifies the identification (ID) for a Job.

[SPI357]  ⌈The type Spi_JobType specifies the identification (ID) for a Job.⌋()

[SPI167] ⌈The type Spi_JobType is used for specifying the identification (ID) for a
Job.⌋()

8.2.9  Spi_SequenceType

Name:
Spi_SequenceType
Type:
uint8
Description:
Specifies the identification (ID) for a sequence of jobs.

[SPI358]  ⌈The type Spi_SequenceType specifies the identification (ID) for a se-
quence of jobs.⌋()

[SPI168] ⌈The type Spi_SequenceType is used for specifying the identification (ID)
for a sequence of jobs.⌋()

8.2.10 Spi_HWUnitType

Name:
Spi_HWUnitType
Type:
uint8
Description:
Specifies the identification (ID) for a SPI Hardware microcontroller peripheral
(unit).

[SPI359]  ⌈The type Spi_HWUnitType specifies the identification (ID) for a SPI Hard-
ware microcontroller peripheral (unit).⌋()

[SPI169] ⌈The type Spi_HWUnitType is used for specifying the identification (ID) for
a SPI Hardware microcontroller peripheral (unit).⌋()

8.2.11 Spi_AsyncModeType

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Name:
Spi_AsyncModeType
Type:
Enumeration
Range:
SPI_POLLING_MODE  The asynchronous mechanism is ensured by polling, so
interrupts related to SPI busses handled asynchronously

are disabled.
SPI_INTERRUPT_MODE
The asynchronous mechanism is ensured by interrupt, so
interrupts related to SPI busses handled asynchronously

are enabled.
Description:
Specifies the asynchronous mechanism mode for SPI busses handled asynchro-
nously in LEVEL 2.

[SPI360]    ⌈The type Spi_AsyncModeType specifies the asynchronous mechanism
mode for SPI buses handled asynchronously in LEVEL 2 and obtained by the API
Spi_SetAsyncMode.⌋()

[SPI170]  ⌈The type Spi_AsyncModeType is used for specifying the asynchronous
mechanism mode for SPI busses handled asynchronously in LEVEL 2.⌋()

[SPI150]  ⌈The type Spi_AsyncModeType  is made available or not depending on
the pre-compile time parameter: SpiLevelDelivered. This is only relevant for
LEVEL 2.⌋()

[SPI361]    ⌈If API Spi_SetAsyncMode function is called by the parameter value
SPI_POLLING_MODE then asynchronous mechanism is ensured by polling. So in-
terrupts related to SPI buses handled asynchronously are disabled.⌋()

[SPI362]    ⌈If API Spi_SetAsyncMode function is called by the parameter value
SPI_INTERRUPT_MODE asynchronous mechanism is ensured by interrupt, so inter-
rupts related to SPI buses handled asynchronously are enabled.⌋()

8.3  Function definitions

8.3.1  Spi_Init

[SPI175]  ⌈void Spi_Init( const Spi_ConfigType* ConfigPtr )

Service name:
Spi_Init
Syntax:
void Spi_Init(
  const Spi_ConfigType* ConfigPtr
)
Service ID[hex]:
0x00
Sync/Async:
Synchronous
Reentrancy:
Non Reentrant
Parameters (in):
ConfigPtr
Pointer to configuration set
Parameters (in-
None
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out):
Parameters (out):  None
Return value:
None
Description:
Service for SPI initialization.
⌋()

[SPI298]  ⌈The operation Spi_Init is Non Re-entrant.⌋()

[SPI299]  ⌈The function Spi_Init provides the service for SPI initialization.⌋()

[SPI013]  ⌈The function Spi_Init shall initialize all SPI relevant registers with the
values of the structure referenced by the parameter ConfigPtr.⌋(BSW00405,
BSW101, BSW12057, BSW12125)

[SPI082] ⌈The function Spi_Init shall define default values for required parameters
of the structure referenced by the ConfigPtr. For example: all buffer pointers shall
be initialized as a null value pointer.⌋()

[SPI015] ⌈After the module initialization using the function Spi_Init, the SPI Han-
dler/Driver shall set its state to SPI_IDLE, the Sequences result to SPI_SEQ_OK and
the jobs result to SPI_JOB_OK.⌋(BSW00406, BSW101, BSW12057)

[SPI151] ⌈For LEVEL 2 (see chapter 7.2.5 and SPI103), the function Spi_Init shall
set the SPI Handler/Driver asynchronous mechanism mode to SPI_POLLING_MODE
by default. Interrupts related to SPI busses shall be disabled.⌋()

A re-initialization of a SPI Handler/Driver by executing the Spi_Init() function requires
a de-initialization before by executing a Spi_DeInit().

Parameters of the function Spi_Init shall be checked as it is explained in section
API parameter checking

8.3.2  Spi_DeInit

[SPI176]  ⌈Std_ReturnType Spi_DeInit( )

Service name:
Spi_DeInit
Syntax:
Std_ReturnType Spi_DeInit(
  void
)
Service ID[hex]:
0x01
Sync/Async:
Synchronous
Reentrancy:
Non Reentrant
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Parameters (in):
None
Parameters (in-
None
out):
Parameters (out):  None
Std_ReturnType  E_OK: de-initialisation command has been accepted
Return value:
E_NOT_OK: de-initialisation command has not been accepted
Description:
Service for SPI de-initialization.
⌋()

[SPI300]  ⌈The operation Std_ReturnType Spi_DeInit( ) is Non Re-entrant.⌋()

[SPI301]  ⌈When the API Spi_DeInit has been accepted the return value of this func-
tion shall be E_OK.⌋()

[SPI302]  ⌈When the API Spi_DeInit has not been accepted the return value of this
function shall be E_NOT_OK.⌋()

[SPI303]  ⌈The function Spi_DeInit provides the service for SPI de-initialization.⌋()

[SPI021]  ⌈The function Spi_DeInit shall de-initialize SPI Han-
dler/Driver.⌋(BSW00336, BSW12163, BSW12064)

[SPI252]  ⌈In case of the SPI Handler/Driver state is not SPI_BUSY, the
deInitialization function shall put all already initialized microcontroller SPI peripherals
into the same state such as Power On Reset.⌋()

[SPI253]  ⌈The function call Spi_DeInit shall be rejected if the status of SPI Han-
dler/Driver is SPI_BUSY.⌋()

[SPI022] ⌈After the module de-initialization using the function Spi_DeInit, the SPI
Handler/Driver shall set its state to SPI_UNINIT.⌋(BSW00336, BSW12163)

The SPI Handler/Driver shall have been initialized before the function Spi_DeInit
is called, otherwise see [SPI046].

8.3.3  Spi_WriteIB

[SPI177]  ⌈Std_ReturnType Spi_WriteIB( Spi_ChannelType Channel, const
Spi_DataType* DataBufferPtr )

Service name:
Spi_WriteIB
Syntax:
Std_ReturnType Spi_WriteIB(
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  Spi_ChannelType Channel,
  const Spi_DataType* DataBufferPtr
)
Service ID[hex]:
0x02
Sync/Async:
Synchronous
Reentrancy:
Reentrant
Channel
Channel ID.
DataBufferPtr
Pointer to source data buffer. If this pointer is null, it is assumed
Parameters (in):
that the data to be transmitted is not relevant and the default
transmit value of this channel will be used instead.
Parameters (in-
None
out):
Parameters (out):  None
Std_ReturnType E_OK: write command has been accepted
Return value:
E_NOT_OK: write command has not been accepted
Description:
Service for writing one or more data to an IB SPI Handler/Driver Channel specified
by parameter.
⌋()

[SPI304]  ⌈The operation Spi_WriteIB is Re-entrant.⌋()

[SPI305]  ⌈When the API Spi_WriteIB command has been accepted the function re-
turns the value E_OK.⌋()

[SPI306]  ⌈When the API Spi_WriteIB command has not been accepted the function
returns the value E_NOT_OK.⌋()

[SPI307]  ⌈The function Spi_WriteIB provides the service for writing one or more data
to an IB SPI Handler/Driver Channel by the respective parameter.⌋()

[SPI018] ⌈The function Spi_WriteIB shall write one or more data to an IB SPI
Handler/Driver Channel specified by the respective parameter.⌋(BSW12101,
BSW12153)

[SPI024] ⌈The function Spi_WriteIB shall take over the given parameters, and
save the pointed data to the internal buffer defined with the function Spi_Init.⌋()

[SPI023] ⌈If the given parameter “DataBufferPtr” is null, the function Spi_WriteIB
shall assume that the data to be transmitted is not relevant and the default transmit
value of the given channel shall be used instead.⌋()

[SPI137] ⌈The function Spi_WriteIB shall be pre-compile time configurable by the
parameter SpiChannelBuffersAllowed. This function is only relevant for Chan-
nels with IB.⌋()
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Parameters of the function Spi_WriteIB shall be checked as it is explained in sec-
tion API parameter checking.

The SPI Handler/Driver shall have been initialized before the function Spi_WriteIB
is called, otherwise see [SPI046].

8.3.4  Spi_AsyncTransmit

[SPI178]  ⌈Std_ReturnType Spi_AsyncTransmit( Spi_SequenceType Sequence )

Service name:
Spi_AsyncTransmit
Syntax:
Std_ReturnType Spi_AsyncTransmit(
  Spi_SequenceType Sequence
)
Service ID[hex]:
0x03
Sync/Async:
Asynchronous
Reentrancy:
Reentrant
Parameters (in):
Sequence
Sequence ID.
Parameters (in-
None
out):
Parameters (out):  None
Std_ReturnType  E_OK: Transmission command has been accepted
Return value:
E_NOT_OK: Transmission command has not been accepted
Description:
Service to transmit data on the SPI bus.
⌋()

[SPI308]  ⌈The operation Std_ReturnType Spi_AsyncTransmit( Spi_SequenceType
Sequence ) is Re-entrant.⌋()

[SPI309]  ⌈When the API Spi_AsyncTransmit command has been accepted the func-
tion shall return the value E_OK.⌋()

[SPI310]  ⌈When the API Spi_AsyncTransmit command has not been accepted the
function shall return the value E_NOT_OK.⌋()

[SPI311]  ⌈The function Spi_AsyncTransmit provides service to transmit data on the
SPI bus.⌋()

[SPI020] ⌈The function Spi_AsyncTransmit shall take over the given parameter,
initiate a transmission, set the SPI Handler/Driver status to SPI_BUSY, set the se-
quence result to SPI_SEQ_PENDING and return. ⌋(BSW12099, BSW12101,
BSW12103)

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[SPI194] ⌈When the function Spi_AsyncTransmit is called, shall take over the given
parameter and set the Job status to SPI_JOB_QUEUED, which can be obtained by
calling the API service Spi_GetJobResult.⌋()

[SPI157]  ⌈When the function Spi_AsyncTransmit is called, the SPI Handler/Driver
shall handle the Job results. Result shall be SPI_JOB_PENDING when the transmis-
sion of Jobs is started.⌋()

[SPI292]  ⌈When the function Spi_AsyncTransmit is called, the SPI Handler/Driver
shall handle the Job results. Result shall be SPI_JOB_OK when the transmission of
Jobs is success.⌋()

[SPI293]  ⌈When the function Spi_AsyncTransmit is called, the SPI Handler/Driver
shall handle the Job results. Result shall be SPI_JOB_FAILED when the transmis-
sion of Jobs is failed.⌋()

[SPI081]  ⌈When the function Spi_AsyncTransmit is called and the requested Se-
quence is already in state SPI_SEQ_PENDING, the SPI Handler/Driver shall not take
in account this new request and this function shall return with value E_NOT_OK, in
this case.⌋()

[SPI266]  ⌈When the function Spi_AsyncTransmit is called and the requested Se-
quence is already in state SPI_SEQ_PENDING the SPI Handler/Driver shall report
the SPI_E_SEQ_PENDING error.⌋()

[SPI086] ⌈When the function Spi_AsyncTransmit is called and the requested Se-
quence shares Jobs with another sequence that is in the state SPI_SEQ_PENDING,
the SPI Handler/Driver shall not take into account this new request and this function
shall return the value E_NOT_OK. In this case and according to [SPI100], the SPI
Handler/Driver shall report the SPI_E_SEQ_PENDING error.⌋()

[SPI035] ⌈When the function Spi_AsyncTransmit is used with EB and the source
data pointer has been provided as NULL using the Spi_SetupEB method, the de-
fault transmit data configured for each channel will be transmitted. (See also
[SPI028])⌋(BSW12200, BSW12201)

[SPI036] ⌈When the function Spi_AsyncTransmit is used with EB and the destina-
tion data pointer has been provided as NULL using the Spi_SetupEB method, the
SPI Handler/Driver shall ignore receiving data (See also [SPI030])⌋()

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[SPI055] ⌈When the function Spi_AsyncTransmit is used for a Sequence with
linked Jobs, the function shall transmit from the first Job up to the last Job in the se-
quence.⌋(BSW12181)

[SPI057] ⌈ At the end of a sequence transmission initiated by the function
Spi_AsyncTransmit and if configured, the SPI Handler/Driver shall invoke the se-
quence notification call-back function after the last Job end notification if this one is
also configured.⌋(BSW157, BSW12108)

[SPI133] ⌈The function Spi_AsyncTransmit is pre-compile time selectable by the
configuration parameter SpiLevelDelivered. This function is only relevant for
LEVEL 1 and LEVEL 2.⌋()

[SPI173] ⌈The SPI Handler/Driver’s environment shall call the function
Spi_AsyncTransmit after a function call of Spi_SetupEB for EB Channels or a
function call of Spi_WriteIB for IB Channels but before the function call
Spi_ReadIB.⌋()

Parameters of the function Spi_AsyncTransmit shall be checked as explained in
section API parameter checking

The SPI Handler/Driver shall have been initialized before the function
Spi_AsyncTransmit is called otherwise see [SPI046].

8.3.5  Spi_ReadIB

[SPI179]  ⌈Std_ReturnType Spi_ReadIB( Spi_ChannelType Channel, Spi_DataType*
DataBufferPointer )

Service name:
Spi_ReadIB
Syntax:
Std_ReturnType Spi_ReadIB(
  Spi_ChannelType Channel,
  Spi_DataType* DataBufferPointer
)
Service ID[hex]:
0x04
Sync/Async:
Synchronous
Reentrancy:
Reentrant
Parameters (in):
Channel
Channel ID.
Parameters (in-
None
out):
Parameters (out):  DataBufferPointer
Pointer to destination data buffer in RAM
Std_ReturnType
E_OK: read command has been accepted
Return value:
E_NOT_OK: read command has not been accepted
Description:
Service for reading synchronously one or more data from an IB SPI Handler/Driver
Channel specified by parameter.
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⌋()

[SPI312]  ⌈The operation Spi_ReadIB is Re-entrant.⌋()

[SPI313]  ⌈The function Spi_ReadIB return values E_OK: read command has been
accepted.⌋()

[SPI314]  ⌈The function Spi_ReadIB return values E_NOT_OK: read command has
not been accepted.⌋()

[SPI315]  ⌈The function Spi_ReadIB provides the service for reading synchronously
one or more data from an IB SPI Handler/Driver Channel specified by parameter.⌋()

[SPI016] ⌈The function Spi_ReadIB shall read synchronously one or more data
from an IB SPI Handler/Driver Channel specified by the respective parame-
ter.⌋(BSW12099, BSW12152)

[SPI027] ⌈The SPI Handler/Driver’s environment shall call the function Spi_ReadIB
after a Transmit method call to have relevant data within IB Channel.⌋()

[SPI138]  ⌈The function Spi_ReadIB is pre-compile time configurable by the pa-
rameter SpiChannelBuffersAllowed. This function is only relevant for Chan-
nels with IB.⌋()

Parameters of the function Spi_ReadIB shall be checked as it is explained in sec-
tion API parameter checking.

The SPI Handler/Driver shall have been initialized before the function Spi_ReadIB
is called otherwise see [SPI046].

8.3.6  Spi_SetupEB

[SPI180]  ⌈Std_ReturnType Spi_SetupEB( Spi_ChannelType Channel, const
Spi_DataType* SrcDataBufferPtr, Spi_DataType* DesDataBufferPtr,
Spi_NumberOfDataType Length )

Service name:
Spi_SetupEB
Syntax:
Std_ReturnType Spi_SetupEB(
  Spi_ChannelType Channel,
  const Spi_DataType* SrcDataBufferPtr,
  Spi_DataType* DesDataBufferPtr,
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  Spi_NumberOfDataType Length
)
Service ID[hex]:
0x05
Sync/Async:
Synchronous
Reentrancy:
Reentrant
Channel
Channel ID.
SrcDataBufferPtr  Pointer to source data buffer.
DesDataBufferPtr Pointer to destination data buffer in RAM.
Parameters (in):
Length
Length (in bytes) of the data to be transmitted from Srcda-
taBufferPtr and/or received from DesDataBufferPtr
Min.: 1
Max.: Max of data specified at configuration for this channel
Parameters (in-
None
out):
Parameters (out):  None
Std_ReturnType  E_OK: Setup command has been accepted
Return value:
E_NOT_OK: Setup command has not been accepted
Description:
Service to setup the buffers and the length of data for the EB SPI Handler/Driver
Channel specified.
⌋()

[SPI316]  ⌈The operation Spi_SetupEB is Re-entrant.⌋()

[SPI317]  ⌈Return values of the function Spi_SetupEB are E_OK: Setup command
has been accepted and E_NOT_OK: Setup command has not been accepted.⌋()

[SPI318]  ⌈The function Spi_SetupEB provides the service to setup the buffers and
the length of data for the EB SPI Handler/Driver Channel specified.⌋()

[SPI058] ⌈The function Spi_SetupEB shall set up the buffers and the length of data
for the specific EB SPI Handler/Driver Channel.⌋(BSW12103)

[SPI067] ⌈The function Spi_SetupEB shall update the buffer pointers and length
attributes of the specified Channel with the provided values.⌋(BSW12103)

As these attributes are persistent, they will be used for all succeeding calls to a
Transmit method (for the specified Channel).

[SPI028] ⌈When the SPI Handler/Driver’s environment is calling the function
Spi_SetupEB with the parameter SrcDataBufferPtr being a Null pointer, the
function shall transmit the default transmit value configured for the channel after a
Transmit method is requested. (See also [SPI035])⌋()

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[SPI030] ⌈When the function Spi_SetupEB is called with the parameter
DesDataBufferPtr being a Null pointer, the SPI Handler/Driver shall ignore the
received data after a Transmit method is requested.(See also [SPI036])⌋()

[SPI037] ⌈The SPI Handler/Driver’s environment shall call the Spi_SetupEB func-
tion once for each Channel with EB declared before the SPI Handler/Driver’s envi-
ronment calls a Transmit method on them.⌋()

[SPI139] ⌈The function Spi_SetupEB is pre-compile time configurable by the pa-
rameter SpiChannelBuffersAllowed. This function is only relevant for Chan-
nels with EB.⌋()

Parameters of the function Spi_SetupEB shall be checked as it is explained in sec-
tion API parameter checking.
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The SPI Handler/Driver shall have been initialized before the function Spi_SetupEB
is called otherwise see [SPI046].

8.3.7  Spi_GetStatus

[SPI181]  ⌈Spi_StatusType Spi_GetStatus( )

Service name:
Spi_GetStatus
Syntax:
Spi_StatusType Spi_GetStatus(
  void
)
Service ID[hex]:
0x06
Sync/Async:
Synchronous
Reentrancy:
Reentrant
Parameters (in):
None
Parameters (in-
None
out):
Parameters (out):  None
Return value:
Spi_StatusType
Spi_StatusType
Description:
Service returns the SPI Handler/Driver software module status.
⌋()

[SPI319]  ⌈The operation Spi_GetStatus is Re-entrant.⌋()

[SPI320]  ⌈The function Spi_GetStatus returns the SPI Handler/Driver software mod-
ule status.⌋()

[SPI025] ⌈The function Spi_GetStatus shall return the SPI Handler/Driver soft-
ware module status.⌋(BSW12064, BSW12104)

8.3.8  Spi_GetJobResult

[SPI182]  ⌈Spi_JobResultType Spi_GetJobResult( Spi_JobType Job )

Service name:
Spi_GetJobResult
Syntax:
Spi_JobResultType Spi_GetJobResult(
  Spi_JobType Job
)
Service ID[hex]:
0x07
Sync/Async:
Synchronous
Reentrancy:
Reentrant
Parameters (in):
Job
Job ID. An invalid job ID will return an undefined result.
Parameters (in-
None
out):
Parameters (out):  None
Return value:
Spi_JobResultType  Spi_JobResultType
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Description:
This service returns the last transmission result of the specified Job.
⌋()

[SPI321]  ⌈The operation Spi_GetJobResult is Re-entrant.⌋()

[SPI322]  ⌈The function Spi_GetJobResult service returns the last transmission result
of the specified Job.⌋()

[SPI026] ⌈The function Spi_GetJobResult shall return the last transmission result
of the specified Job. ⌋(BSW157, BSW12104)

[SPI038] ⌈The SPI Handler/Driver’s environment shall call the function
Spi_GetJobResult to inquire whether the Job transmission has succeeded
(SPI_JOB_OK) or failed (SPI_JOB_FAILED).⌋(BSW157)

NOTE: Every new transmit job that has been accepted by the SPI Handler/Driver
overwrites the previous job result with SPI_JOB_QUEUED or SPI_JOB_PENDING.

Parameters of the function Spi_GetJobResult shall be checked as it is explained
in section API parameter checking.

If SPI Handler/Driver has not been initialized before the function
Spi_GetJobResult is called, the return value is undefined.

8.3.9  Spi_GetSequenceResult

[SPI183]  ⌈Spi_SeqResultType Spi_GetSequenceResult( Spi_SequenceType Se-
quence )

Service name:
Spi_GetSequenceResult
Syntax:
Spi_SeqResultType Spi_GetSequenceResult(
  Spi_SequenceType Sequence
)
Service ID[hex]:
0x08
Sync/Async:
Synchronous
Reentrancy:
Reentrant
Sequence
Sequence ID. An invalid sequence ID will return an undefined
Parameters (in):
result.
Parameters (in-
None
out):
Parameters (out):  None
Return value:
Spi_SeqResultType Spi_SeqResultType
Description:
This service returns the last transmission result of the specified Sequence.
⌋()

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[SPI323]  ⌈The operation Spi_GetSequenceResult is Re-entrant.⌋()

[SPI324]  ⌈The function Spi_GetSequenceResult shall return the last transmission
result of the specified Sequence.⌋()

[SPI039] ⌈The function Spi_GetSequenceResult shall return the last transmission
result of the specified Sequence. ⌋(BSW157, BSW12104)

[SPI042] ⌈The SPI Handler/Driver’s environment shall call the function
Spi_GetSequenceResult to inquire whether the full Sequence transmission has
succeeded (SPI_SEQ_OK) or failed (SPI_SEQ_FAILED).⌋(BSW157, BSW12170)

Note:
-  Every new transmit sequence that has been accepted by the SPI Han-
dler/Driver overwrites the previous sequence result with SPI_SEQ_PENDING.
-  If the SPI Handler/Driver has not been initialized before the function
Spi_GetSequenceResult is called, the return value is undefined.

Parameters of the function Spi_GetSequenceResult shall be checked as it is ex-
plained in section API parameter checking.

8.3.10 Spi_GetVersionInfo

[SPI184]  ⌈void Spi_GetVersionInfo( Std_VersionInfoType* versioninfo )

Service name:
Spi_GetVersionInfo
Syntax:
void Spi_GetVersionInfo(
  Std_VersionInfoType* versioninfo
)
Service ID[hex]:
0x09
Sync/Async:
Synchronous
Reentrancy:
Reentrant
Parameters (in):
None
Parameters (in-
None
out):
Parameters (out):  versioninfo  Pointer to where to store the version information of this module.
Return value:
None
Description:
This service returns the version information of this module.
⌋()

[SPI325]  ⌈The operation Spi_GetVersionInfo is Non Re-entrant.⌋()

[SPI326]  ⌈The function Spi_GetVersionInfo service returns the version information of
this module.⌋()
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[SPI101]  ⌈The function Spi_GetVersionInfo  shall return the version information
of this module according to the definition of Std_VersionInfoType [13]
⌋(BSW00407)

[SPI196]  ⌈If source code for caller and callee of Spi_GetVersionInfo is availa-
ble, the SPI Handler/Driver should realize Spi_GetVersionInfo  as a macro, de-
fined in the module’s header file.⌋()

[SPI102]  ⌈The function Spi_GetVersionInfo is pre compile time configurable by the
configuration parameter SpiVersionInfoApi.⌋(BSW00407, BSW00411)

[SPI278]  ⌈The function Spi_GetVersionInfo is pre compile time configurable On/Off
by the configuration parameter SpiVersionInfoApi.⌋()

[SPI371]  ⌈If Det is enabled, the parameter versioninfo shall be checked for being
NULL. The error SPI_E_PARAM_POINTER shall be reported in case the value is a
NULL pointer.⌋()

8.3.11 Spi_SyncTransmit

[SPI185]  ⌈Std_ReturnType Spi_SyncTransmit( Spi_SequenceType Sequence )

Service name:
Spi_SyncTransmit
Syntax:
Std_ReturnType Spi_SyncTransmit(
  Spi_SequenceType Sequence
)
Service ID[hex]:
0x0a
Sync/Async:
Asynchronous
Reentrancy:
Reentrant
Parameters (in):
Sequence
Sequence ID.
Parameters (in-
None
out):
Parameters (out):  None
Std_ReturnType  E_OK: Transmission command has been accepted
Return value:
E_NOT_OK: Transmission command has not been accepted
Description:
Service to transmit data on the SPI bus
⌋()

[SPI327]  ⌈The operation Spi_SyncTransmit is Re-entrant.⌋()

[SPI328]  ⌈Return value of the function Spi_SyncTransmit is E_OK: when Transmis-
sion command has been accepted.⌋()

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[SPI329]  ⌈Return value of the function Spi_SyncTransmit is E_NOT_OK: When
Transmission command has not been accepted.⌋()

[SPI330]  ⌈The function Spi_SyncTransmit provides the service to transmit data on
the SPI bus.⌋()

[SPI134]  ⌈When the function Spi_SyncTransmit is called, shall take over the given
parameter and set the SPI Handler/Driver status to SPI_BUSY can be obtained call-
ing the API service SPI_GetStatus.⌋(BSW12152, BSW12153, BSW12154)

[SPI285]  ⌈When the function Spi_SyncTransmit is called, shall take over the given
parameter and set the Sequence status to SPI_SEQ_PENDING can be obtained
calling the API service Spi_GetSequenceResult.⌋()

[SPI286]  ⌈When the function Spi_SyncTransmit is called, shall take over the given
parameter and set the Job status to SPI_JOB_PENDING can be obtained calling the
API service Spi_GetJobResult.⌋()

[SPI135]  ⌈When the function Spi_SyncTransmit is called while a sequence is on
transmission and SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT is disabled or an-
other sequence is on transmition on same bus, the SPI Handler/Driver shall not take
into account this new transmission request and the function shall return the value
E_NOT_OK (see [SPI114]). In this case and according to [SPI100], the SPI Han-
dler/Driver shall report the SPI_E_SEQ_IN_PROCESS error.⌋()

[SPI136] ⌈The function Spi_SyncTransmit is pre-compile time selectable by the
configuration parameter SpiLevelDelivered. This function is only relevant for
LEVEL 0 and LEVEL 2.⌋()

Parameters of the function Spi_SyncTransmit shall be checked as it is explained
in section API parameter checking

8.3.12 Spi_GetHWUnitStatus

[SPI186]  ⌈Spi_StatusType Spi_GetHWUnitStatus( Spi_HWUnitType HWUnit )

Service name:
Spi_GetHWUnitStatus
Syntax:
Spi_StatusType Spi_GetHWUnitStatus(
  Spi_HWUnitType HWUnit
)
Service ID[hex]:
0x0b
Sync/Async:
Synchronous
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Reentrancy:
Reentrant
Parameters (in):
HWUnit
SPI Hardware microcontroller peripheral (unit) ID.
Parameters (in-
None
out):
Parameters (out):  None
Return value:
Spi_StatusType
Spi_StatusType
Description:
This service returns the status of the specified SPI Hardware microcontroller pe-
ripheral.
⌋()

[SPI331]  ⌈The operation Spi_GetHWUnitStatus is Re-entrant.⌋()

[SPI332]  ⌈The function Spi_GetHWUnitStatus service returns the status of the
specified SPI Hardware microcontroller peripheral.⌋()

[SPI141]  ⌈The function Spi_GetHWUnitStatus shall return the status of the specified
SPI Hardware microcontroller peripheral.⌋()

[SPI287]  ⌈The SPI Handler/Driver’s environment shall call this function to inquire
whether the specified SPI Hardware microcontroller peripheral is SPI_IDLE or
SPI_BUSY.⌋()

[SPI142]  ⌈The function Spi_GetHWUnitStatus is pre-compile time configurable
On / Off by the configuration parameter SpiHwStatusApi.⌋()

Parameters of the function Spi_GetHWUnitStatus shall be checked as it is ex-
plained in section API parameter checking.

If SPI Handler/Driver has not been initialized before the function
Spi_GetHWUnitStatus is called, the return value is undefined.

8.3.13 Spi_Cancel

[SPI187]  ⌈void Spi_Cancel( Spi_SequenceType Sequence )

Service name:
Spi_Cancel
Syntax:
void Spi_Cancel(
  Spi_SequenceType Sequence
)
Service ID[hex]:
0x0c
Sync/Async:
Asynchronous
Reentrancy:
Reentrant
Parameters (in):
Sequence
Sequence ID.
Parameters (in-
None
out):
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Parameters (out):  None
Return value:
None
Description:
Service cancels the specified on-going sequence transmission.
⌋()

[SPI333]  ⌈The operation Spi_Cancel is Re-entrant.⌋()

[SPI334]  ⌈The function Spi_Cancel service cancels the specified on-going sequence
transmission.⌋()

[SPI144]  ⌈The function Spi_Cancel shall cancel the specified on-going sequence
transmission without cancelling any Job transmission and set the sequence result to
SPI_SEQ_CANCELLED.⌋()

With other words, the Spi_Cancel function stops a Sequence transmission after a
(possible) on transmission Job ended and before a (potential) next Job transmission
starts.

[SPI145]  ⌈When the sequence is cancelled by the function Spi_Cancel and if con-
figured, the SPI Handler/Driver shall call the sequence notification call-back function
instead of starting a potential next job belonging to it.⌋()

[SPI146]  ⌈The function Spi_Cancel is pre-compile time configurable On / Off by
the configuration parameter SpiCancelApi.⌋()

The SPI Handler/Driver is not responsible on external devices damages or undefined
state due to cancelling a sequence transmission. It is up to the SPI Handler/Driver’s
environment to be aware to what it is doing!

8.3.14 Spi_SetAsyncMode

[SPI188]  ⌈Std_ReturnType Spi_SetAsyncMode( Spi_AsyncModeType Mode )

Service name:
Spi_SetAsyncMode
Syntax:
Std_ReturnType Spi_SetAsyncMode(
  Spi_AsyncModeType Mode
)
Service ID[hex]:
0x0d
Sync/Async:
Synchronous
Reentrancy:
Non Reentrant
Parameters (in):
Mode
New mode required.
Parameters (in-
None
out):
Parameters (out):  None
Return value:
Std_ReturnType
E_OK: Setting command has been done
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E_NOT_OK: setting command has not been accepted
Description:
Service to set the asynchronous mechanism mode for SPI busses handled asyn-
chronously.
⌋()

[SPI335]  ⌈The operation Spi_SetAsyncMode is Non Re-entrant.⌋()

[SPI336]  ⌈Return value of the function Spi_SetAsyncMode is E_OK: Setting com-
mand has been done.⌋()

[SPI337]  ⌈Return value of the function Spi_SetAsyncMode is E_NOT_OK: setting
command has not been accepted.⌋()

[SPI338]  ⌈The function Spi_SetAsyncMode service to set the asynchronous mecha-
nism mode for SPI buses handled asynchronously.⌋()

[SPI152] ⌈The function Spi_SetAsyncMode according to the given parameter shall
set the asynchronous mechanism mode for SPI channels configured to behave
asynchronously.⌋()

[SPI171] ⌈If the function Spi_SetAsyncMode is called while the SPI Handler/Driver
status is SPI_BUSY and an asynchronous transmition is in progress, the SPI Han-
dler/Driver shall not change the AsyncModeType and keep the mode type as it is.
The function shall return the value E_NOT_OK.⌋()

[SPI172] ⌈If  Spi_SetAsyncMode is called while a synchronous transmission is in
progress, the SPI Handler/Driver shall set the AsyncModeType according to parame-
ter 'Mode', even if the SPI Handler/Driver status is SPI_BUSY. The function shall re-
turn the value E_OK.⌋()

[SPI154]  ⌈The function Spi_SetAsyncMode is pre-compile time selectable by the
configuration parameter SpiLevelDelivered. This function is only relevant for
LEVEL 2.⌋()

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8.4  Callback notifications

This chapter lists all functions provided by the SPI module to lower layer modules.

The SPI Handler/Driver module belongs to the lowest layer of AUTOSAR Software
Architecture hence this module specification has not identified any callback functions.

8.5  Scheduled functions

This chapter lists all functions provided by the SPI Handler/Driver and called directly
by the Basic Software Module Scheduler.

The SPI Handler/Driver module requires a scheduled function for the management of
the asynchronous mode managed with polling (see SPI361). The specified functions
below exemplify how to implement them if they are needed.

8.5.1  Spi_MainFunction_Handling

[SPI189]  ⌈void Spi_MainFunction_Handling ( void )

Service name:
Spi_MainFunction_Handling
Syntax:
void Spi_MainFunction_Handling(
  void
)
Service ID[hex]:
0x10
Timing:
FIXED_CYCLIC
Description:
--
⌋()

This function shall polls the SPI interrupts linked to HW Units allocated to the trans-
mission of SPI sequences to enable the evolution of transmission state machine.

8.6  Expected Interfaces

This chapter lists all functions that the SPI Handler/Driver requires from other mod-
ules.
8.6.1  Mandatory Interfaces

The SPI Handler/Driver module does not define any interface which is required to
fulfill its core functionality.

8.6.2  Optional Interfaces

This chapter defines all interfaces which are required to fulfill an optional functionality
of SPI Handler/Driver module.
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[SPI191]  ⌈void Dem_ReportErrorStatus(Dem_EventIdType EventId,
Dem_EventStatusType EventStatus)⌋()

[SPI339]  ⌈void Det_ReportError(uint16 ModuleId, uint8 InstanceId, uint8 ApiId, uint8
ErrorId)

API function
Description
Dem_ReportErrorStatus
Queues the reported events from the BSW modules (API is only used
by BSW modules). The interface has an asynchronous behavior, be-
cause the processing of the event is done within the Dem main function.
Det_ReportError
Service to report development errors.
⌋()

8.6.3  Configurable interfaces

In this chapter all interfaces are listed where the target function could be configured.
The target function is usually a call-back function. The name of these interfaces is not
fixed because they are configurable.

[SPI075]
⌈The SPI Handler/Driver shall use the callback routines
Spi_JobEndNotification to inform other software modules about certain states or
state changes.⌋(BSW157)

[SPI264]
⌈The SPI Handler/Driver shall use the callback routines
Spi_SeqEndNotification to inform other software modules about certain states or
state changes.⌋()

[SPI265]    ⌈For implement the call back function other modules are required to pro-
vide the routines in the expected manner.⌋()

he callback notifications Spi_JobEndNotification
and
Spi_SeqEndNotification as function pointers defined within the initialization da-
ta structure (Spi_ConfigType).⌋(BSW12056)

The callback notifications Spi_JobEndNotification and
Spi_SeqEndNotification shall have no parameters and no return
value.⌋(BSW00359, BSW00360, BSW00369)

[SPI054] ⌈If a callback notification is configured as null pointer, no callback shall be
executed.⌋(BSW12056)

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[SPI085] ⌈It is allowed to use the following API calls within the SPI callback notifica-
tions:
•  Spi_ReadIB
•  Spi_WriteIB
•  Spi_SetupEB
•  Spi_GetJobResult
•  Spi_GetSequenceResult
•  Spi_GetHWUnitStatus
•  Spi_Cancel
All other SPI Handler/Driver API calls are not allowed.⌋()

8.6.3.1  Spi_JobEndNotification

[SPI192]  ⌈void (*Spi_JobEndNotification)( )

Service name:
(*Spi_JobEndNotification)
Syntax:
void (*Spi_JobEndNotification)(
  void
)
Sync/Async:
Synchronous
Reentrancy:
Reentrant
Parameters (in):
None
Parameters (in-
None
out):
Parameters (out):  None
Return value:
None
Description:
Callback routine provided by the user for each Job to notify the caller that a job
has been finished.
⌋()

[SPI340]  ⌈The operation SpiJobEndNotification is Re-entrant.⌋()

[SPI071] ⌈If the SpiJobEndNotification is configured (i.e. not a null pointer), the
SPI Handler/Driver shall call the configured callback notification at the end of a Job
transmission.⌋(BSW157)

Note: This routine might be called on interrupt level, depending on the calling func-
tion.

8.6.3.2  Spi_SeqEndNotification

[SPI193]  ⌈void (*Spi_SeqEndNotification)( )

Service name:
(*Spi_SeqEndNotification)
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Syntax:
void (*Spi_SeqEndNotification)(
  void
)
Sync/Async:
Synchronous
Reentrancy:
Reentrant
Parameters (in):
None
Parameters (in-
None
out):
Parameters (out):  None
Return value:
None
Description:
Callback routine provided by the user for each Sequence to notify the caller that a
sequence has been finished.
⌋()

[SPI341]  ⌈The operation SpiJobEndNotification is Re-entrant.⌋()

[SPI073] ⌈If the SpiSeqEndNotification is configured (i.e. not a null pointer), the
SPI Handler/Driver shall call the configured callback notification at the end of a Se-
quence transmission.⌋(BSW157)

Note: This routine might be called on interrupt level, depending on the calling func-
tion.

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9  Sequence diagrams

9.1  Initialization

Spi User
«module»
Spi
Spi_Init(const
Spi_ConfigType*)
Spi_Init()

9.2  Modes transitions

The following sequence diagram shows an example of an Init / DeInit calls for a run-
ning mode transition.

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Spi User
«module»
Spi
Description:
Initialization of SPI Handler/Driver is
Spi_Init(const
performed synchronously with a
Spi_ConfigType*)
parameter to run in a mode.
Spi_Init()
For instance, "FullPowerConf" is the
structure containing all configurations
for the "RUN State" with PLL enable.
Use of SPI
Handler/Driver:
Embedded software
Spi_GetStatus(Spi_StatusType) :
execution, time and
Spi_StatusType
code execution
undefined during this
Spi_GetStatus=SPI_BUSY()
life period.
Spi_GetStatus(Spi_StatusType) :
Spi_StatusType
Spi_GetStatus=SPI_IDLE()
Description:
Use the get status service of SPI
Handler/Driver to know its state before
to de-initialize it.
Spi_DeInit(Std_ReturnType)
Spi_DeInit()
Spi_Init(const
Description:
Spi_ConfigType*)
Initialization of SPI Handler/Driver is
performed with a specific parameter to run in
Spi_Init()
Use of SPI
another mode.
Handler/Driver:
For instance, "ReducePowerConf" is the
Embedded software
structure containing all configurations for the
execution, time and
"SLEEP State" with PLL disable.
code execution
undefined during this
life period.

9.3 Write/AsyncTransmit/Read (IB)

9.3.1 One Channel, one Job then one Sequence

The following sequence diagram shows an example of Spi_WriteIB /
Spi_AsyncTransmit / Spi_ReadIB calls for a Sequence transmission with only one
Job composed of only one Channel. Write or Read step could be skipped when Job
is just reading or writing respectively.

Example: Channel ID 2 belongs to Job ID 1 which belongs to Sequence ID 0

Sequence
Job
Channel
ID0
ID1
ID2

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V3.2.0
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Spi User
«module»
Spi
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*)
Description:
Write to the Channel is done synchronously.
You pass the Channel ID and the buffer.
Spi_WriteIB()
Spi_AsyncTransmit(Std_ReturnType, Spi_SequenceType)
Description:
Spi_AsyncTransmit()
Transmission is performing asynchronously. The
SPI Handler/Driver records the sequence and
returns.
Description:
Seq0.Job1()
Transmission processing (writing to SPI bus) is
done asynchronously according to the sequence
requested and the prioritization mechanism.
This case is not a Sequence of linked Jobs so
the SPI Handler/Driver becomes idle at the end
of the Channel transmission.
<Spi_Job1EndNotification>()
<Spi_Job1EndNotification>()
Description:
When a Job transmission ends, if it is
<Spi_Seq0EndNotification>()
configured, the “End Job Notification” of the
Job process is called.
<Spi_Seq0EndNotification>()
Description:
Spi_ReadIB(Std_ReturnType, Spi_ChannelType, Spi_DataType**)
When the Sequence transmission ends, if it is
configured, the “End Seq Notification” of the
Sequence process is called.
Spi_ReadIB()
Description:
The received data will be allocated in the
configured receive buffers, and can be read
using the read function for IB Channels.

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V3.2.0
R4.0 Rev 3
9.3.2 Many Channels, one Job then one Sequence

The following sequence diagram shows an example of Spi_WriteIB /
Spi_AsyncTransmit / Spi_ReadIB calls for a Sequence transmission with only one
Job composed of many Channels. Write or Read steps could be skipped when Job is
just reading or writing respectively.

Example: Channels ID 2 & 3 belong to Job ID 1 which belongs to Sequence ID 0

Sequence
Job
Channel
ID2
ID0
ID1
ID3

User1 :Spi User
User2 :Spi User
«module»
Spi
Description:
Write to a Channel is done synchronously. You
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*)
pass the Channel ID and the buffer.
In this case, Channels are within the same Job.
Spi_WriteIB()
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*)
Description:
Spi_WriteIB()
Transmission is performing asynchronously. The
SPI Handler/Driver records the sequence and
returns.
Spi_AsyncTransmit(Std_ReturnType, Spi_SequenceType)
Spi_AsyncTransmit()
Description:
Transmission processing (writing to SPI bus) is
done asynchronously according to the sequence
requested and the prioritization mechanism.
Seq0.Job1()
This case is not a sequence of linked Jobs. At
the end of Channels transmission the SPI
Handler/Driver becomes idle.
<Spi_Job1EndNotification>()
<Spi_Job1EndNotification>()
Description:
When a Job transmission ends, if it is
<Spi_Seq0EndNotification>()
configured, the “End Job Notification” of the
Job process is called.
<Spi_Seq0EndNotification>()
Spi_ReadIB(Std_ReturnType, Spi_ChannelType, Spi_DataType**)
Description:
When the Sequence transmission ends, if it is
Spi_ReadIB()
configured, the “End Seq Notification” of the
Sequence process is called.
Description:
The received data, if there are, will be
allocated in the configured receive buffers,
and can be read using the read function for
IB Channels.

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
9.3.3 Many Channels, many Jobs and one Sequence

The following sequence diagram shows an example of Spi_WriteIB /
Spi_AsyncTransmit / Spi_ReadIB calls for a Sequence transmission of linked Jobs.
Write or Read steps could be skipped when Jobs are just reading or writing respec-
tively.

Example: Channels ID 0 to 3 belong to Job ID 1 (higher priority), Channels ID 4 to 10
belong to Job ID 2 (Lower priority) which has not an end notification function. These
Jobs belong to the same Sequence ID 0

Sequence
Job
Channel
Name
Priority
ID1
High
ID0…ID3
ID0
ID2
Low
ID4…ID10

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
User1 :Spi User
User2 :Spi User
«module»
Spi
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*)
Spi_WriteIB()
loop Channel:=5...10
opt If channel needed
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const
Spi_DataType*)
Spi_WriteIB()
Description:
Write to a Channel is done synchronously. You
pass the Channel ID and the buffer.
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*)
In this case, Channels are not within the same
Job.
Spi_WriteIB()
loop Channel:=1...3
opt If channel needed
Description:
Transmission is performing asynchronously. The
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const
SPI Handler/Driver records the sequence and
Spi_DataType*)
returns.
Spi_WriteIB()
Spi_AsyncTransmit(Std_ReturnType, Spi_SequenceType)
Description:
Transmission processing (writing to SPI bus) is
done asynchronously according to the sequence
Spi_AsyncTransmit()
requested and the prioritization mechanism.
This case is a sequence of linked Jobs. At the
end of Channels transmission the SPI
Handler/Driver becomes idle.
Seq0.Job1()
<Spi_Job1EndNotification>()
<Spi_Job1EndNotification>()
Description:
Seq0.Job2()
When a Job transmission ends, if it is
configured, the “End Job Notification” of the
Job process is called.
<Spi_Seq0EndNotification>()
<Spi_Seq0EndNotification>()
Description:
When the Sequence transmission ends, if it is
configured, the “End Seq Notification” of the
Sequence process is called.
Spi_ReadIB(Std_ReturnType, Spi_ChannelType, Spi_DataType**)
Spi_ReadIB()
Description:
The received data, if there are, will be allocated
in the configured receive buffers, and can be
read using the read function for IB Channels.

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V3.2.0
R4.0 Rev 3
9.3.4 Many Channels, many Jobs and many Sequences

The following sequence diagram shows an example of Spi_WriteIB /
Spi_AsyncTransmit / Spi_ReadIB calls for Sequences transmission. Write or Read
steps could be skipped when Jobs are just reading or writing respectively.

Example: Channels ID 0 to 3 belong to Job ID 1 (high priority 2), Channels ID 4 to 10
belong to Job ID 2 (Low priority 1) which has not an end notification function. These
Jobs belong to the same Sequence ID 0 which is configured as interruptible.
Channels ID 11 to 13 belong to Job ID 0 (higher priority 3) which belongs to Se-
quence ID 1 which is configured as not interruptible.

Sequence
Job
Channel
Name
Interruptible
Name
Priority
ID1
2
ID0…ID3
ID0
Yes
ID2
1
ID4…ID10
ID1
No
ID0
3
ID11…ID13

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
User1 :Spi User
User2 :Spi User
«module»
Spi
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*)
Spi_WriteIB()
loop Channel:=5...10
opt If channel needed
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const
Spi_DataType*)
Spi_WriteIB()
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*)
Spi_WriteIB()
loop Channel:=12...13
Description:
Write to a Channel is done
opt If channel needed
synchronously. You pass the Channel
ID and the buffer.
In this case, Channels are not within
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const
the same Job.
Spi_DataType*)
Spi_WriteIB()
Spi_AsyncTransmit(Std_ReturnType, Spi_SequenceType)
Description:
Transmission is performing
Spi_AsyncTransmit()
asynchronously. The SPI
Handler/Driver records the
sequence and returns.
Seq0.Job1 (part1)
Spi_AsyncTransmit(Std_ReturnType, Spi_SequenceType)
Description:
Spi_AsyncTransmit()
Transmission processing (writing to SPI
bus) is done asynchronously according to
the job requested and the prioritization
mechanism.
Seq0.Job1 (part2)
This case concerns many Sequences of
many Jobs so at the end of a Job
<Spi_Job1EndNotification>()
transmission SPI Handler/Driver schedule
the next Job to transmit.
<Spi_Job1EndNotification>()
The Job selected has the higher priority
and could belong to another Sequence
only if the sequence on going is
configured as interruptible.
Description:
At the end of all Sequences transmission
Seq1.Job0()
When a Job transmission ends, if it is configured, the “End Job
SPI Handler/Driver becomes idle.
Notification” of the Job process is called.
<Spi_Seq1EndNotification>()
<Spi_Seq1EndNotification>()
Spi_ReadIB(Std_ReturnType, Spi_ChannelType, Spi_DataType**)
Spi_ReadIB()
Description:
Seq0.Job2()
When the Sequence
transmission ends, if it is
configured, the “End
<Spi_Seq0EndNotification>()
Seq Notification” of the
Description:
Sequence process is
The received data, if there are, will be
<Spi_Seq0EndNotification>()
called.
allocated in the configured receive
buffers, and can be read using the read
function for IB Channels.
Spi_ReadIB(Spi_ChannelType, Spi_DataType*) :Std_ReturnType
Spi_ReadIB()

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9.4  Setup/AsyncTransmit (EB)

9.4.1  Variable Number of Data / Constant Number of Data

[SPI077]  ⌈To transmit a variable number of data, it is mandatory to call the
Spi_SetupEB  function to store new parameters within SPI Handler/Driver before
each Spi_AsyncTransmit function call.⌋(BSW12198, BSW12200, BSW12201)

[SPI078]  ⌈To transmit a constant number of data, it is only mandatory to call the
Spi_SetupEB function to store parameters within SPI Handler/Driver before the first
Spi_AsyncTransmit function call.⌋(BSW12253, BSW12262, BSW12202)

9.4.2  One Channel, one Job then one Sequence

The following sequence diagram shows an example of Spi_SetupEB  /
Spi_AsyncTransmit  calls for a Sequence transmission with only one Job com-
posed of only one Channel. Write or Read accesses are “User Dependant” and could
be skipped when Job is just reading or writing respectively.

Example: Channel ID 2 belongs to Job ID 1 which belongs to Sequence ID 0

Sequence
Job
Channel
ID0
ID1
ID2

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Spi User
«module»
Spi
Description:
Setup a Channel; initialize buffer pointers
and length synchronously. Parameters are
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
saved.
Spi_NumberOfDataType)
Spi_SetupEB()
Description:
Spi_AsyncTransmit(Std_ReturnType, Spi_SequenceType)
Transmission is performing asynchronously. The
SPI Handler/Driver records the sequence and
returns.
Spi_AsyncTransmit()
Description:
Seq0.Job1()
Transmission processing (writing to SPI bus) is
done asynchronously according to the sequence
requested and the prioritization mechanism.
This case is not a Sequence of linked Jobs so
<Spi_Job1EndNotification>()
the SPI Handler/Driver becomes idle at the end
of the Channel transmission.
<Spi_Job1EndNotification>()
<Spi_Seq0EndNotification>()
<Spi_Seq0EndNotification>()
Description:
When a Job transmission ends, if it is
configured, the “End Job Notification” of the
Job process is called.
Description:
When the Sequence transmission ends, if it is
configured, the “End Seq Notification” of the
Sequence process is called.

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V3.2.0
R4.0 Rev 3

9.4.3  Many Channels, one Job then one Sequence

The following sequence diagram shows an example of Spi_SetupEB  /
Spi_AsyncTransmit  calls for a Sequence transmission with only one Job com-
posed of many Channels. Write or Read accesses are “User Dependant” and could
be skipped when Job is just reading or writing respectively.

Example: Channels ID 2 & 3 belong to Job ID 1 which belongs to Sequence ID 0

Sequence
Job
Channel
ID2
ID0
ID1
ID3

User1 :Spi User
User2 :Spi User
«module»
Spi
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
Spi_NumberOfDataType)
Spi_SetupEB()
Description:
Setup a Channel; initialize buffer pointers
and length synchronously. Parameters are
saved.
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
In this case, Channels are within the same
Spi_NumberOfDataType)
Job.
Spi_SetupEB()
Spi_AsyncTransmit(Std_ReturnType, Spi_SequenceType)
Description:
Transmission is performing asynchronously.
Spi_AsyncTransmit()
The SPI Handler/Driver records the sequence
and returns.
Seq0.Job1()
<Spi_Job1EndNotification>()
Description:
Transmission processing (writing to SPI bus) is
done asynchronously according to the
<Spi_Job1EndNotification>()
sequence requested and the prioritization
mechanism.
This case is not a sequence of linked Jobs. At
the end of Channels transmission the SPI
Handler/Driver becomes idle.
<Spi_Seq0EndNotification>()
<Spi_Seq0EndNotification>()
Description:
When a Job transmission ends, if it is
configured, the “End Job Notification” of the
Job process is called.
Description:
When the Sequence transmission ends, if it is
configured, the “End Seq Notification” of the
Sequence process is called.
The received data, if there are, will be
directly stored in EB Channel receive buffer
and can be used such as.

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
9.4.4  Many Channels, many Jobs and one Sequence

The following sequence diagram shows an example of Spi_SetupEB  /
Spi_AsyncTransmit  calls for a Sequence transmission of linked Jobs. Write or
Read accesses are “User Dependant” and could be skipped when Job is just  read-
ing or writing respectively.

Example: Channels ID 0 to 3 belong to Job ID 1 (higher priority), Channels ID 4 to 10
belong to Job ID 2 (Lower priority) which has not an end notification function. These
Jobs belong to the same Sequence ID 0

Sequence
Job
Channel
ID1
ID0…ID3
ID0
ID2
ID4…ID10

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
User1 :Spi User
User2 :Spi User
«module»
Spi
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
Spi_NumberOfDataType)
Spi_SetupEB()
loop Channel:=5...10
opt If channel needed
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
Spi_NumberOfDataType)
Spi_SetupEB()
Description:
Setup a Channel; initialize buffer pointers
and length synchronously. Parameters are
saved.
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
In this case, Channels are not within the same
Spi_NumberOfDataType)
Job.
Spi_SetupEB()
loop Channel:=1...3
opt If channel needed
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
Spi_NumberOfDataType)
Description:
Spi_SetupEB()
Transmission is performing asynchronously.
The SPI Handler/Driver records the sequence
and returns.
Spi_AsyncTransmit(Std_ReturnType, Spi_SequenceType)
Description:
Spi_AsyncTransmit()
Transmission processing (writing to SPI bus) is
done asynchronously according to the job
requested and the prioritization mechanism.
This case is a Sequence of linked Jobs so at
Seq0.Job1()
the end of a Job transmission SPI
Handler/Driver schedule the next Job to
transmit.
<Spi_Job1EndNotification>()
At the end of Sequence transmission the SPI
Handler/Driver becomes idle.
<Spi_Job1EndNotification>()
Seq0.Job2()
Description:
Description:
When a Job transmission
When the Sequence transmission ends, if it
ends, if it is configured, the
<Spi_Seq0EndNotification>()
is configured, the “End Seq Notification” of
“End Job Notification” of the
the Sequence process is called.
Job process is called.
<Spi_Seq0EndNotification>()
The received data, if there are, will be
directly stored in EB Channel receive buffer
and can be used such as.
Description:
The received data will be allocated in the
configured receive buffers, and can be read
using the read function for IB Channels.

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
9.4.5  Many Channels, many Jobs and many Sequences

The following sequence diagram shows an example of Spi_SetupEB  /
Spi_AsyncTransmit  calls for Sequences transmission. Write or Read accesses
are “User Dependant” and could be skipped when Job is just reading or writing re-
spectively.

Example: Channels ID 0 to 3 belong to Job ID 1 (high priority 2), Channels ID 4 to 10
belong to Job ID 2 (Low priority 1) which has not an end notification function. These
Jobs belong to the same Sequence ID 0 which is configured as interruptible.
Channels ID 11 to 13 belong to Job ID 0 (higher priority 3) which belongs to Se-
quence ID 1 which is configured as not interruptible.

Sequence
Job
Channel
Name
Interruptible
Name
Priority
ID1
2
ID0…ID3
ID0
Yes
ID2
1
ID4…ID10
ID1
No
ID0
3
ID11…ID13

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
User1 :Spi User
User2 :Spi User
«module»
Spi
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
Spi_NumberOfDataType)
Spi_SetupEB()
loop Channel:=5...10
opt If channel needed
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
Spi_NumberOfDataType)
Spi_SetupEB()
Description:
Setup a Channel; initialize buffer pointers
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
and length synchronously. Parameters are
Spi_NumberOfDataType)
saved.
Spi_SetupEB()
In this case, Jobs of those Channels are not
within the same Sequence.
loop Channel:=12...13
opt If channel needed
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
Spi_NumberOfDataType)
Spi_SetupEB()
Description:
Transmission is performing asynchronously.
Spi_AsyncTransmit(Std_ReturnType, Spi_SequenceType)
The SPI Handler/Driver records the sequence
and returns.
Spi_AsyncTransmit()
Description:
Seq0.Job1 (part1)
Transmission processing (writing to SPI bus) is
done asynchronously according to the job
Spi_AsyncTransmit(Std_ReturnType, Spi_SequenceType)
requested and the prioritization mechanism.
This case concerns many Sequences of many
Jobs so at the end of a Job transmission SPI
Spi_AsyncTransmit()
Handler/Driver schedule the next Job to
transmit.
The Job selected has the higher priority and
could belong to another Sequence only if the
Seq0.Job1 (part2)
sequence on going is configured as
interruptible.
<Spi_Job1EndNotification>()
At the end of all Sequences transmission SPI
Handler/Driver becomes idle.
<Spi_Job1EndNotification>()
Seq1.Job0()
<Spi_Seq1EndNotification>()
Description:
<Spi_Seq1EndNotification>()
When a Job transmission ends, if it is
configured, the “End Job Notification” of the
Job process is called.
Seq0.Job2()
Description:
<Spi_Seq0EndNotification>()
When the Sequence transmission ends, if it is
configured, the “End Seq Notification” of the
<Spi_Seq0EndNotification>()
Sequence process is called.
The received data, if there are, will be
directly stored in EB Channel receive buffer
and can be used such as.

9.5 Mixed Jobs Transmission

All kind of mixed Jobs transmission is possible according to the Channels configura-
tion and the priority requirement inside Sequences.

The user knows which Channels are in use. Then, according to the types of these
Channels, the appropriate methods shall be called.
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V3.2.0
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9.6 LEVEL 0 SyncTransmit diagrams

9.6.1 Write/SyncTransmit/Read (IB): Many Channels, many Jobs and one
Sequence

The following sequence diagram shows an example of Spi_WriteIB /
Spi_SyncTransmit / Spi_ReadIB calls for a Sequence transmission of linked Jobs.
Write or Read steps could be skipped when Jobs are just reading or writing respec-
tively.

Example: Channels ID 0 to 3 belong to Job ID 1 (higher priority), Channels ID 4 to 10
belong to Job ID 2 (Lower priority). These Jobs belong to the same Sequence ID 0

Sequence
Job
Channel
Name
Priority
ID1
High
ID0…ID3
ID0
ID2
Low
ID4…ID10

User1 :Spi User
User2 :Spi User
«module»
Spi
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*)
Spi_WriteIB()
loop Channel:=5...10
opt If channel needed
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const
Spi_DataType*)
Spi_WriteIB()
Write to a Channel is done
synchronously. You pass the
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*)
Channel ID and the buffer.
In this case, Channels are not
Spi_WriteIB()
within the same Job.
loop Channel:=1...3
opt If channel needed
Spi_WriteIB(Std_ReturnType, Spi_ChannelType, const
Spi_DataType*)
Spi_WriteIB()
Transmission is performing
synchronously. The SPI
Handler/Driver transmits the
complete Sequence and it
returns. At the end of Sequence
Spi_SyncTransmit(Std_ReturnType, Spi_SequenceType)
transmission, the SPI
Handler/Driver becomes idle.
Seq0.Job1()
Seq0.Job2()
The received data, if there are,
Spi_SyncTransmit()
will be allocated in the
configured receive buffers, and
Spi_ReadIB(Std_ReturnType, Spi_ChannelType, Spi_DataType**)
can be read using the read
function for IB Channels.
Spi_ReadIB()

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V3.2.0
R4.0 Rev 3
9.6.2  Setup/SyncTransmit (EB): Many Channels, many Jobs and one
Sequence

The following sequence diagram shows an example of Spi_SetupEB  /
Spi_SyncTransmit  calls for a Sequence transmission of linked Jobs. Write or
Read accesses are “User Dependant” and could be skipped when Job is just  read-
ing or writing respectively.

Example: Channels ID 0 to 3 belong to Job ID 1 (higher priority), Channels ID 4 to 10
belong to Job ID 2 (Lower priority). These Jobs belong to the same Sequence ID 0

Sequence
Job
Channel
ID1
ID0…ID3
ID0
ID2
ID4…ID10

User1 :Spi User
User2 :Spi User
«module»
Spi
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
Spi_NumberOfDataType)
Spi_SetupEB()
loop Channel:=5...10
opt If channel needed
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
Spi_NumberOfDataType)
Spi_SetupEB()
Setup a Channel; initialize
buffer pointers and length
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
synchronously. Parameters are
Spi_NumberOfDataType)
saved. In this case, Channels are
not within the same Job.
Spi_SetupEB()
loop Channel:=1...3
opt If channel needed
Spi_SetupEB(Std_ReturnType, Spi_ChannelType, const Spi_DataType*, Spi_DataType*,
Spi_NumberOfDataType)
Spi_SetupEB()
Transmission is performing
synchronously. The SPI
Handler/Driver transmits the
complete Sequence and it
returns. At the end of Sequence
transmission, the SPI
Spi_SyncTransmit(Std_ReturnType, Spi_SequenceType)
Handler/Driver becomes idle.
Seq0.Job1()
Seq0.Job2()
Description:
Spi_SyncTransmit()
The received data, if there are,
will be directly stored in EB
Channel receive buffer and can
be used such as.

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10 Configuration specification

10.1 How to read this chapter

In addition to this section, it is highly recommended to read the documents:
-  AUTOSAR Layered Software Architecture [1]
-  AUTOSAR ECU Configuration Specification [5]
This document describes the AUTOSAR configuration methodology and the
AUTOSAR configuration metamodel in detail.

The following is only a short survey of the topic and it will not replace the ECU Con-
figuration Specification document.

10.1.1 Configuration and configuration parameters

Configuration parameters define the variability of the generic part(s) of an implemen-
tation of a module. This means that only generic or configurable module implementa-
tion can be adapted to the environment (software/hardware) in use during system
and/or ECU configuration.

The configuration of parameters can be achieved at different times during the soft-
ware process: before compile time, before link time or after build time. In the follow-
ing, the term “configuration class” (of a parameter) shall be used in order to refer to a
specific configuration point in time.

10.1.2 Containers

Containers structure the set of configuration parameters. This means:
-  all configuration parameters are kept in containers.
-  (sub-) containers can reference (sub-) containers. It is possible to assign a
multiplicity to these references. The multiplicity then defines the possible num-
ber of instances of the contained parameters.

10.1.3 Specification template for configuration parameters

The following tables consist of three sections:
-  the general section
-  the configuration parameter section
-  the section of included/referenced containers

Pre-compile time
-  specifies whether the configuration parameter shall be
of configuration class Pre-compile time or not

Label
Description
x
The configuration parameter shall be of configuration class Pre-compile time.
--
The configuration parameter shall never be of configuration class Pre-compile time.
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Link time
-  specifies whether the configuration parameter shall be
of configuration class Link time or not

Label
Description
x
The configuration parameter shall be of configuration class Link time.
--
The configuration parameter shall never be of configuration class Link time.

Post Build
-  specifies whether the configuration parameter shall be
of configuration class Post Build or not

Label
Description
The configuration parameter shall be of configuration class Post Build and no specific
x
implementation is required.
Loadable - the configuration parameter shall be of configuration class Post Build and only
L
one configuration parameter set resides in the ECU.
Multiple - the configuration parameter shall be of configuration class Post Build and is
M
selected out of a set of multiple parameters by passing a dedicated pointer to the init func-
tion of the module.
--
The configuration parameter shall never be of configuration class Post Build.
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10.2 Containers and configuration parameters

The following chapters summarize all configuration parameters. The detailed mean-
ings of the parameters are described in Chapter 7 and Chapter 8. Further hardware /
implementation specific parameters can be added if necessary.

10.2.1 Variants

[SPI056]  ⌈VARIANT-PRE-COMPILE: Only parameters with "Pre-compile time" con-
figuration are allowed in this variant.⌋(BSW00345,  BSW00350, BSW00396,
BSW00397)

[SPI076] ⌈VARIANT-LINK-TIME: Only parameters with "Pre-compile time" and "Link
time" are allowed in this variant.⌋(BSW00396, BSW00398, BSW00405, BSW12263)

[SPI148]  ⌈VARIANT-POST-BUILD: Parameters with "Pre-compile time", "Link time"
and "Post-build time" are allowed in this variant.⌋(BSW00404, BSW00405)

[SPI234] ⌈The initialization function of this module shall always have a pointer as a
parameter, even though for Variant PC no configuration set shall be given. Instead a
NULL pointer shall be passed to the initialization function.⌋()

[SPI235]  ⌈If not applicable, the SPI Handler/Driver module’s environment shall pass
a NULL pointer to the function Spi_Init.⌋()

10.2.2 Spi
SWS Item
SPI103_Conf :
Module Name
Spi
Module Description
Configuration of the Spi (Serial Peripheral Interface) module.

Included Containers
Container Name
Multiplicity  Scope / Dependency
Configuration of one instance (if multiplicity is 1, it is the sole
SpiDriver
1
configuration) of an SPI driver.
SpiGeneral
1
General configuration settings for SPI-Handler
Container holding all SPI specific published information pa-
SpiPublishedInformation
1
rameters


10.2.3 SpiGeneral
SWS Item
SPI225_Conf :
Container Name
SpiGeneral
Description
General configuration settings for SPI-Handler
Configuration Parameters

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SWS Item
SPI226_Conf :
Name
SpiCancelApi {SPI_CANCEL_API}

Description
Switches the Spi_Cancel function ON or OFF.
Multiplicity
1
Type
EcucBooleanParamDef
Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency
scope: module

SWS Item
SPI227_Conf :
Name
SpiChannelBuffersAllowed {SPI_CHANNEL_BUFFERS_ALLOWED}

Description
Selects the SPI Handler/Driver Channel Buffers usage allowed and
delivered. IB = 0; EB = 1; IB/EB = 2;
Multiplicity
1
Type
EcucIntegerParamDef
Range
0 .. 2

Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency
scope: module

SWS Item
SPI228_Conf :
Name
SpiDevErrorDetect {SPI_DEV_ERROR_DETECT}

Description
Switches the Development Error Detection and Notification
ON or OFF.
Multiplicity
1
Type
EcucBooleanParamDef
Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency
scope: module

SWS Item
SPI229_Conf :
Name
SpiHwStatusApi {SPI_HW_STATUS_API}

Description
Switches the Spi_GetHWUnitStatus function ON or OFF.
Multiplicity
1
Type
EcucBooleanParamDef
Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency
scope: module

SWS Item
SPI230_Conf :
Name
SpiInterruptibleSeqAllowed

{SPI_INTERRUPTIBLE_SEQ_ALLOWED}
Description
Switches the Interruptible Sequences handling functionality ON or
OFF.
Multiplicity
1
Type
EcucBooleanParamDef
Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
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Link time
--
Post-build time
--
Scope / Dependency
scope: module
dependency: This parameter depends on SPI_LEVEL_DELIVERED
value. It is only
used for SPI_LEVEL_DELIVERED configured to 1 or 2.

SWS Item
SPI231_Conf :
Name
SpiLevelDelivered {SPI_LEVEL_DELIVERED}

Description
Selects the SPI Handler/Driver level of scalable functional-
ity that is available and delivered.
Multiplicity
1
Type
EcucIntegerParamDef
Range
0 .. 2

Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency
scope: module

SWS Item
SPI237_Conf :
Name
SpiSupportConcurrentSyncTransmit

{SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT}
Description
Specifies whether concurrent Spi_SyncTransmit() calls for different se-
quences shall be configurable.
Multiplicity
1
Type
EcucBooleanParamDef
Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency
scope: module

SWS Item
SPI232_Conf :
Name
SpiVersionInfoApi {SPI_VERSION_INFO_API}

Description
Switches the Spi_GetVersionInfo function ON or OFF.
Multiplicity
1
Type
EcucBooleanParamDef
Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency
scope: module

No Included Containers


10.2.4 SpiSequence
SWS Item
SPI106_Conf :
Container Name
SpiSequence{SpiSequenceConfiguration}
Description
All data needed to configure one SPI-sequence
Configuration Parameters

SWS Item
SPI222_Conf :
Name
SpiInterruptibleSequence {SPI_INTERRUPTIBLE_SEQUENCE}

Description
This parameter allows or not this Sequence to be suspended by an-
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other one.
Multiplicity
1
Type
EcucBooleanParamDef
Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module
dependency: This SPI_INTERRUPTIBLE_SEQ_ALLOWED parame-
ter as to be
configured as ON.

SWS Item
SPI223_Conf :
Name
SpiSeqEndNotification {SPI_SEQ_END_NOTIFICATION}

Description
This parameter is a reference to a notification function.
Multiplicity
0..1
Type
EcucFunctionNameDef
Default value
--
maxLength
--
minLength
--
regularExpression
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: ECU

SWS Item
SPI224_Conf :
Name
SpiSequenceId {SPI_SEQUENCE_NAME}

Description
SPI Sequence ID, used as parameter in SPI API functions.
Multiplicity
1
Type
EcucIntegerParamDef (Symbolic Name generated for this
parameter)
Range
0 .. 255

Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency
scope: ECU

SWS Item
SPI221_Conf :
Name
SpiJobAssignment {SPI_JOB_LINKING}

Description
A sequence references several jobs, which are exe-
cuted during a communication sequence
Multiplicity
1..*
Type
Reference to [ SpiJob ]
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: ECU

No Included Containers


10.2.5 SpiChannel
SWS Item
SPI104_Conf :
Container Name
SpiChannel{SpiChannelConfiguration}
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Description
All data needed to configure one SPI-channel
Configuration Parameters

SWS Item
SPI200_Conf :
Name
SpiChannelId {SPI_CHANNEL_NAME}

Description
SPI Channel ID, used as parameter in SPI API functions.
Multiplicity
1
Type
EcucIntegerParamDef (Symbolic Name generated for
this parameter)
Range
0 .. 255

Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency
scope: ECU

SWS Item
SPI201_Conf :
Name
SpiChannelType {SPI_CHANNEL_TYPE}

Description
Buffer usage with EB/IB channel.
Multiplicity
1
Type
EcucEnumerationParamDef
Range
EB
External Buffer
IB
Internal Buffer
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: ECU
dependency: SPI_CHANNEL_BUFFERS_ALLOWED

SWS Item
SPI202_Conf :
Name
SpiDataWidth {SPI_DATA_WIDTH}

Description
This parameter is the width of a transmitted data unit.
Multiplicity
1
Type
EcucIntegerParamDef
Range
1 .. 32

Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

SWS Item
SPI203_Conf :
Name
SpiDefaultData {SPI_DEFAULT_DATA}

Description
The default data to be transmitted when (for internal
buffer or external buffer) the pointer passed to
Spi_WriteIB (for internal buffer) or to Spi_SetupEB (for
external buffer) is NULL.
Multiplicity
0..1
Type
EcucIntegerParamDef
Range
0 .. 4294967295

Default value
--
ConfigurationClass
Pre-compile time
X  VARIANT-PRE-
COMPILE
Link time
X  VARIANT-LINK-TIME
Post-build time
X  VARIANT-POST-BUILD
Scope / Dependency
scope: module
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SWS Item
SPI204_Conf :
Name
SpiEbMaxLength {SPI_EB_MAX_LENGTH}

Description
This parameter contains the maximum size (in bytes) of data buffers
in case of EB Channels and only.
Multiplicity
1
Type
EcucIntegerParamDef
Range
0 .. 65535

Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module
dependency: The SPI_CHANNEL_TYPE parameter has to be con-
figured as EB for this Channel.
The SPI_CHANNEL_BUFFERS_ALLOWED parameter has to be
configured as 1 or 2.

SWS Item
SPI205_Conf :
Name
SpiIbNBuffers {SPI_IB_N_BUFFERS}

Description
This parameter contains the maximum number of data buffers in
case of IB Channels and only.
Multiplicity
1
Type
EcucIntegerParamDef
Range
0 .. 65535

Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module
dependency: The SPI_CHANNEL_TYPE parameter has to be con-
figured as IB for this Channel. The
SPI_CHANNEL_BUFFERS_ALLOWED parameter has to be config-
ured as 0 or 2.

SWS Item
SPI206_Conf :
Name
SpiTransferStart {SPI_TRANSFER_START}

Description
This parameter defines the first starting bit for transmission.
Multiplicity
1
Type
EcucEnumerationParamDef
Range
LSB
Transmission starts with the Least
Significant Bit first
MSB
Transmission starts with the Most
Significant Bit first
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

No Included Containers


10.2.6 SpiChannelList
SWS Item
SPI233_Conf :
Container Name
SpiChannelList{SpiChannelList}
Description
References to SPI channels and their order within the Job.
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Configuration Parameters

SWS Item
SPI234_Conf :
Name
SpiChannelIndex

Description
This parameter specifies the order of Channels within
the Job.
Multiplicity
1
Type
EcucIntegerParamDef
Range
0 .. 255

Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: ECU

SWS Item
SPI215_Conf :
Name
SpiChannelAssignment {SPI_CHANNEL_LINKING}

Description
A job reference to a SPI channel.
Multiplicity
1
Type
Reference to [ SpiChannel ]
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: ECU

No Included Containers


10.2.7 SpiJob
SWS Item
SPI105_Conf :
Container Name
SpiJob{SpiJobConfiguration}
All data needed to configure one SPI-Job, amongst others the connec-
Description
tion between the internal SPI unit and the special settings for an external
device is done.
Configuration Parameters

SWS Item
SPI238_Conf :
Name
SpiHwUnitSynchronous {SPI_HW_UNIT_SYNCHRONOUS}

Description
If SpiHwUnitSynchronous is set to "SYNCHRONOUS", the SpiJob
uses its containing SpiDriver in a synchronous manner. If it is set
to "ASYNCHRONOUS", it uses the driver in an asynchronous
way. If the parameter is not set, the SpiChannel uses the driver
also in an asynchronous way.
Multiplicity
0..1
Type
EcucEnumerationParamDef
Range
ASYNCHRONOUS
--
SYNCHRONOUS
--
ConfigurationClass
Pre-compile time
X  VARIANT-PRE-
COMPILE
Link time
X  VARIANT-LINK-TIME
Post-build time
X  VARIANT-POST-
BUILD
Scope / Dependency
scope: module

SWS Item
SPI218_Conf :
Name
SpiJobEndNotification {SPI_JOB_END_NOTIFICATION}

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Description
This parameter is a reference to a notification function.
Multiplicity
0..1
Type
EcucFunctionNameDef
Default value
--
maxLength
--
minLength
--
regularExpression
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

SWS Item
SPI219_Conf :
Name
SpiJobId {SPI_JOB_NAME}

Description
SPI Job ID, used as parameter in SPI API functions.
Multiplicity
1
Type
EcucIntegerParamDef (Symbolic Name generated for
this parameter)
Range
0 .. 65535

Default value
--
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency
scope: ECU

SWS Item
SPI220_Conf :
Name
SpiJobPriority {SPI_JOB_PRIORITY}

Description
Priority set accordingly to SPI093: 0, lowest, 3, highest
priority
Multiplicity
1
Type
EcucIntegerParamDef
Range
0 .. 3

Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

SWS Item
SPI216_Conf :
Name
SpiDeviceAssignment

Description
Reference to the external device used by this job
Multiplicity
1
Type
Reference to [ SpiExternalDevice ]
ConfigurationClass
Pre-compile time
X   All Variants
Link time
--
Post-build time
--
Scope / Dependency


Included Containers
Container
Multiplicity
Scope / Dependency
Name
SpiChannel-
1..*
References to SPI channels and their order within the Job.
List

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10.2.8 SpiExternalDevice
SWS Item
SPI207_Conf :
Container Name
SpiExternalDevice
The communication settings of an external device. Closely
Description
linked to SpiJob.
Configuration Parameters

SWS Item
SPI208_Conf :
Name
SpiBaudrate {SPI_BAUDRATE}

Description
This parameter is the communication baudrate -
This parameter allows using a range of values, from
the point of view of configuration tools, from Hz up to
MHz.
Multiplicity
1
Type
EcucFloatParamDef
Range
0 .. INF

Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

SWS Item
SPI209_Conf :
Name
SpiCsIdentifier {SPI_CS_IDENTIFIER}

Description
This parameter is the symbolic name to identify the
Chip Select (CS) allocated to this Job.
Multiplicity
1
Type
EcucStringParamDef (Symbolic Name generated for
this parameter)
Default value
--
maxLength
--
minLength
--
regularExpression
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

SWS Item
SPI210_Conf :
Name
SpiCsPolarity {SPI_CS_POLARITY}

Description
This parameter defines the active polarity of Chip Select.
Multiplicity
1
Type
EcucEnumerationParamDef
Range
HIGH
--
LOW
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

SWS Item
SPI239_Conf :
Name
SpiCsSelection {SPI_CS_SELECTION}

Description
When the Chip select handling is enabled (see SpiEnableCs), then this
parameter specifies if the chip select is handled automatically by Pe-
ripheral HW engine or via general purpose IO by Spi driver.
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Multiplicity
0..1
Type
EcucEnumerationParamDef
Range
CS_VIA_GPIO
chip select handled
via gpio by Spi
driver.
CS_VIA_PERIPHERAL_ENGINE
chip select is han-
dled automatically
by Peripheral HW
engine.
(default)
ConfigurationClass
Pre-compile time
X  VARIANT-PRE-
COMPILE
Link time
X  VARIANT-LINK-
TIME
Post-build time
X  VARIANT-POST-
BUILD
Scope / Dependency
scope: module
dependency: SpiEnableCs

SWS Item
SPI211_Conf :
Name
SpiDataShiftEdge {SPI_DATA_SHIFT_EDGE}

Description
This parameter defines the SPI data shift edge.
Multiplicity
1
Type
EcucEnumerationParamDef
Range
LEADING
--
TRAILING
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

SWS Item
SPI212_Conf :
Name
SpiEnableCs {SPI_ENABLE_CS}

Description
This parameter enables or not the Chip Select handling
functions. If this parameter is enabled then parameter
SpiCsSelection further details the type of chip selec-
tion.
Multiplicity
1
Type
EcucBooleanParamDef
Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

SWS Item
SPI217_Conf :
Name
SpiHwUnit {SPI_HW_UNIT}

Description
This parameter is the symbolic name to identify the HW SPI
Hardware microcontroller peripheral allocated to this Job.
Multiplicity
1
Type
EcucEnumerationParamDef
Range
CSIB0
--
CSIB1
--
CSIB2
--
CSIB3
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
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Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

SWS Item
SPI213_Conf :
Name
SpiShiftClockIdleLevel {SPI_SHIFT_CLOCK_IDLE_LEVEL}

Description
This parameter defines the SPI shift clock idle level.
Multiplicity
1
Type
EcucEnumerationParamDef
Range
HIGH
--
LOW
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

SWS Item
SPI214_Conf :
Name
SpiTimeClk2Cs {SPI_TIME_CLK2CS}

Description
Timing between clock and chip select (in seconds) -
This parameter allows to use a range of values from
0 up to 0.0001 seconds. The real configuration-value
used in software BSW-SPI is calculated out of this by
the generator-tools
Multiplicity
1
Type
EcucFloatParamDef
Range
0 .. 1E-4

Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency
scope: module

No Included Containers


10.2.9 SpiDriver
SWS Item
SPI091_Conf :
Container Name
SpiDriver{SpiDriverConfiguration} [Multi Config Container]
Configuration of one instance (if multiplicity is 1, it is the sole configuration)
Description
of an SPI driver.
Configuration Parameters

SWS Item
SPI197_Conf :
Name
SpiMaxChannel {SPI_MAX_CHANNEL}

Description
This parameter contains the number of Channels con-
figured. It will be gathered by tools during the configu-
ration stage.
Multiplicity
0..1
Type
EcucIntegerParamDef
Range
0 .. 255

Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency


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V3.2.0
R4.0 Rev 3
SWS Item
SPI198_Conf :
Name
SpiMaxJob {SPI_MAX_JOB}

Description
Total number of Jobs configured.
Multiplicity
0..1
Type
EcucIntegerParamDef
Range
0 .. 65535

Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency


SWS Item
SPI199_Conf :
Name
SpiMaxSequence {SPI_MAX_SEQUENCE}

Description
Total number of Sequences configured.
Multiplicity
0..1
Type
EcucIntegerParamDef
Range
0 .. 255

Default value
--
ConfigurationClass
Pre-compile time
X   VARIANT-PRE-COMPILE
Link time
X   VARIANT-LINK-TIME
Post-build time
X   VARIANT-POST-BUILD
Scope / Dependency


Included Containers
Container Name
Multiplicity  Scope / Dependency
SpiChannel
1..*
All data needed to configure one SPI-channel
Container for the references to DemEventParameter elements
which shall be invoked using the API Dem_ReportErrorStatus
SpiDemEventParameter-
API in case the corresponding error occurs. The EventId is
0..1
Refs
taken from the referenced DemEventParameter's DemEventId
value. The standardized errors are provided in the container
and can be extended by vendor specific error references.
The communication settings of an external device. Closely
SpiExternalDevice
1..*
linked to SpiJob.
All data needed to configure one SPI-Job, amongst others the
SpiJob
1..*
connection between the internal SPI unit and the special set-
tings for an external device is done.
SpiSequence
1..*
All data needed to configure one SPI-sequence

10.2.10
SpiPublishedInformation
SWS Item
SPI235_Conf :
Container Name
SpiPublishedInformation
Description
Container holding all SPI specific published information parameters
Configuration Parameters

SWS Item
SPI236_Conf :
Name
SpiMaxHwUnit

Description
Number of different SPI hardware microcontroller peripherals
(units/busses) available and handled by this SPI Handler/Driver module.
Multiplicity
1
Type
EcucIntegerParamDef
Range
0 ..

18446744073709551615
Default value
--
ConfigurationClass
Published Information
X   All Variants
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Scope / Dependency


No Included Containers


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V3.2.0
R4.0 Rev 3
10.3  Published information

[SPI089]  ⌈The following description  specifies information that is published in the
module’s header file Spi.h or in the module’s description file. Published information
contains data defined by the implementer of the SW module that does not change
when the module is adapted (i.e. configured) to the actual HW/SW environment. It
thus contains version and manufacturer information.⌋(BSW003,  BSW00374,
BSW00379, BSW0402, BSW158)

[SPI068]  ⌈The standardized common published parameters as required by
BSW00402 in the General Requirements on Basic Software Modules [3]shall be pub-
lished within the header file of this module and need to be provided in the BSW Mod-
ule Description. The according module abbreviation can be found in the List of Basic
Software Modules [12].⌋(BSW003, BSW00318, BSW00321, BSW00374, BSW00379,
BSW00390, BSW00391, BSW0402)

Additional module-specific published parameters are listed below if applicable.”

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V3.2.0
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10.4 Configuration concept

There is a relationship between the SPI Handler/Driver module and the modules that
use it. This relationship is resolved during the configuration stage and the result of it
influences the proper API and behaviour between those modules.

The user needs to provide to the SPI Handler/Driver part of the configuration to adapt
it to its necessities. The SPI Handler/Driver shall take this configuration and provide
the needed tools to the user.

The picture shows the information flow during the configuration of the SPI Han-
dler/Driver. It is shown only for one user, using an External EEPROM Driver as ex-
ample, but this situation is common to all users of the SPI Handler/Driver. To high-
light the situation where more users are affected, several overlapping documents are
drawn.

Basic software
responsable
EEPROM External
Configures
Driver responsable
SPI Handler/Driver full
configuration
Configuration
Tool
Part of SPI configuration
Spi_Cfg.c
Generates
Imported
Configures
Imported
Includes
Spi_Cfg.h
XML
XML
Hardware ECU Resources
User driver XML sheet
containing all hardware
(e.g: EEPROM External
configuration
Driver)
(e.g: Number of SPI
buses, list of all CS)
Includes
Eep_Cfg.c
Publishes
Includes
User of SPI Handler/Driver (e.g: External EEPROM Driver)
Eep.c
Eep.h
Eep_Cfg.h
Includes
Includes

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The steps on the diagrams are:

1.  The user (External EEPROM Driver) of SPI Handler/Driver edits a XML con-
figuration file. This XML configuration file is the same used by the user to gen-
erate its own configuration.
2.  For each ECU, a XML HW configuration document contains information which
should be used in order to configure some parameters.
3.  The “SPI generation tool”. The Generation tool (here is reflected only the part
that generates code to SPI usage) shall generate the handles to export and
the instance of the configuration sets. In this step the software integrator  will
provide missing information.
4.  SPI instance configuration file. As a result of the generation all the symbolic
handlers needed by the user are included in the configuration header file of
the SPI Handler/Driver.
5.  User gets the symbolic name of handlers. User imports the handle generated
to make use of them as requested by its XML configuration file.
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11 Not applicable requirements
[SPI999] ⌈ These requirements are not applicable to this specification. ⌋ (BSW00301,
BSW00302, BSW00306, BSW00307, BSW00308, BSW00309, BSW00312,
BSW00324, BSW00325, BSW00326, BSW00328, BSW00330, BSW00331,
BSW00334, BSW00341, BSW00342, BSW00343, BSW00347, BSW00355,
BSW00375, BSW00399, BSW00400, BSW00401, BSW00413, BSW00416,
BSW00417, BSW00420, BSW00422, BSW00423, BSW00424, BSW00426,
BSW00427, BSW00428, BSW00429, BSW00431, BSW00432, BSW00433,
BSW00434, BSW005, BSW006, BSW009, BSW010, BSW161, BSW164, BSW168,
BSW170, BSW172, BSW12267, BSW12068, BSW12069, BSW12063, BSW12129,
BSW12067, BSW12077, BSW12078, BSW12092, BSW12265)
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V3.2.0
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12 Appendix

The table shown on the next page is just an example to help future users (and/or de-
velopers) that have to configure software modules to use the SPI Handler/Driver.
This table is independent of the Spi_ConfigType structure but contains all ele-
ments and aggregations like Channels, Jobs and Sequences.

EEP_WRITE_SEQ
EEP_READ_SEQ
EEP_CMD_JOB
EEP_DATA_JOB
EEP_CMD_CH
EEP_ADR_CH
EEP_DATA_CH

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External EEPROM Write/Read Configuration for SPI Handler/Driver
Sequences
Jobs
Channels
Symbolic Name
ID
Attributes
Symbolic Name
ID
Attributes
Symbolic Name
ID
Attributes
SPI_BUS_0,
CS_EEPROM,
CS_ON,
CS_LOW,
2 (Number of Jobs),
EB,
CLK_2MHz,
{EEP_CMD_JOB,
8 bits,
1 (time in µs),
EEP_DATA_JOB} (List of
1 data to TxD,
EEP_WRITE_SEQ
0
EEP_CMD_JOB
0  Polarity 180,
EEP_CMD_CH
0
Jobs),
MSB First,
Falling Edge,
Not Interruptible,
Default value is
3,
EEP_vidEndOfWriteSeq
0x00
EEP_vidEndOfStartWrJob,
1 (Number of Channels)
{EEP_CMD_CH} (List of Chan-
nels)
SPI_BUS_0,
CS_EEPROM,
CS_ON,
CS_LOW,
CLK_2MHz,
EB,
1 (Number of Jobs),
1 (time in µs),
16 bits,
{EEP_DATA_JOB} (List of
Polarity 180,
1 data to TxD,
EEP_READ_SEQ
1  Jobs),
EEP_DATA_JOB
1
EEP_ADR_CH
1
Falling Edge,
MSB First,
Not Interruptible,
2,
Default value is
EEP_vidEndOfReadSeq
NULL,
0x0000
3 (Number of Channels)
{EEP_CMD_CH, EEP_ADR_CH,
EEP_DATA_CH} (List of Chan-
nels)
EB,
8 bits,
32 data to TxD,
EEP_DATA_CH
2  MSB First,
Default value is



0x00

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V3.2.0
R4.0 Rev 3
13  Changes to Release 1

13.1  Deleted SWS Items

SWS Item
Rationale
SPI090
Redundant with the new version of SPI089

13.2  Replaced SWS Items

SWS Item of Re-
replaced by
Rationale
lease 1
SWS Item
SPI056
SPI056, SPI103
To split the old requirement into two require-
ments to fit to the new SWS template with con-
tainers and variants.
SPI053
SPI053, SPI112
To split the old requirement into two require-
ments to improve the testability. Description for
the maximum size of External Buffers.

13.3  Changed SWS Items

SWS Item
Rationale
SPI089
To take in account the new template sentence to describe requirement.
To take in account the new template location and sentence to describe
SPI029
requirement.
SPI092
Clarify the structure of includes files as described in new template.
SPI076
To take in account the new SWS template with variants.
SPI091
To take in account the new SWS template with containers definitions.
SPI001
To take in account the scalabilty with Levels of Functionalities concept.
SPI014
Improvement for interruptible sequences behavior.
SPI021
Changes
SPI052
Changes
SPI031, SPI032,
Changes to fulfill BSW12448
SPI060, SPI046
SPI103
After creation, add of new parameters for pre-compile time configuration
SPI044
Changed to fulfill a requirement concerning object code delivery
SPI085
To add new interfaces
SPI020
Delete the Job result setting from this service.
SPI094
Fulfill the SWS template

13.4  Added SWS Items

SWS Item
Rationale
Additional requirement to identify the table of published parameters and
SPI094
creation of new parameters.
SPI095
New item to fullfil the required code file structure.
SPI096
New item to describe the relationship with the Dem module.
SPI097
New item to describe Dem Ids allocation rules.
SPI098
Clarify development errors C type.
SPI099
New requirement to the production errors detection.
SPI100
Clarify development errors reporting.
SPI101
New item for Spi_GetVersionInfo service description.
SPI102
New item for Spi_GetVersionInfo configuration rules.
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SPI104
Creation of SpiChannel container with all its parameters.
SPI105
Creation of SpiJobConfiguration container with all its parameters.
SPI106
Creation of SpiSequence with all its parameters.
SPI108
Restriction to LEVEL 2 usage at microcontrollers with more than 1 SPI bus.
SPI109
The level is selected at pre-compile time.
SPI110
Define the parameter to configure level of functionality.
SPI111
Define the parameter to configure buffers usage IB / EB / Both.
SPI113
Global requirement for the LEVEL 0 synchronous behavior.
SPI114
Multiple sequences transmission restriction for synchronous level.
SPI115
Requirement to include buffers usage in LEVEL 0.
SPI116
Multiple sequences transmission acceptance rule for asynchronous level.
Requirement to include buffers usage and interruptible sequences in LEV-
SPI117
EL 1.
SPI118
Requirement for End Notification Function.
SPI119
Additional requirement for Job end notification.
SPI120
Additional requirement for Sequence end notification.
SPI121
Define the parmeter to configure interruptible sequences.
SPI122
Description of behavior in case of interruptible sequences disabled.
SPI123
Additional requirement in case of interruptible sequences disabled.
SPI124
Additional requirement in case of interruptible sequences disabled.
SPI125
Description of behavior in case of interruptible sequences enabled.
SPI126
Additional requirement in case of interruptible sequences enabled.
SPI127
Additional requirement in case of interruptible sequences enabled.
Global requirement for the LEVEL 2 synchronous and asynchronous be-
SPI128
havior.
SPI129
Description for the prearrange SPI bus for synchronous transmissions..
SPI130
Description of a so-called synchronous sequence.
SPI131
Restrictions to Jobs linkage within a Sequence.
SPI133
Spi_AsyncTransmit() configuration dependance.
SPI134
Spi_SyncTransmit() main behavior requirement.
SPI135
Spi_SyncTransmit() re-entrance behavior requirement.
SPI136
Spi_SyncTransmit() configuration dependance.
SPI137
Spi_WriteIB() configuration dependance.
SPI138
Spi_ReadIB() configuration dependance.
SPI139
Spi_SetupEB() configuration dependance.
Creation of API interface Spi_GetHWUnitStatus to get the status of a
SPI141
specified SPI Hardware microcontroller peripheral (unit)
SPI142
Spi_GetHWUnitStatus() configuration dependance.
SPI143
Creation in order to fulfill BSW12448
Creation of API interface Spi_Cancel to stop a specified Sequence
SPI144
transmission.
SPI145
Additional requirement for end sequence notification in case of cancelling.
SPI146
Spi_Cancel() configuration dependance.
Additional requirement for checking API parameter and what should be
SPI147
done in case of error
SPI148
Creation of a dedicated variant for post build-time parameters.
Global requirement concerning data width handled by HW and data type
SPI149
given by users.
Creation of API type Spi_AsyncModeType configurable at pre-compile
SPI150
time
Additional requirement to the service in order to cover the polling or inter-
SPI151
rupt handling at initialisation for LEVEL 2.
Creation of API interface Spi_SetAsyncMode to set the asynchronous
SPI152
mechanism mode.
Additional requirement in case of setting mode while SPI Handler/Driver is
SPI153
busy.
SPI154
Spi_SetAsyncMode() configuration dependance.
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Requirement to include both polling and interrupt asynchronous mecha-
SPI155
nisms in LEVEL 2.
SPI156
Additional requirement to have selectable modes during execution time.
Additional requirement for asynchronous transmissions of Jobs and spe-
SPI157
cially for setting their results.

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V3.2.0
R4.0 Rev 3
14  Changes during SWS Improvements by Technical Of-
fice

14.1  Deleted SWS Items

SWS Item
Rationale
SPI079
Not a requirement but an example (sequence diagram)
SPI147
Redundant to SPI032

14.2  Replaced SWS Items

SWS Item of Release 1  replaced by
Rationale
SWS Item
SPI096
SPI158, SPI159
Splitted because original requirement was on
different objects.
SPI113
SPI160, SPI161
Splitted because original requirement was on
different issues.
SPI001
SPI162, SPI163
Splitted because original requirement was on
different issues.
SPI153
SPI171, SPI172
Splitted because for better distinction between
modes
SPI070
SPI174
Replaced by UML Model linking of imported
types

14.3  Changed SWS Items

Many requirements have been changed to improve understandability without chang-
ing the technical contents.

14.4  Added SWS Items

SWS Item
Rationale
SPI164
Definition of Spi_DataType
SPI165
Definition of Spi_NumberOfDataType
SPI166
Definition of Spi_ChannelType
SPI167
Definition of Spi_JobType
SPI168
Definition of Spi_SequenceType
SPI169
Definition of Spi_HWUnitType
SPI170
Definition of Spi_AsyncModeType
SPI173
Requirement had no ID
SPI175
UML Model linking of Spi_Init
SPI176
UML Model linking of Spi_DeInit
SPI177
UML Model linking of Spi_WriteIB
SPI178
UML Model linking of Spi_AsyncTransmit
SPI179
UML Model linking of Spi_ReadIB
SPI180
UML Model linking of Spi_SetupEB
SPI181
UML Model linking of Spi_GetStatus
SPI182
UML Model linking of Spi_GetJobResult
SPI183
UML Model linking of Spi_GetSequenceResult
SPI184
UML Model linking of Spi_GetVersionInfo
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V3.2.0
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SPI185
UML Model linking of Spi_SyncTransmit
SPI186
UML Model linking of Spi_GetHWUnitStatus
SPI187
UML Model linking of Spi_Cancel
SPI188
UML Model linking of Spi_SetAsyncMode
SPI189
UML Model linking of Spi_MainFunction_Handling
SPI190
UML Model linking of Spi_MainFunction_Driving
SPI191
UML Model linking of the optional interfaces
SPI192
UML Model linking of Spi_JobEndNotification
SPI193
UML Model linking of Spi_SeqEndNotification
SPI196
Hint Spi_GetVersionInfo
Requirement added for inclusion of development error
SPI233
SPI_E_ALREADY_INITIALIZED.
SPI234
sentence agreed within SPAL,
SPI235
Extension of SPI198

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Specification of SPI Handler/Driver

V3.2.0
R4.0 Rev 3
15  Changes to Release 3

15.1  Deleted SWS Items

SWS Item
Rationale
SPI190
SPI doesn’t need to use a FIXED_CYCLIC scheduled function
SPI094
Already covered SPI068

15.2  Splitted SWS Items

SWS Item of Release 1  Splitted in
Rationale
SWS Item
SPI003
SPI003, SPI236
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI004
SPI004, SPI237,
SWS items that need to be split up into more
SPI238, SPI240,
than one requirement to yield atomic require-
SPI241, SPI242,
ments.
SPI243, SPI245,
SPI246
SPI005
SPI005, SPI249,
SWS items that need to be split up into more
SPI250,
than one requirement to yield atomic require-
ments.
SPI019
SPI019, SPI251
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI021
SPI021, SPI252,
SWS items that need to be split up into more
SPI253
than one requirement to yield atomic require-
ments.
SPI032
SPI032, SPI254
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI034
SPI034, SPI255
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI046
SPI046, SPI256
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI051
SPI051, SPI257
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI060
SPI060, SPI258
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI061
SPI061, SPI259,
SWS items that need to be split up into more
SPI260
than one requirement to yield atomic require-
ments.
SPI062
SPI062, SPI261
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI065
SPI065, SPI262
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI066
SPI066, SPI263
SWS items that need to be split up into more
than one requirement to yield atomic require-
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V3.2.0
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ments.
SPI075
SPI075, SPI264,
SWS items that need to be split up into more
SPI265
than one requirement to yield atomic require-
ments.
SPI081
SPI081, SPI266
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI083
SPI083, SPI267
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI088
SPI088, SPI268,
SWS items that need to be split up into more
SPI269, SPI270,
than one requirement to yield atomic require-
SPI271
ments.
SPI092
SPI092, SPI272,
SWS items that need to be split up into more
SPI273, SPI274,
than one requirement to yield atomic require-
SPI275, SPI276
ments.
SPI095
SPI095, SPI277
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI102
SPI102, SPI278
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI111
SPI111, SPI279
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI112
SPI112, SPI280
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI118
SPI118, SPI281
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI123
SPI123, SPI282
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI128
SPI128, SPI283
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI134
SPI134, SPI285,
SWS items that need to be split up into more
SP286
than one requirement to yield atomic require-
ments.
SPI141
SPI141, SPI287
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI143
SPI143, SPI288
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI149
SPI149, SPI289,
SWS items that need to be split up into more
SPI290, SPI291
than one requirement to yield atomic require-
ments.
SPI157
SPI157, SPI292,
SWS items that need to be split up into more
SPI293
than one requirement to yield atomic require-
ments.
SPI161
SPI161, SPI294
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI162
SPI162, SPI295
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI174
SPI174, SPI296,
SWS items that need to be split up into more
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V3.2.0
R4.0 Rev 3
SP297
than one requirement to yield atomic require-
ments.
SPI175
SPI175, SPI298,
SWS items that need to be split up into more
SPI299
than one requirement to yield atomic require-
ments.
SPI176
SPI176, SPI300,
SWS items that need to be split up into more
SPI301, SPI302,
than one requirement to yield atomic require-
SPI303
ments.
SPI177
SPI177, SPI304,
SWS items that need to be split up into more
SPI305, SPI306,
than one requirement to yield atomic require-
SPI307
ments.
SPI178
SPI178, SPI308,
SWS items that need to be split up into more
SPI309, SPI310,
than one requirement to yield atomic require-
SPI311
ments.
SPI179
SPI179, SPI312,
SWS items that need to be split up into more
SPI313, SPI314,
than one requirement to yield atomic require-
SPI315
ments.
SPI180
SPI180, SPI316,
SWS items that need to be split up into more
SPI317, SPI318
than one requirement to yield atomic require-
ments.
SPI181
SPI181, SPI319,
SWS items that need to be split up into more
SPI320
than one requirement to yield atomic require-
ments.
SPI182
SPI182, SPI321,
SWS items that need to be split up into more
SPI322
than one requirement to yield atomic require-
ments.
SPI183
SPI183, SPI323,
SWS items that need to be split up into more
SPI324
than one requirement to yield atomic require-
ments.
SPI184
SPI184, SPI325,
SWS items that need to be split up into more
SPI326
than one requirement to yield atomic require-
ments.
SPI185
SPI185, SPI327,
SWS items that need to be split up into more
SPI328, SPI329,
than one requirement to yield atomic require-
SPI330
ments.
SPI186
SPI186, SPI331,
SWS items that need to be split up into more
SPI332
than one requirement to yield atomic require-
ments.
SPI187
SPI187, SPI333,
SWS items that need to be split up into more
SPI334
than one requirement to yield atomic require-
ments.
SPI188
SPI188, SPI335,
SWS items that need to be split up into more
SPI336, SPI337,
than one requirement to yield atomic require-
SPI338
ments.
SPI191
SPI191, SPI339
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI192
SPI192, SPI340
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.
SPI193
SPI193, SPI341
SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.

SWS items that need to be split up into more
than one requirement to yield atomic require-
ments.

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V3.2.0
R4.0 Rev 3
15.3 Changed SWS Items

Many requirements have been changed to improve understandability without chang-
ing the technical contents.
SPI089
Change with revising “Published information”.
SPI068
Rework of Published Information

15.4 Added SWS Items

SWS Item
Rationale
SPI239
Requirement already contained in the specification but without specific ID
SPI244
Requirement already contained in the specification but without specific ID
SPI342
Requirement already contained in the specification but without specific ID
SPI343
Requirement already contained in the specification but without specific ID
SPI344
Requirement already contained in the specification but without specific ID
SPI345
Requirement already contained in the specification but without specific ID
SPI346
Requirement already contained in the specification but without specific ID
SPI347
Requirement already contained in the specification but without specific ID
SPI348
Requirement already contained in the specification but without specific ID
SPI349
Requirement already contained in the specification but without specific ID
SPI350
Requirement already contained in the specification but without specific ID
SPI351
Requirement already contained in the specification but without specific ID
SPI352
Requirement already contained in the specification but without specific ID
SPI353
Requirement already contained in the specification but without specific ID
SPI354
Requirement already contained in the specification but without specific ID
SPI355
Requirement already contained in the specification but without specific ID
SPI356
Requirement already contained in the specification but without specific ID
SPI357
Requirement already contained in the specification but without specific ID
SPI358
Requirement already contained in the specification but without specific ID
SPI359
Requirement already contained in the specification but without specific ID
SPI360
Requirement already contained in the specification but without specific ID
SPI361
Requirement already contained in the specification but without specific ID
SPI362
Requirement already contained in the specification but without specific ID
SPI363
Requirement to implement debugging concept
SPI364
Requirement to implement debugging concept
SPI365
Requirement to implement debugging concept
SPI366
Requirement to implement debugging concept
SPI367
Requirement to implement debugging concept
SPI368
Added the decsription of the Channel Index related to the SpiChannelIndex
parameter inside the SpiChannelList container
SPI369
Satisfaction of BSW004
SPI370
Chip Select handling
SPI371
Added reporting of passed parameter is a NULL pointer

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AUTOSAR_SWS_SPIHandler_Driver
- AUTOSAR confidential -

Component Design

Component Design

Module Detailled Design

Component Documentation

1 - CM600A_CSIG0CfgAndUse

High Level Description

Derived Requirements

Sub-Function Data Flow

Design Rationale

Sub-Functions

Sub-Function:

Hardware Related Design

Software Related Design

SPI Driver Configurations (General)

SPI Driver Configurations (PwrSply/TmplMonr specific)

PORT Configurations (PwrSply/TmplMonr specific)

OS Configurations (PwrSply/TmplMonr specific)

API Descriptions

Sub-Function: Next Sub-function

Timing / Execution Constraints

Rationale / Comments

Rates and State Execution

Serial Communications Interfaces

Additional Information

Revision Record & Change Approval

2 - A4412 Datasheet 2015_05_20

3 - A4412 Datasheet 2015_05_20_ind

4 - A4412 Datasheet 2015_05_20s

5 - AUTOSAR_SWS_SPIHandlerDriver

6 - AUTOSAR_SWS_SPIHandlerDriver_ind

7 - AUTOSAR_SWS_SPIHandlerDrivers

Document Outline