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Component Design

1: CM200C_DmaCfgAndUse_NexteerDmaRegsh
2: CM200C_DmaCfgAndUse_PeripheralCfg
3: CM200C_DmaCfgAndUse_FDD_Checklist

Component Design

Module Detailled Design

Component Documentation

CM200C_DmaCfgAndUse_FDD_Checklist.html

1 - CM200C_DmaCfgAndUse_NexteerDmaRegsh

Nexteer Dma Regs
Field Reg Name	DMA Channel	Register	Register Field name	Field Length ( Bits)
DMASSDTFR9	9	DTFR	-	32
DMASSDRQC9	9	DTFRRQC	DRQC	1
DMASSTCC9	9	DCSTC	TCC	1
DMASSDTE9	9	DCEN	DTE	1
DMASSDRQC14	14	DTFRRQC	DRQC	1
DMASSTCC14	14	DCSTC	TCC	1
DMASSDTE14	14	DCEN	DTE	1
DMASSTC15	15	DCST	TC	1
DMASSTCC15	15	DCSTC	TCC	1

2 - CM200C_DmaCfgAndUse_PeripheralCfg

DMAC Peripheral Register Configuration (base Address 0xFFFF 8000h)
*DMA Channel*	*Configurable*	*Offset*	*Name*	*Update*	*Description*	*Bit #*	*Set/Clear*	*Comment*
-	-	*0030h*	*DM0CMV*	*Dynamic*	*DMAC0 register access protection violation register*	*31-0*	-	*protection violation register*
-	-	*0034h*	*DM1CMV*	*Dynamic*	*DMAC1 register access protection violation register*	*31-0*	-	*protection violation register*
-	-	*003Ch*	*CMVC*	*Static*	*Register access protection violation clear register*	*31-0*	7U	*Clear protection violation register*
*DMA00*	*Do Not Configure this channel - Reserved for Future Use - MotAg0 Data Read : FromSPI Register (CSIH1) to Local RAM (Motor Control)*
*DMA01*	Adc0 Results Read : FromADC Register (ADCD0) to Local RAM (Motor Control)
DMA01	No	0100h + 4h *1	DM01CM	Static	DMAC1 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	3U	Channel Master SPID setting
						1	0U	Channel Master UM setting: Supervisor Mode
		0400h + 40h *1	DSA1	Static	DMAC1 Source Address	31-0	-	Address of (RegInpADCD0DR00)
		0404h + 40h *1	DDA1	Static	DMAC1 Destination Address	31-0	-	[Address of (MotCtrlAdc0RawRes)]
		0408h + 40h *1	DTC1	Static	DMAC1 transfer Count	16-31	0	Address Reload Count
		0408h + 40h *1	DTC1	Static	DMAC1 transfer Count	0-15	3U	Transfer Count
		040Ch + 40h *1	DTCT1	Static	DMAC1 transfer control	27	0	DMA transfer when transfer errored
						26	1U	Hardware DMA transfer request
						18-20	0	No Chain
						16-17	0	No Chain
						15	0	Disable - Transfer count match interrupt
						14	1U	Enable - Transfer Completion interrupt - Trigger Motor Control ISR
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	0	Increment -Destinable address count direction
						5-6	0	Increment - Source Address count direction
						2-4	4U	Transfer Data Size - 128 bit
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *1	DRSA1	Static	DMAC1 Reload Source Address	31-0	-	Address of (RegInpADCD0DR00)
		0414h + 40h *1	DRDA1	Static	DMAC1 Reload Destination Address	31-0	-	[Address of (MotCtrlAdc0RawRes)]
		0418h + 40h *1	DRTC1	Static	DMAC1 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *1	DRTC1	Static	DMAC1 Reload transfer Count	0-15	3U	Transfer Count
		0430h + 40h *1	DTFR1	Static	DMAC1 DTFR Setting	1-7	58U	Hardware DMA transfer source = INTADCD0I3
		0430h + 40h *1	DTFR1	Static	DMAC1 DTFR Setting	0	1U	Enable - Hardware DMA transfer source
		0414h + 40h *1	DCEN1	Static	DMAC1 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA02*	*Do Not Configure this channel -Reserved for Future Use - MotAg1 Data Read : FromSPI Register (CSIH3) to Local RAM (Motor Control)*
*DMA03*	*TSG Update Group 0 : FromLocal RAM (Motor Control) to TSG3 (TSG31)*
*DMA04*	*TSG Update Group 1 : FromLocal RAM (Motor Control) to TSG3 (TSG31)*
*DMA05*	*Do not Configure this channel - Reserved for Future Use*
*DMA06*	*SCI Rx Buffer Data Read- From SCI Rx to Local RAM*
*DMA07*	*SCI Tx Buffer Data Read- From Local RAM to SCI Tx*
*DMA10*	*Do not Configure this channel - Reserved for Future Use*
*DMA11*	*2mSec to MotCtrl : FromLocal RAM (Motor Control) to Local RAM*
*DMA12*	*Do Not Configure this channel - Reserved for Future Use - MotAg1 Spi Start : FromLocal RAM (Motor Control) to SPI Register (CSIH3)*
*DMA13*	*Do Not Configure this channel - Reserved for Future Use -MotAg1 Reset Read Pointer: From Local RAM (Motor Control) to SPI Register (CSIH3)*
*DMA14*	*Do Not Configure this channel - Reserved for Future Use - MotAg0 Spi Start : FromLocal RAM (Motor Control) to SPI Register (CSIH1)*
*DMA15*	*Do Not Configure this channel - Reserved for Future Use - MotAg0 Reset Read Pointer: From Local RAM (Motor Control) to SPI Register (CSIH1)*
*DMA16*	*Adc1 Results : FromADC Register (ADCD1) to Local RAM (Motor Control)*
DMA16	No	0120h + 4h *6	DM16CM	Static	DMAC16 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	3U	Channel Master SPID setting
						1	1U	Channel Master UM setting
		0400h + 40h *14	DSA14	Static	DMAC14 Source Address	31-0	-	Address of (RegInpADCD1DR00)
		0404h + 40h *14	DDA14	Static	DMAC14 Destination Address	31-0	-	Address of (MotCtrlAdc1RawRes)
		0408h + 40h *14	DTC14	Static	DMAC14 transfer Count	16	0	Address Reload Count
		0408h + 40h *14	DTC14	Static	DMAC14 transfer Count	0	3U	Transfer Count
		040Ch + 40h *14	DTCT14	Static	DMAC14 transfer control	27	0	DMA transfer when transfer errored
						26	1U	Hardware Request
						18-20	7U	Chain DMAC 1 Channel 7
						16-17	1U	Chain at last transfer
						15	0	Disable - Transfer count match interrupt
						14	0	Disable - Transfer Completion interrupt
						13	0	Disable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	0	Increment -Destinable address count direction
						5-6	0	Increment - Source Address count direction
						2-4	4U	Transfer Data Size - 128 bit
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *14	DRSA14	Static	DMAC14 Reload Source Address	31-0	-	Address of (RegInpADCD1DR00)
		0414h + 40h *14	DRDA14	Static	DMAC14 Reload Destination Address	31-0	-	Address of (MotCtrlAdc1RawRes)
		0418h + 40h *14	DRTC14	Static	DMAC14 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *14	DRTC14	Static	DMAC14 Reload transfer Count	0-15	3U	Transfer Count
		0430h + 40h *14	DTFR14	Static	DMAC14 DTFR Setting	1-7	61U	Hardware DMA transfer source = INTADCD1I1
		0430h + 40h *14	DTFR14	Static	DMAC14 DTFR Setting	0	1U	Enable - Hardware DMA transfer source
		0414h + 40h *14	DCEN14	Static	DMAC14 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA17*	*MotCtrl to 2mSec : FromLocal RAM (Motor Control) to Local RAM (2ms)*

Note 1:		ZZZ= Dynamic change value, X = Don’t Care, 1=Set, 0=Clear, -=Loaded Data/Configurable Data, unspecified register bits shall have safe default value
Note 2:		RSENTn, where n = 0

3 - CM200C_DmaCfgAndUse_FDD_Checklist

Nexteer_Template_V1.0

Overview

Peer Review Instructions
Technical Review Checklist
Template Change Log

Sheet 1: Peer Review Instructions

Instructions for Functional Design Package Peer Review

PRE-MEETING
	Function Owner	Confirm that requirements are reviewed and approved PRIOR to the FDP peer review
	Function Owner	Start with latest version of the template for any "first reviews" - Continue to use existing temmplate for re-reviews
	Function Owner	Provide the functional design package (changed documents) to the invited attendees 1-2 working days in advance of review
	Function Owner	Notify the assigned peer reviewer and make sure they are prepared to do their function in the meeting
	Function Owner	Identify necessary attendance and invite to meeting
	Function Owner	Complete the "Author" column information for sections 1 through 3 prior to the review
	Function Owner	Complete the attendance invitation list in section 5
	Function Owner	For Re-reviews only: Complete the column "remarks by author" to identify actions taken to address items found in earlier reviews.

DURING MEETING
	Function Owner	Present document changes to the review team
	Peer Reviewer	Capture attendance of the review
	Peer Reviewer	Capture actions and issues in section 4. Identify issue summary, Document type, Reference (Requirement ID, section number, etc), Defect Type and indicate status as "OPEN"

POST MEETING
	Function Owner	Follow up on all "open" items. Update "Summary of Resolution" to indicate what was done or decided.
	Function Owner	Schedule follow up review OR review open items with peer reviewer and obtain agreement to close
	Peer Reviewer	Close change request in system and confirm all associated tasks are complete. Upload peer review checklist (this document) with any FDP updates

Sheet 2: Technical Review Checklist

Technical Review Checklist - Template Version 01.00.05

Product Name

Electric Power Steering

Electrical Arch.

Review Scope

Defect Type

Numbers

Yes

Closed

Function Name

CM200C Dma Configuration And Use

Revision

1.1.0

EA4#8876
- Fault Injection

Requirement

Rejected

FDD

Author

Keyur Patel

Interface

Open

Model

Effort

Design

FMEA

Review Effort(Hrs.)

1.00

Standards

*.m File

Corr+Verf effort(Hrs.)

0.00

Documentation

Cal Process

Total Effort (Hrs.)

1.00

Others

Total

Checklist No.

Description of Check

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

Section 1: TECHNICAL CHECK

1.1

Confirm that all signal inputs into the FDP (Functional Design Package) are contained within and exactly named as the "Available_Nexteer_Signals.m" states.

Dma config and use has Motor control Manager inputs and register, which never brought in available nexteer signal name

Closed

1.2

Confirm any removed signal inputs from the design have been removed from the "Available_Nexteer_Signals.m" file.

Dma config and use has Motor control Manager inputs and register, which never brought in available nexteer signal name

Closed

1.3

Confirm all signals and parameters (outputs, calibrations, constants, non-volatile memory) used in the *.m file and the design conform to the AutoSAR naming convention documentation.

Yes

1.4

Confirm *.m file has been provided to the "Available_Signal_Names" Author.

Yes

It has been uploaded to synergy. This function should be same asCM200A, with removing some functionality

Closed

1.5

Confirm Electrical Systems interface map is updated to reflect the FDP (signal IO)

Section 2: Safety CHECK

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

2.1

Confirm that the functional DFMEA is up to date based on the design in the current package.

2.2

Confirm that Safety requirements (ASIL A - D) are referenced in the design documents.

Yes

Section 3: Lessons Learned

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

3.1

Have functions depending upon system state been reviewed for need to be executed at the 2ms rate to avoid system lag issues?

Yes

3.2

Have all diagnostics (NTCs) been confirmed to show logic to invoke a diagnostic "PASS" for control of the status byte at the customer level.

3.3

Has the requirements traceability steps used the RMI steps as defined in the FDD authoring spec to generate the traceability report?

there is no requirement associate with this design model

Closed

3.4

Has the requirements traceability report been verified to only contain ONLY requirements from the FR.

when ever requirement available need to revisit this

there is no requirement associate with this design model

Closed

3.5

Confirm that all PIM that does NOT have an initialization value of zero is initialized in an INIT function.

Yes

Section 4: Issues / Actions Identified

Document

Reference

Summary of resolution

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

4.1

VerifyDD report error

*.m File

Model is not runnable and software doesn't need model runnable, because they will hand code this CDD component

Standards

The design has configurable structure which is not recognized by the tool, so considering deadline & reviewer comment, didn't run CreateDD & VerifyDD tool. M file has been created based on previous version

Closed

4.2

Model advisor report not run

Model

Model is not runnable, so no model advisor report

Standards

Intent of this model to show function. There is no calculation, All the function try to access register data to & from, so model is not runnable

Closed

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

4.12

4.13

4.14

4.15

4.16

4.17

4.18

4.19

4.20

4.21

4.22

4.23

4.24

4.25

Section 5: APPROVALS

Role

First Review

Date

Attendance

Approval?

Function Owner*

Keyur Patel

12/9/2016

Yes

Peer Reviewer*

Avinash

Yes

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Second Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Third Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Fourth Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Add more if necessary

Date

Attendance

Approval?

P.S.:

Yes indicates adherence

No indicates non-adherence, reviewer shall provide suitable comments at the end of this document for each point.

NA indicates not applicable

Sheet 3: Template Change Log

Rev	Change	Author
01.00.05	Added lesson learned #3.5	MDK