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Component Design

1: CM670A_HwAg1Meas_RSENTPeripheralCfg
2: CM670A_HwAg1Meas_FDD_CheckList

Component Design

Module Detailled Design

CM670A_HwAg1Meas_RSENTPeripheralCfg.html

Component Documentation

CM670A_HwAg1Meas_FDD_CheckList.html

1 - CM670A_HwAg1Meas_RSENTPeripheralCfg

Overview

Configuration
Sheet1
Sheet2

Sheet 1: Configuration

RSENT Peripheral Register Configuration
*Offset*	*Name*	*Update*	*Description*	*Bit #*	*Set/Clear*	*Comment*
0000H	RSENTnTSPC	Static	RSENT timestamp register	16	0	Master Mode
				14-8	0	Tick Multiplier = 1
				6-0	79U	Tick Prescaler value = 80
0010H	RSENTnCC	Static	RSENT communication configuration register	12	1	SPC Pulse Active low
				11	1	Frame Check Against Previous Calibration Pulse
				10	1	Slow Channel CRC Check disable
				9	0	Fast Channel CRC Check Enable
				7-6	0	No Serial Message Extraction
				5	0	Puase Pulse for Variable Message Length
				4	0	Puase Pulse Absent
				3-1	3U	4 data nibble
				0	1	SPC mode enable
0014H	RSENTnBRP	Static	RSENT baud rate prescaler register	27-24	0	Tick Time Decimal Fraction = 0.0 us
				22-16	0	Time Tick Integer 1us
				14-8	4U	Sample Clock Division Value: 5 (80/5=16)
				0	0	Sample Clock Multiplication Value: 1
0018H	RSENTnIDE	Static	RSENT interrupt/DMA enable register	10	0	Slow Channel Encoding Error Interrupt Enable : Disabled
				9	0	Slow Channel Message Lost Interrupt Enable : Disabled
				8	0	Slow Channel CRC Error Interrupt Enable : Disabled
				7	0	No Response Error Interrupt Enable : Disabled
				6	0	Calibration Pulse Length Variation Error Interrupt Enable : Disabled
				5	0	Calibration Pulse Length Error Interrupt Enable : Disabled
				4	0	Fast Channel Nibble Count Error Interrupt Enable : Disabled
				3	0	Fast Channel Nibble Encoding Error Interrupt Enable : Disabled
				2	0	Fast Channel Message Lost Interrupt Enable : Disabled
				1	0	Fast Channel CRC Error Interrupt Enable : Disabled
				0	0	Fast Channel Receive Interrupt Enable : Disabled
001CH	RSENTnMDC	Dynamic	RSENT Mode Control Register	2-0	ZZZ	0 - Reset 1U- Configuration 5U - Operation Active
0020H	RSENTnSPCT	Static	RSENT SPC transmission register	6-0	ZZZ	17 Tick = 17 us

Note 1:	ZZZ= Dynamic change value, X = Don’t Care, 1=Set, 0=Clear, -=Loaded Data, unspecified register bits shall have safe default value
Note 2:	RSENTn, where n = 2

Sheet 2: Sheet1

HwTqMeas_Register_Configuration
Register Name	Abbrevision	Address			Bit Position	Bit Name	Function to Set
RSENT timestamp register	RSENTnTSPC	FFE0 5000	+	0000H
					16	TMS	0: Master mode


RSENT timestamp counter	RSENTnTSC	FFE0 5000	+	0004H



RSENT communication configuration register	RSENTnCC	FFE0 5000	+	0010H



RSENT baud rate prescaler register	RSENTnBRP	FFE0 5000	+	0014H



RSENT interrupt/DMA enable register	RSENTnIDE	FFE0 5000	+	0018H



RSENT mode control register	RSENTnMDC	FFE0 5000	+	001CH
RSENT SPC transmission register	RSENTnSPCT	FFE0 5000	+	0020H
RSENT mode status register	RSENTnMST	FFE0 5000	+	0024H
RSENT communication status register	RSENTnCS	FFE0 5000	+	0028H
RSENT communication status clear register	RSENTnCSC	FFE0 5000	+	002CH
RSENT slow channel receive timestamp register	RSENTnSRTS	FFE0 5000	+	0030H
RSENT slow channel receive data register	RSENTnSRXD	FFE0 5000	+	0034H
RSENT calibration pulse length register	RSENTnCPL	FFE0 5000	+	0038H
RSENT message length register	RSENTnML	FFE0 5000	+	003CH
RSENT fast channel receive timestamp register	RSENTnFRTS	FFE0 5000	+	0040H
RSENT fast channel receive data register	RSENTnFRXD	FFE0 5000	+	0044H
RSENT timestamp mode selection register	RSENTTSSEL	FFE0 5000	+	A000H

Sheet 3: Sheet2

RSENT timestamp register	RSENTnTSPC	RSENTn_base>	+	0000H
RSENT timestamp counter	RSENTnTSC	RSENTn_base>	+	0004H
RSENT communication configuration register	RSENTnCC	RSENTn_base>	+	0010H
RSENT baud rate prescaler register	RSENTnBRP	RSENTn_base>	+	0014H
RSENT interrupt/DMA enable register	RSENTnIDE	RSENTn_base>	+	0018H
RSENT mode control register	RSENTnMDC	RSENTn_base>	+	001CH
RSENT SPC transmission register	RSENTnSPCT	RSENTn_base>	+	0020H
RSENT mode status register	RSENTnMST	RSENTn_base>	+	0024H
RSENT communication status register	RSENTnCS	RSENTn_base>	+	0028H
RSENT communication status clear register	RSENTnCSC	RSENTn_base>	+	002CH
RSENT slow channel receive timestamp register	RSENTnSRTS	RSENTn_base>	+	0030H
RSENT slow channel receive data register	RSENTnSRXD	RSENTn_base>	+	0034H
RSENT calibration pulse length register	RSENTnCPL	RSENTn_base>	+	0038H
RSENT message length register	RSENTnML	RSENTn_base>	+	003CH
RSENT fast channel receive timestamp register	RSENTnFRTS	RSENTn_base>	+	0040H
RSENT fast channel receive data register	RSENTnFRXD	RSENTn_base>	+	0044H
RSENT timestamp mode selection register	RSENTTSSEL	RSENT0_base>	+	A000H

2 - CM670A_HwAg1Meas_FDD_CheckList

Nexteer_Template_V1.0

Overview

Peer Review Instructions
Technical Review Checklist
Template Change Log

Sheet 1: Peer Review Instructions

Instructions for Functional Design Package Peer Review

PRE-MEETING
	Function Owner	Confirm that requirements are reviewed and approved PRIOR to the FDP peer review
	Function Owner	Start with latest version of the template for any "first reviews" - Continue to use existing temmplate for re-reviews
	Function Owner	Provide the functional design package (changed documents) to the invited attendees 1-2 working days in advance of review
	Function Owner	Notify the assigned peer reviewer and make sure they are prepared to do their function in the meeting
	Function Owner	Identify necessary attendance and invite to meeting
	Function Owner	Complete the "Author" column information for sections 1 through 3 prior to the review
	Function Owner	Complete the attendance invitation list in section 5
	Function Owner	For Re-reviews only: Complete the column "remarks by author" to identify actions taken to address items found in earlier reviews.

DURING MEETING
	Function Owner	Present document changes to the review team
	Peer Reviewer	Capture attendance of the review
	Peer Reviewer	Capture actions and issues in section 4. Identify issue summary, Document type, Reference (Requirement ID, section number, etc), Defect Type and indicate status as "OPEN"

POST MEETING
	Function Owner	Follow up on all "open" items. Update "Summary of Resolution" to indicate what was done or decided.
	Function Owner	Schedule follow up review OR review open items with peer reviewer and obtain agreement to close
	Peer Reviewer	Close change request in system and confirm all associated tasks are complete. Upload peer review checklist (this document) with any FDP updates

Sheet 2: Technical Review Checklist

Technical Review Checklist - Template Version 01.00.09

Product Name

Electric Power Steering

Electrical Arch.

Review Scope

Defect Type

Numbers

Yes

Closed

Function Name

CM670A Handwheel Angle 1 Measurement

Version

1.8.0

Change Control #: WCR-EA4#6132
Description:
- Throughput Improvement

Requirement

Rejected

FDD

Author

Muragesh Asundi

Interface

Open

Model

Effort

Design

FMEA

Review Effort(Hrs.)

0.25

Standards

*.m File

Corr+Verf effort(Hrs.)

Documentation

Cal Process

Total Effort (Hrs.)

0.25

Others

Total

Checklist No.

Description of Check

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

Section 1: TECHNICAL CHECK

1.1

Confirm that all signal inputs into the FDP (Functional Design Package) are contained within and exactly named as the "Available_Nexteer_Signals.m" states.

Yes

1.2

Confirm any removed signal inputs from the design have been removed from the "Available_Nexteer_Signals.m" file.

1.3

Confirm all signals and parameters (outputs, calibrations, constants, non-volatile memory) used in the *.m file and the design conform to the AutoSAR naming convention documentation.

Yes

1.4

Confirm *.m file has been provided to the "Available_Signal_Names" Author.

Yes

1.5

Confirm Electrical Systems interface map is updated to reflect the FDP (signal IO)

Yes

1.6

Confirm that Static Register evaluation has been completed and updated for any register data that is written to.

1.7

Have calibration default values been reviewed for correctness?

Section 2: Safety CHECK

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

2.1

Confirm that the functional DFMEA is up to date based on the design in the current package.

2.2

Confirm that Safety requirements (ASIL A - D) are referenced in the design documents.

Yes

Section 3: Lessons Learned

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

3.01

Have functions depending upon system state been reviewed for need to be executed at the 2ms rate to avoid system lag issues?

Yes

3.02

Have all diagnostics (NTCs) been confirmed to show logic to invoke a diagnostic "PASS" for control of the status byte at the customer level.

Yes

3.03

Has the requirements traceability steps used the RMI steps as defined in the FDD authoring spec to generate the traceability report?

Yes

3.04

Has the requirements traceability report been verified to only contain ONLY requirements from the FR.

Yes

3.05

Confirm that all PIM that does NOT have an initialization value of zero is initialized in an INIT function.

Yes

3.06

Confirm if NVM is used, the NVM is defined in structures

3.07

If the function uses NVM, confirm that the m file uses the SetBlockStatus to indicate a write at powerdown

3.08

Confirm NTCs are not set within an IRQ (not related to the typical periodic OS)

Yes

3.09

Confirm NTCs are not set or read in a periodic rate faster than 2 ms (ex. Motor Control Loop)

Yes

3.10

Constants check: Do all constants have the correct scope (local, global) and are they defined in the correct location (this FDD, ES/SF/AR999)?

Yes

3.11

Confirm all calibrations are required (ie they cannot be constants)

Yes

Section 4: Issues / Actions Identified

Document

Reference

Summary of resolution

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

4.12

4.13

4.14

4.15

4.16

4.17

4.18

4.19

4.20

4.21

4.22

4.23

4.24

4.25

Section 5: APPROVALS

Role

First Review

Date

Attendance

Approval?

Function Owner*

Keyur Patel

6/10/2016

Yes

Peer Reviewer*

Travis

Yes

EPDT Engineer

ES Engineer

Software Lead

krishna anne

Yes

Hardware Lead

Test Lead

Safety Lead

Role

Second Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Third Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Fourth Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Add more if necessary

Date

Attendance

Approval?

P.S.:

Yes indicates adherence

No indicates non-adherence, reviewer shall provide suitable comments at the end of this document for each point.

NA indicates not applicable

Sheet 3: Template Change Log

Rev	Change	Author
01.00.05	Added lesson learned #3.5	MDK
01.00.06	Added lesson learned #3.6, 3.7 - Structure and writing of NVM in mfiles and models.	MDK
01.00.07	Clarified 3.6 and 3.7 Added lessons learned for NTCs not being set in IRQs or periodics faster than 2ms/	MDK
01.00.08	Added section 1.6 to look for critical static register analysis	MDK
01.00.09	Added two checks - default cals and are all cals really required to be a calibration	MDK