Sr. No.	Title	Version
1	FDD – CM475A Sci30CfgAndUse	See Synergy subproject version
2	Software Naming Conventions	Process 04.02.01
3	Software Coding Standards	Process 04.02.01

Dependencies

SWCs

Module	Required Feature
AR350A ImcArbn	All the IMC signal group definitions

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

IninSciDtsChMstReg - To be defined as a trusted function as the DTS Channel master registers need to be configured in the supervisor mode.

Configuration REQUIREMeNTS

Build Time Config

Modules	Notes
None

Configuration Files to be provided by Integration Project

Da Vinci Parameter Configuration Changes

Parameter	Notes	SWC

DaVinci Interrupt Configuration Changes

ISR Name	VIM #	Priority Dependency	Notes

Manual Configuration Changes

Constant	Notes	SWC
None

Exclusive Areas

Constant

Notes

SWC

ExclsvAr1SciDrvrTxRxBuf

Exclusive area needs to protect access to Transmit and Receive buffers from asynchronous updates by server runnables and periodic updates by tasks.

Integrator needs to verify if client calls to server runnables can interrupt periodics and set up exclusive area to properly protect access. If exclusive area is needed, at minimum it must disable OS Task scheduling (It is assumed that all clients call occurs in OS Tasks).

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

None

Required Global Data Outputs

None

Specific Include Path present

Yes

Runnable Scheduling

This section specifies the required runnable scheduling.

Init	Scheduling Requirements	Trigger
Sci30CfgAndUseInit1	None	Once At Init (RTE)

Runnable	Scheduling Requirements	Trigger
Sci30CfgAndUsePer1	None	2ms(RTE)
Sci30CfgAndUsePer2	None	2ms(RTE)
Sci30CfgAndUsePer3	None	10ms(RTE)
Sci30CfgAndUsePer4	None	100ms(RTE)

Memory Map REQUIREMENTS

Mapping

Memory Section	Contents	Notes
CDD_Sci30CfgAndUse_START_SEC_CODE
CDD_Sci30CfgAndUse_START_SEC_VAR_INIT_128
CDD_Sci30CfgAndUse_DmaWrite_START_SEC_VAR_INIT_128

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Feature	RAM	ROM

Table 1: ARM Cortex R4 Memory Usage

NvM Blocks

None

Compiler Settings

Preprocessor MACRO

None

Optimization Settings

None

Appendix

2 - Sci30CfgAndUse Module Design Document

Module Design Document

For

Sci30CfgAndUse

Jan 20, 2016

Prepared For:

Software Engineering

Nexteer Automotive,

Saginaw, MI, USA

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA
Change History

Description	Author	Version	Date
Initial Version	Avinash James	1.0	01/20/17

Table of Contents

1 Introduction 5

1.1.1 Purpose 5

1.1.2 Scope 5

2 Sci30CfgAndUse & High-Level Description 6

3 Design details of software module 7

3.1.1 Graphical representation of Sci30CfgAndUse 7

3.1.2 Data Flow Diagram 7

3.1.3 Component level DFD 7

3.1.4 Function level DFD 7

4 Constant Data Dictionary 8

4.1.1 Program (fixed) Constants 8

4.1.2 Embedded Constants 8

5 Variable Data Dictionary 9

5.1.1 User defined typedef definition/declaration 9

5.1.2 Variable definition for enumerated types 9

6 Software Component Implementation 10

6.1.1 Sub-Module Functions 10

6.1.2 Init: Sci30CfgAndUseInit1 10

6.1.3 Design Rationale 10

6.1.4 Module Outputs 10

6.1.5 Per: Sci30CfgAndUsePer1 10

6.1.6 Per: Sci30CfgAndUsePer2 10

6.1.7 Per: Sci30CfgAndUsePer3 11

6.1.8 Per: Sci30CfgAndUsePer4 11

6.1.9 Server Runnables 11

6.1.10 Interrupt Functions 12

6.1.11 Module Internal (Local) Function: RollOvrAdd 12

6.1.12 Module Internal (Local) Function: UpdDtsTxReg 12

6.1.13 Module Internal (Local) Function: UpdDtsRxReg 12

6.1.14 GLOBAL Function/Macro Definitions 12

7 Known Limitations with Design 14

8 UNIT TEST CONSIDERATION 15

Appendix A Abbreviations and Acronyms 16

Appendix B Glossary 17

Appendix C References 18

Introduction

Purpose

Scope

The following definitions are used throughout this document:

Shall: indicates a mandatory requirement without exception in compliance.
Should: indicates a mandatory requirement; exceptions allowed only with documented justification.
May: indicates an optional action.

Sci30CfgAndUse & High-Level Description

See FDD

Design details of software module

Graphical representation of Sci30CfgAndUse

Data Flow Diagram

Component level DFD

See FDD

Function level DFD

See FDD

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Constant Name	Resolution	Units	Value
SCITXMAXBUFSIZE_CNT_U08	1	Cnt	80
IMCARBNRXDATASRCSCI_CNT_U08	1	Cnt	1
Refer .m file

Variable Data Dictionary

User defined typedef definition/declaration

Typedef Name	Element Name	User Defined Type	Legal Range (min)	Legal Range (max)
Ary1D_u8_Sci30CfgAndUseA
Ary2D_u8_Sci30CfgAndUseA
Ary2D_u8_Sci30CfgAndUseB
Ary2D_u8_Sci30CfgAndUseC

Variable definition for enumerated types

Enum Name	Element Name	Value

Software Component Implementation

We have the global transmit and receive buffers declared at the file level as static variables in different memory map sections. The global transmit is in a memory map section aligned at 128 bit boundary in the Sci30CfgAndUse data section as DTS has to read the data from the buffer. The global memory map is also aligned on a 128 bit boundary but defined in the .data_dma_128 memory map as the DTS has to write data to the buffer

Sub-Module Functions

Init: Sci30CfgAndUseInit1

Design Rationale

Refer FDD

Module Outputs

None

Per: Sci30CfgAndUsePer1

Design Rationale

See FDD

Store Module Inputs to Local copies

Refer to FDD

(Processing of function)………

Refer to FDD

Store Local copy of outputs into Module Outputs

Refer to FDD

Module Outputs

None

Per: Sci30CfgAndUsePer2

Design Rationale

See FDD

Store Module Inputs to Local copies

Refer to FDD

(Processing of function)………

Refer to FDD

Store Local copy of outputs into Module Outputs

Refer to FDD

Module Outputs

None

Per: Sci30CfgAndUsePer3

Design Rationale

See FDD

Store Module Inputs to Local copies

Refer to FDD

(Processing of function)………

Refer to FDD

Store Local copy of outputs into Module Outputs

Refer to FDD

Module Outputs

None

Per: Sci30CfgAndUsePer4

Design Rationale

See FDD

Store Module Inputs to Local copies

Refer to FDD

(Processing of function)………

Refer to FDD

Store Local copy of outputs into Module Outputs

Refer to FDD

Module Outputs

None

Server Runnables

None

Design Rationale

Store Module Inputs to Local copies

(Processing of function)………

Store Local copy of outputs into Module Outputs

Interrupt Functions

None

Module Internal (Local) Function: RollOvrAdd

Function Name	RollOvrAdd	Type	Min	Max
Arguments Passed	Idx_Cnt_T_u08	Uint8	0	255
Return Value	None

Design Rationale

Function which returns the index value rolled over the max number of bytes received

Processing

Module Internal (Local) Function: UpdDtsTxReg

Function Name	UpdDtsTxReg	Type	Min	Max
Arguments Passed	SciGlbTxCnt_Cnt_u08	Uint8	0	255
Return Value	None

Design Rationale

Processing

Module Internal (Local) Function: UpdDtsRxReg

Function Name	UpdDtsRxReg	Type	Min	Max
Arguments Passed	None
Return Value	None

Design Rationale

Processing

GLOBAL Function/Macro Definitions

IninSciDtsChMstReg

Function Name	IninSciDtsChMstReg	Type	Min	Max
Arguments Passed	None
Return Value	None

Design Rationale

The DTS channel master registers can only be configured in the supervisor mode. Hence we need to make use of a trusted function to configure the channel master registers

Processing

Known Limitations with Design

UNIT TEST CONSIDERATION

*Rte_Pim_SciDiagcRxMaxDataErrCntr(),*Rte_Pim_SciDiagcOvrrunErrCntr(),*Rte_Pim_SciDiagcParErrCntr() and *Rte_Pim_SciDiagcFrmErrCntr()are used as rolling counters. Hence rollover on them is intentional.

Abbreviations and Acronyms

Abbreviation or Acronym	Description

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

ISO 9000
ISO/IEC 12207
ISO/IEC 15504
Automotive SPICE® Process Reference Model (PRM)
Automotive SPICE® Process Assessment Model (PAM)
ISO/IEC 15288
ISO 26262
IEEE Standards
SWEBOK
PMBOK
Existing Nexteer Automotive documentation

Term	Definition	Source
MDD	Module Design Document
DFD	Data Flow Diagram

References

Ref. #	Title	Version
1	AUTOSAR Specification of Memory Mapping (Link:AUTOSAR_SWS_MemoryMapping.pdf)	v1.3.0 R4.0 Rev 2
2	MDD Guideline	EA4 01.00.00
3	Software Naming Conventions.doc	1.0
4	Software Design and Coding Standards.doc	2.0

3 - Sci30CfgAndUse Peer Review Checklists

Overview

Summary Sheet
Synergy Project
Source Code
PolySpace

Sheet 1: Summary Sheet

Rev 1.2

8-Jun-15

Peer Review Summary Sheet

Synergy Project Name:

kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. CM745A_Sci30CfgAndUse_Impl

Revision / Baseline:

kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. CM745A_Sci30CfgAndUse_Impl_1.1.0

Change Owner:

kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Avinash James

Work CR ID:

EA4#8022

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

N/A

MDD

Yes

Source Code

Yes

PolySpace

N/A

Integration Manual

N/A

Davinci Files

Comments:

General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include FDD Owner and Integrator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.

Sheet 2: Synergy Project

Peer Review Meeting Log (Component Synergy Project Review)

Quality Check Items:

Rationale is required for all answers of No

New baseline version name from Summary Sheet follows

Yes

Comments:

naming convention

Project contains necessary subprojects

Yes

Comments:

Project contains the correct version of subprojects

Yes

Comments:

Design subproject is correct version

Yes

Comments:

General Notes / Comments:

LN: Intended Use: Identify who were the reviewers and if the reviewed changes have been approved. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. KMC: Group Review Level removed in Rev 4.0 since the design review is not checked in until approved, so it would always be DR4. Review Board:

Change Owner:

Avinash James

Review Date :

02/01/17

Lead Peer Reviewer:

Shruthi Raghavan

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 3: Source Code

Rev 1.2

8-Jun-15

Peer Review Meeting Log (Source Code Review)

Source File Name:

CDD_Sci30CfgAndUse.c

Source File Revision:

Header File Name:

CDD_Sci30CfgAndUse.h

Header File Revision:

kzshz2: Intended Use: Identify which version of the source file is being review. Rationale: Required for traceability between source code and review. Auditors will likely require this. 1

Header File Name:

CDD_Sci30CfgAndUse_Private.h

Header File Revision:

kzshz2: Intended Use: Identify which version of the source file is being review. Rationale: Required for traceability between source code and review. Auditors will likely require this. 1

MDD Name:

Sci30CfgAndUse Module Design Document

Revision:

FDD/SCIR/DSR/FDR/CM Name:

CM745A_Sci30CfgAndUse_Design

Revision:

1.3.0

Quality Check Items:

Rationale is required for all answers of No

Working EA4 Software Naming Convention followed:

for variable names

N/A

Comments:

for constant names

N/A

Comments:

for function names

N/A

Comments:

for other names (component, memory

N/A

Comments:

mapping handles, typedefs, etc.)

All paths assign a value to outputs, ensuring

N/A

Comments:

all outputs are initialized prior to being written

Requirements Tracability tags in code match the requirements tracability in the FDD

N/A

Comments:

requirements tracability in the FDD

All variables are declared at the function level.

Comments:

Global transmit and receive buffers

are defined in static file scope as they are accessed in multiple functions and also mapped in specific memory sections

Synergy version matches change history

kzshz2: Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). Rationale: There have been many occassions where versions were not updated in files and as a result Unit Test were referencing wrong versions. This often time leads to the need to re-run of batch tests.

Yes

Comments:

and Version Control version in file comment block

Change log contains detailed description of changes

Yes

Comments:

and Work CR number

Code accurately implements FDD (Document or Model)

Yes

Comments:

Verified no Compiler Errors or Warnings

KMC: Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). Rationale: This is needed to ensure there will be no errors discovered at the time of integration. A Sandox project should be used; QAC can find compiler errors but not warnings.

Yes

Comments:

Component.h is included

Yes

Comments:

All other includes are actually needed. (System includes

Yes

Comments:

only allowed in Nexteer library components)

Software Design and Coding Standards followed:

Version: 2.1

Code comments are clear, correct, and adequate

Yes

Comments:

and have been updated for the change: [N40] and

all other rules in the same section as rule [N40],

plus [N75], [N12], [N23], [N33], [N37], [N38],

[N48], [N54], [N77], [N79], [N72]

Source file (.c and .h) comment blocks are per

Yes

Comments:

standards and contain correct information: [N41], [N42]

Function comment blocks are per standards and

Yes

Comments:

contain correct information: [N43]

Code formatting (indentation, placement of

Yes

Comments:

braces, etc.) is per standards: [N5], [N55], [N56],

[N57], [N58], [N59]

Embedded constants used per standards; no

N/A

Comments:

"magic numbers": [N12]

Memory mapping for non-RTE code

Yes

Comments:

is per standard

All execution-order-dependent code can be

Yes

Comments:

recognized by the compiler: [N80]

All loops have termination conditions that ensure

Yes

Comments:

finite loop iterations: [N63]

All divides protect against divide by zero

N/A

Comments:

if needed: [N65]

All integer division and modulus operations

N/A

Comments:

handle negative numbers correctly: [N76]

All typecasting and fixed point arithmetic,

Yes

Comments:

including all use of fixed point macros and

timer functions, is correct and has no possibility

of unintended overflow or underflow: [N66]

All float-to-unsiged conversions ensure the.

N/A

Comments:

float value is non-negative: [N67]

All conversions between signed and unsigned

N/A

Comments:

types handle msb==1 as intended: [N78]

All pointer dereferencing protects against

N/A

Comments:

null pointer if needed: [N70]

Component outputs are limited to the legal range

N/A

Comments:

defined in the FDD DataDict.m file : [N53]

All code is mapped with FDD (all FDD

Yes

Comments:

subfunctions and/or model blocks identified

with code comments; all code corresponds to

some FDD subfunction and/or model block): [N40]

Review did not identify violations of other

Yes

Comments:

coding standard rules

Anomaly or Design Work CR created

N/A

Comments: List Anomaly or CR numbers

for any FDD corrections needed

General Notes / Comments:

Reviewed only the changes

Change Owner:

Avinash James

Review Date :

02/01/17

Lead Peer Reviewer:

Shruthi Raghavan

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 4: PolySpace

Rev 1.2

8-Jun-15

Peer Review Meeting Log (QAC/PolySpace Review)

Source File Name:

CDD_Sci30CfgAndUse.c

Source File Revision:

Source File Name:

Source File Revision:

Source File Name:

Source File Revision:

EA4 Static Analysis Compliance Guideline version:

01.01.00

Poly Space version:

Windows User: eg. 2013b 2013b

Polyspace sub project version:

Windows User: eg. TL108a_PolyspaceSuprt_1.0.0 N/A

QAC version:

Windows User: eg 8.1.1-R 8.1.1-R

QAC sub project version:

Windows User: eg. TL_100A_1.1.0 1.2.0

Quality Check Items:

Rationale is required for all answers of No

Contract Folder's header files are appropriate and

kzshz2: Intended Use: Identify that the contract folder contains only the information required for this component. All other variables, constants, function prototypes, etc. should be removed. Rationale: This will help avoid unit testers having to considers object not used. It will also avoid having other files required for QAC.

Yes

Comments:

function prototypes match the latest component version

100% Compliance to the EA4 Static Analysis

Comments:

See comments below

Compliance Guideline

Are previously added justification and deviation

Yes

Comments:

comments still appropriate

Do all MISRA deviation comments use approved

Yes

Comments:

deviation tags

Cyclomatic complexity and Static path count OK

Creager, Kathleen: use Browse Function Metrics, STCYC and STPTH

Yes

Comments:

for all functions in the component per Design

and Coding Standards rule [N47]

General Notes / Comments:

Bug finder flags error 10.3 which is not seen in QAC. Need to fix this in later version

Polyspace code prover flags an unreachable code. Analysed to be okay

Change Owner:

Avinash James

Review Date :

02/01/17

Lead Peer Reviewer:

Shruthi Raghavan

Approved by Reviewer(s):

Yes

Other Reviewer(s):