This is the multi-page printable view of this section. Click here to print.

Return to the regular view of this page.

Component Design

1: CM100A_StrtUpSeq_FDD_Checklist
2: StartUpGraphic

Component Design

Component Documentation

1 - CM100A_StrtUpSeq_FDD_Checklist

Nexteer_Template_V1.0

Overview

Peer Review Instructions
Technical Review Checklist
Template Change Log

Sheet 1: Peer Review Instructions

Instructions for Functional Design Package Peer Review

PRE-MEETING
	Function Owner	Confirm that requirements are reviewed and approved PRIOR to the FDP peer review
	Function Owner	Start with latest version of the template for any "first reviews" - Continue to use existing temmplate for re-reviews
	Function Owner	Provide the functional design package (changed documents) to the invited attendees 1-2 working days in advance of review
	Function Owner	Notify the assigned peer reviewer and make sure they are prepared to do their function in the meeting
	Function Owner	Identify necessary attendance and invite to meeting
	Function Owner	Complete the "Author" column information for sections 1 through 3 prior to the review
	Function Owner	Complete the attendance invitation list in section 5
	Function Owner	For Re-reviews only: Complete the column "remarks by author" to identify actions taken to address items found in earlier reviews.

DURING MEETING
	Function Owner	Present document changes to the review team
	Peer Reviewer	Capture attendance of the review
	Peer Reviewer	Capture actions and issues in section 4. Identify issue summary, Document type, Reference (Requirement ID, section number, etc), Defect Type and indicate status as "OPEN"

POST MEETING
	Function Owner	Follow up on all "open" items. Update "Summary of Resolution" to indicate what was done or decided.
	Function Owner	Schedule follow up review OR review open items with peer reviewer and obtain agreement to close
	Peer Reviewer	Close change request in system and confirm all associated tasks are complete. Upload peer review checklist (this document) with any FDP updates

Sheet 2: Technical Review Checklist

Technical Review Checklist - Template Version 01.00.07

Product Name

Electric Power Steering

Electrical Arch.

Review Scope

Defect Type

Numbers

Yes

Closed

Function Name

CM100A Start Up Sequence

Version

1.3.0

EA4#6641

Requirement

Rejected

FDD

Author

Samanth Kumaraswamy

Interface

Open

Model

Effort

Design

FMEA

Review Effort(Hrs.)

1.00

Standards

*.m File

Corr+Verf effort(Hrs.)

Documentation

Cal Process

Total Effort (Hrs.)

1.00

Others

Total

Checklist No.

Description of Check

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

Section 1: TECHNICAL CHECK

1.1

Confirm that all signal inputs into the FDP (Functional Design Package) are contained within and exactly named as the "Available_Nexteer_Signals.m" states.

1.2

Confirm any removed signal inputs from the design have been removed from the "Available_Nexteer_Signals.m" file.

1.3

Confirm all signals and parameters (outputs, calibrations, constants, non-volatile memory) used in the *.m file and the design conform to the AutoSAR naming convention documentation.

1.4

Confirm *.m file has been provided to the "Available_Signal_Names" Author.

1.5

Confirm Electrical Systems interface map is updated to reflect the FDP (signal IO)

Section 2: Safety CHECK

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

2.1

Confirm that the functional DFMEA is up to date based on the design in the current package.

2.2

Confirm that Safety requirements (ASIL A - D) are referenced in the design documents.

Section 3: Lessons Learned

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

3.1

Have functions depending upon system state been reviewed for need to be executed at the 2ms rate to avoid system lag issues?

3.2

Have all diagnostics (NTCs) been confirmed to show logic to invoke a diagnostic "PASS" for control of the status byte at the customer level.

3.3

Has the requirements traceability steps used the RMI steps as defined in the FDD authoring spec to generate the traceability report?

3.4

Has the requirements traceability report been verified to only contain ONLY requirements from the FR.

3.5

Confirm that all PIM that does NOT have an initialization value of zero is initialized in an INIT function.

3.6

Confirm if NVM is used, the NVM is defined in structures

3.7

If the function uses NVM, confirm that the m file uses the SetBlockStatus to indicate a write at powerdown

3.8

Confirm NTCs are not set within an IRQ (not related to the typical periodic OS)

3.9

Confirm NTCs are not set or read in a periodic rate faster than 2 ms (ex. Motor Control Loop)

Section 4: Issues / Actions Identified

Document

Reference

Summary of resolution

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

Section 5: APPROVALS

Role

First Review

Date

Attendance

Approval?

Function Owner*

Samanth Kumaraswamy

7/28/2016

Yes

Peer Reviewer*

Avinash

Yes

EPDT Engineer

ES Engineer

Raghavendran

Software Lead

Selva

Yes

Hardware Lead

Test Lead

Safety Lead

Role

Second Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Third Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Fourth Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Add more if necessary

Date

Attendance

Approval?

P.S.:

Yes indicates adherence

No indicates non-adherence, reviewer shall provide suitable comments at the end of this document for each point.

NA indicates not applicable

Sheet 3: Template Change Log

Rev	Change	Author
01.00.05	Added lesson learned #3.5	MDK
01.00.06	Added lesson learned #3.6, 3.7 - Structure and writing of NVM in mfiles and models.	MDK
01.00.07	Clarified 3.6 and 3.7 Added lessons learned for NTCs not being set in IRQs or periodics faster than 2ms/	MDK

2 - StartUpGraphic

MICRO
RESET

Out of Reset

In Reset

TOD
STATE

Pwr On

Pwr Off

WATCHDOG
STATE

Active

Inactive

ERROR-OUT
STATE

Normal

Faulted

INTRPT VECTOR TBL

Ebase

Rbase

ECM
STATE

Intlzd

Not Intlzd

DIAG MGR
STATE

Avail

Not Avail

Motor Control ISR

Active

Not Active

FDD Ref.

CM110A_FblStrtUpCfg

CM112A_CoreVltgMonr

CM106A _McuCoreConfigAndDiagc

CM104A_EcmOutpAndDiagc

CM107A_GuardCfgAndDiagc

CM108A_DataAndAdrPar

CM101A_ExcpnHdlg

CM107A_GuardCfgAndDiagc

CM800A_SyncCrc

CM102A_FlsMem

Hardware Power Up

BIST Execution

Lock Step Init*

Init Local RAM

Init DTS RAM

BSS/Data Sections

Power On Reset?

* BRAMDAT0 = FlsProgmReq or

* Includes

Yes è

Backup RAM Test

No app or cals?

FPU Init

Init Server Runnable Names

GP Init

Pass è

McuDiag = PwrOnRst

Configure BIST Reset (only on POR)

Configure Code Flash ECC

Configure Data Flash ECC Off

Configure Local RAM ECC / I Cache

Init SPI ECC Peripheral Mem

Confg SEGCONT

Init SPI

Init Ports

Stay in FBL*?

MCAL

McuCoreCfgAndDiagcInit1

McuCoreCfgAndDiagcInit2

EcmOutpAndDiagcInit3

MCAL

EcmOutpAndDiagcInit4

EcmOutpAndDiagcInit1

GuardCfgAndDiagcInit3

DataAndAdrParInit1

ExcpnHdlgInit1

GuardCfgAndDiagcInit1

SyncCrcInit0

FlsMemInit2

System Reg Init

MPU Init

Fail è

McuDiag = BackupRamTstFailr

Yes è

Temporal Monitor to Flash Mode

Init FEE for FBL

Init Serial Comm

PROGRAMMING….

McuDiag = FlsProgmCmpl

SW RESET

Cache init

No è

Reset Temporal Monitor

Jump to Application

Establish C Environment

Init DET

(ExecStrtUpTest == TRUE)?

(PowerOnReset == TRUE) AND (DebugMode = OFF)?

(ExecStrtUpTest == TRUE) AND (DebugMode = OFF)?

No è

CVM Low Reset?

Yes è

CVM Start Up Test

Yes è

BIST Checks

Yes è

Lock Step Tests

(ExecStrtUpTest == TRUE) AND (ECM Status Bits = 0)?

Init ECM*

(ExecStrtUpTest == TRUE) AND (ECM Status Bits = 0)?

Init AutoSAR SPI Drivers

Init Ports

Enable Watchdog ISR

Start Watchdog

(ExecStrtUpTest == TRUE)?

Init Digital IO

Init Flash Driver

Enable FPU Exceptions

StartOS*

Configure Guards

Sync CRC Init

Flash Mem Init*

CRC Check Start

Init FEE and Load

Init DEM

Config Prog Flow / Alive Monitors

Start Alarms / Run RTE Inits

PERIODICS RUN

Condition to Check If a test has to be performed for Power On Reset/ Soft Reset/ Hard Reset:

Yes è

McuDiag = CoreVltgMonLo

Clear CVM Error

ChkForStrtUpTest ( Address of ExecStrtUpTest)

Pass è

* Do Nothing *

Pass è

* Do Nothing *

Pass è

* Do Nothing *

Pass è

EI Interrupt Test

*MCU_Init()

Yes è

Pseudo Error Injection

ECM Compare Tests

Yes è

PBG Start Up Test

Yes è

P Bus Data Parity Start Up Test

* Init MPUs, User mode

* This function starts the Cofe Flash CRC

* Includes DMA initialization

If (ExecStrtUpTest == TRUE)

No è

CVM High Reset?

Enable Motor Control ISR

{

Fail è

McuDiag = CVM Start Up Test Failure

Fail è

McuDiag = Bist Failures

Fail è

McuDiag = Lock Step failures

Pass è

* Do Nothing *

Pass è

* Do Nothing *

Pass è

* Do Nothing *

Pass è

* Do Nothing *

Pass è

* Do Nothing *

Start OS Timer

Execute Start Up Test

Yes è

McuDiag = CoreVltgMonHi

Clear CVM Error

AutoSAR mode to RUN

}

No è

* Do Nothing *

No è

* Do Nothing *

No è

* Do Nothing *

Fail è

McuDiag = EI Interrupt Test Failure

Fail è

McuDiag = Pseudo Error Injection Failure

Fail è

McuDiag = Mst/Chkr Compare

Fail è

McuDiag = PBG Start Up Test Fault

Fail è

McuDiag = P Bus Data Parity Start Up Test

INITs Execute

No è

Pin Reset ?

Reset Cause

Fail è

McuDiag = ECM Start Up Fault/FACI Reset Transfer Error

No è

* Do Nothing *

No è

Do Nothiing

No è

Do Nothiing

Yes è

McuDiag = PinRst

Clear POF Flag

No è

ECM Reset ?

Check for ECM Bits that are set from reset.
FACI Reset is a special case because it is being checked in the If-Else If Conditions.
If(FACI Reset Bit Clear and No ECM Bits Set, Perform Test)
Else If (FACI Bit Set, Set BRAMDAT with FACI Error)
Else If (Any other ECM Bits set, Set BRAMDAT0 with ECM Start Up Fault)
Else (ExecStrtUpTest = False, Do Nothing)

*MCU_Init() does not clear the ECM Bits due to RESF Bits being cleared in FBL on an ECM Reset.
On a Power On Reset and SW Reset, irrespective of the RESF Bits, the MCU_Init does not clear the ECM Error Status Registers and there is no reason to clear the ECM Status Register. ECM Status Register gets cleared on a Power On Reset.

Rationale: PBG Lock bits once set, don't allow the control registers to chagne its values. Hence it is required that this Start Up test is run before the Guard is configured

Yes è

McuDiag = EcmRst

Clear POF Flag

No è

Software Reset?

Yes è

Clear POF Flag

No è

Debug Mode?

Rationale: When out an ECM Reset, the BRAMDAT0 is loaded with ECMRESET value and cannot be over written. This value is then checked in the Reset Cause and the ECM Bits are checked if it's a Lockstep Error and the NTC is logged. Hence we do not clear the ECM Status Bits.
In the Else case Statement, we are supposed to check for the ECM bits and log it as a ECM Start Up Fault. This means that the bit was set during the window where the Init3 ends and the MCU_Init() configuraiton is complete.

Yes è

* Do Nothing *

No è

McuDiag = RstUkwn