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Component Design

1: CM460A_Tauj1CfgAndUse_RegisterConfiguration
2: CM460A_Tauj1CfgAndUse_Design_PeerReviewChkList

Component Design

Module Detailled Design

CM460A_Tauj1CfgAndUse_RegisterConfiguration.html

Component Documentation

CM460A_Tauj1CfgAndUse_Design_PeerReviewChkList.html

1 - CM460A_Tauj1CfgAndUse_RegisterConfiguration

Overview

Assignments
Config
All Registers

Sheet 1: Assignments

Channel

Assignment

Clock Source

Phase D

CK0

Phase E

CK0

Phase F

CK0

AR102 - Timer Library

Sheet 2: Config

Register Group	Register	Register/Field	Setting	Description	Read Write Constraints

Clock Config	TAUJ1PRS0	TAUJ1.TPS.BIT.PRS0	000	PreClock = PCLK/1	Must be written at the field level
Control	TAUJ1CMUR0	TAUJ1.CMUR0.UINT8	11	Detection of falling and rising edges (selection of high width measurement
Control	TAUJ1TIS	TAUJ1.CMUR0.BIT.TIS	--	unused field register
Control	TAUJ1CMUR1	TAUJ1.CMUR1.UINT8	11	Detection of falling and rising edges (selection of high width measurement
Control	TAUJ1CMUR2	TAUJ1.CMUR2.UINT8	11	Detection of falling and rising edges (selection of high width measurement
Control	TAUJ1CMOR0	TAUJ1.CMOR0.UINT16	--	Detailed at field level	Can be written at field or register level
Control	TAUJ1MD	TAUJ1.CMOR0.BIT.MD	11010	Capture and gate count mode	Can be written at field or register level
Control	TAUJ1COS	TAUJ1.CMOR0.BIT.COS	01	Sets when CDR and OVF registers are updated, don't care for this application	Can be written at field or register level
Control	TAUJ1STS	TAUJ1.CMOR0.BIT.STS	010	Valid edge of TAUJnTTINm input signal is used as a start trigger and the reverse edge as a stop trigger.	Can be written at field or register level
Control	TAUJ1MAS	TAUJ1.CMOR0.BIT.MAS	0	Set channel as slave - not really applicable for use case	Can be written at field or register level
Control	TAUJ1CCS	TAUJ1.CMOR0.BIT.CCS	00	every other setting is prohibited	Can be written at field or register level
Control	TAUJ1CKS	TAUJ1.CMOR0.BIT.CKS	00	Select CK0 for all channels	Can be written at field or register level
Control	TAUJ1CMOR1	TAUJ1.CMOR1.UINT16	--	Detailed at field level	Can be written at field or register level
Control	TAUJ1MD	TAUJ1.CMOR1.BIT.MD	11010	Capture and gate count mode	Can be written at field or register level
Control	TAUJ1COS	TAUJ1.CMOR1.BIT.COS	01	Sets when CDR and OVF registers are updated, don't care for this application	Can be written at field or register level
Control	TAUJ1STS	TAUJ1.CMOR1.BIT.STS	010	Valid edge of TAUJnTTINm input signal is used as a start trigger and the reverse edge as a stop trigger.	Can be written at field or register level
Control	TAUJ1MAS	TAUJ1.CMOR1.BIT.MAS	0	Set channel as slave - not really applicable for use case	Can be written at field or register level
Control	TAUJ1CCS	TAUJ1.CMOR1.BIT.CCS	00	every other setting is prohibited	Can be written at field or register level
Control	TAUJ1CKS	TAUJ1.CMOR1.BIT.CKS	00	Select CK0 for all channels	Can be written at field or register level
Control	TAUJ1CMOR2	TAUJ1.CMOR2.UINT16	--	Don't care, channel not used
Control	TAUJ1MD	TAUJ1.CMOR2.BIT.MD	11010	Capture and gate count mode	Can be written at field or register level
Control	TAUJ1COS	TAUJ1.CMOR2.BIT.COS	01	Sets when CDR and OVF registers are updated, don't care for this application	Can be written at field or register level
Control	TAUJ1STS	TAUJ1.CMOR2.BIT.STS	010	Valid edge of TAUJnTTINm input signal is used as a start trigger and the reverse edge as a stop trigger.	Can be written at field or register level
Control	TAUJ1MAS	TAUJ1.CMOR2.BIT.MAS	0	Set channel as slave - not really applicable for use case	Can be written at field or register level
Control	TAUJ1CCS	TAUJ1.CMOR2.BIT.CCS	00	every other setting is prohibited	Can be written at field or register level
Control	TAUJ1CKS	TAUJ1.CMOR2.BIT.CKS	00	Select CK0 for all channels	Can be written at field or register level
Control	TAUJ1TS00	TAUJ1.TS.BIT.TS00	1	Enables Timer 0	Must be written at the field level
Control	TAUJ1TS01	TAUJ1.TS.BIT.TS01	1	Enables Timer 1	Must be written at the field level
Control	TAUJ1TS02	TAUJ1.TS.BIT.TS02	1	Enables Timer 2	Must be written at the field level
Not Written To/Read From During Init
Control	TAUJ1CDR0	TAUJ1.CDR0	--	Compare register, not used - read directly from count register	Can be left at default value
Control	TAUJ1CDR1	TAUJ1.CDR1	--	Compare register, not used - read directly from count register	Can be left at default value
Control	TAUJ1CDR2	TAUJ1.CDR2	--	Don't care, channel not used	Can be left at default value
Control	TAUJ1CNT0	TAUJ1.CNT0	--	Read by model	Read Only
Control	TAUJ1CNT1	TAUJ1.CNT1	--	Read by model	Read Only
Control	TAUJ1CNT2	TAUJ1.CNT2	--	Read by model	Read Only
Control	TAUJ1CSR0	TAUJ1.CSR0.UINT8	--	Unused feature	Read Only
Control	TAUJ1OVF	TAUJ1.CSR0.BIT.OVF	--	Unused feature	Read Only
Control	TAUJ1CSR1	TAUJ1.CSR1.UINT8	--	Unused feature	Read Only
Control	TAUJ1CSR2	TAUJ1.CSR2.UINT8	--	Unused feature	Read Only
Control	TAUJ1CSC0	TAUJ1.CSC0.UINT8	--	Unused feature, overflow is expected as part of normal operation	Can be left at default value
Control	TAUJ1CLOV	TAUJ1.CSC0.BIT.CLOV	--	Unused feature, overflow is expected as part of normal operation	Can be left at default value
Control	TAUJ1CSC1	TAUJ1.CSC1.UINT8	--	Unused feature, overflow is expected as part of normal operation	Can be left at default value
Control	TAUJ1CSC2	TAUJ1.CSC2.UINT8	--	Unused feature, overflow is expected as part of normal operation	Can be left at default value
Control	TAUJ1TE00	TAUJ1.TE.BIT.TE00	--	Unused register	Read Only
Control	TAUJ1TE01	TAUJ1.TE.BIT.TE01	--	Unused register	Read Only
Control	TAUJ1TE02	TAUJ1.TE.BIT.TE02	--	Unused register	Read Only
Control	TAUJ1TT00	TAUJ1.TT.BIT.TT00	--	Unused register, timer is never stopped	Do Not Write To
Control	TAUJ1TT01	TAUJ1.TT.BIT.TT01	--	Unused register, timer is never stopped	Do Not Write To
Control	TAUJ1TT02	TAUJ1.TT.BIT.TT02	--	Unused register, timer is never stopped	Do Not Write To
Output Channel Config	TAUJ1TOE00	TAUJ1.TOE.BIT.TOE00	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOE01	TAUJ1.TOE.BIT.TOE01	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOE02	TAUJ1.TOE.BIT.TOE02	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TO00	TAUJ1.TO.BIT.TO00	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TO01	TAUJ1.TO.BIT.TO01	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TO02	TAUJ1.TO.BIT.TO02	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOM00	TAUJ1.TOM.BIT.TOM00	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOM01	TAUJ1.TOM.BIT.TOM01	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOM02	TAUJ1.TOM.BIT.TOM02	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOC00	TAUJ1.TOC.BIT.TOC00	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOC01	TAUJ1.TOC.BIT.TOC01	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOC02	TAUJ1.TOC.BIT.TOC02	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOL00	TAUJ1.TOL.BIT.TOL00	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOL01	TAUJ1.TOL.BIT.TOL01	--	Not used, used to configure output channel characteristics	Do Not Write To
Output Channel Config	TAUJ1TOL02	TAUJ1.TOL.BIT.TOL02	--	Not used, used to configure output channel characteristics	Do Not Write To
Reload Data	TAUJ1RDE00	TAUJ1.RDE.BIT.RDE00	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RDE01	TAUJ1.RDE.BIT.RDE01	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RDE02	TAUJ1.RDE.BIT.RDE02	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RDM00	TAUJ1.RDM.BIT.RDM00	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RDM01	TAUJ1.RDM.BIT.RDM01	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RDM02	TAUJ1.RDM.BIT.RDM02	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RDT00	TAUJ1.RDT.BIT.RDT00	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RDT01	TAUJ1.RDT.BIT.RDT01	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RDT02	TAUJ1.RDT.BIT.RDT02	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RSF00	TAUJ1.RSF.BIT.RSF00	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RSF01	TAUJ1.RSF.BIT.RSF01	--	Not used, would be important for output uses	Do Not Write To
Reload Data	TAUJ1RSF02	TAUJ1.RSF.BIT.RSF02	--	Not used, would be important for output uses	Do Not Write To
Parts of Tauj1 shared with AR102
Clock Config	TAUJ1TPS	TAUJ1.TPS.UINT16	--	Register fields shared with AR102A	Do Not Write To
Clock Config	TAUJ1PRS1	TAUJ1.TPS.BIT.PRS1	--	Owned by AR102A	Do Not Write To
Clock Config	TAUJ1PRS2	TAUJ1.TPS.BIT.PRS2	--	Owned by AR102A	Do Not Write To
Clock Config	TAUJ1PRS3	TAUJ1.TPS.BIT.PRS3	--	Owned by AR102A	Do Not Write To
Clock Config	TAUJ1BRS	TAUJ1.BRS	--	Owned by AR102A	Do Not Write To
Control	TAUJ1CDR3	TAUJ1.CDR3	--	Owned by AR102A	Do Not Write To
Control	TAUJ1CMUR3	TAUJ1.CMUR3.UINT8	--	Owned by AR102A	Do Not Write To
Control	TAUJ1CMOR3	TAUJ1.CMOR3.UINT16	--	Owned by AR102A	Do Not Write To
Control	TAUJ1MD	TAUJ1.CMOR3.BIT.MD	--	Owned by AR102A	Do Not Write To
Control	TAUJ1COS	TAUJ1.CMOR3.BIT.COS	--	Owned by AR102A	Do Not Write To
Control	TAUJ1STS	TAUJ1.CMOR3.BIT.STS	--	Owned by AR102A	Do Not Write To
Control	TAUJ1MAS	TAUJ1.CMOR3.BIT.MAS	--	Owned by AR102A	Do Not Write To
Control	TAUJ1CCS	TAUJ1.CMOR3.BIT.CCS	--	Owned by AR102A	Do Not Write To
Control	TAUJ1CKS	TAUJ1.CMOR3.BIT.CKS	--	Owned by AR102A	Do Not Write To
Control	TAUJ1CNT3	TAUJ1.CNT3	--	Owned by AR102A	Do Not Write To
Control	TAUJ1TT	TAUJ1.TT.UINT8	--	Register fields shared with AR102A	Do Not Write To
Control	TAUJ1TT03	TAUJ1.TT.BIT.TT03	--	Owned by AR102A	Do Not Write To
Control	TAUJ1TS	TAUJ1.TS.UINT8	--	Register fields shared with AR102A	Do Not Write To
Control	TAUJ1TS03	TAUJ1.TS.BIT.TS03	--	Owned by AR102A	Do Not Write To
Control	TAUJ1CSC3	TAUJ1.CSC3.UINT8	--	Owned by AR102A	Do Not Write To
Control	TAUJ1TE	TAUJ1.TE.UINT8	--	Register fields shared with AR102A	Do Not Write To
Control	TAUJ1TE03	TAUJ1.TE.BIT.TE03	--	Owned by AR102A	Do Not Write To
Control	TAUJ1CSR3	TAUJ1.CSR3.UINT8	--	Owned by AR102A	Do Not Write To
Reload Data	TAUJ1RDT	TAUJ1.RDT.UINT8	--	Register fields shared with AR102A	Do Not Write To
Reload Data	TAUJ1RDT03	TAUJ1.RDT.BIT.RDT03	--	Owned by AR102A	Do Not Write To
Reload Data	TAUJ1RSF	TAUJ1.RSF.UINT8	--	Register fields shared with AR102A	Do Not Write To
Reload Data	TAUJ1RSF03	TAUJ1.RSF.BIT.RSF03	--	Owned by AR102A	Do Not Write To
Reload Data	TAUJ1RDM	TAUJ1.RDM.UINT8	--	Register fields shared with AR102A	Do Not Write To
Reload Data	TAUJ1RDM03	TAUJ1.RDM.BIT.RDM03	--	Owned by AR102A	Do Not Write To
Reload Data	TAUJ1RDE	TAUJ1.RDE.UINT8	--	Register fields shared with AR102A	Do Not Write To
Reload Data	TAUJ1RDE03	TAUJ1.RDE.BIT.RDE03	--	Owned by AR102A	Do Not Write To
Output Channel Config	TAUJ1TOC	TAUJ1.TOC.UINT8	--	Register fields shared with AR102A	Do Not Write To
Output Channel Config	TAUJ1TOC03	TAUJ1.TOC.BIT.TOC03	--	Owned by AR102A	Do Not Write To
Output Channel Config	TAUJ1TOL	TAUJ1.TOL.UINT8	--	Register fields shared with AR102A	Do Not Write To
Output Channel Config	TAUJ1TOL03	TAUJ1.TOL.BIT.TOL03	--	Owned by AR102A	Do Not Write To
Output Channel Config	TAUJ1TOE	TAUJ1.TOE.UINT8	--	Register fields shared with AR102A	Do Not Write To
Output Channel Config	TAUJ1TOE03	TAUJ1.TOE.BIT.TOE03	--	Owned by AR102A	Do Not Write To
Output Channel Config	TAUJ1TO	TAUJ1.TO.UINT8	--	Register fields shared with AR102A	Do Not Write To
Output Channel Config	TAUJ1TO03	TAUJ1.TO.BIT.TO03	--	Owned by AR102A	Do Not Write To
Output Channel Config	TAUJ1TOM	TAUJ1.TOM.UINT8	--	Register fields shared with AR102A	Do Not Write To
Output Channel Config	TAUJ1TOM03	TAUJ1.TOM.BIT.TOM03	--	Owned by AR102A	Do Not Write To

Sheet 3: All Registers

#define	TAUJ0CDR0	TAUJ0.CDR0
#define	TAUJ0CDR1	TAUJ0.CDR1
#define	TAUJ0CDR2	TAUJ0.CDR2
#define	TAUJ0CDR3	TAUJ0.CDR3
#define	TAUJ0CNT0	TAUJ0.CNT0
#define	TAUJ0CNT1	TAUJ0.CNT1
#define	TAUJ0CNT2	TAUJ0.CNT2
#define	TAUJ0CNT3	TAUJ0.CNT3
#define	TAUJ0CMUR0	TAUJ0.CMUR0.UINT8
#define	TAUJ0TIS	TAUJ0.CMUR0.BIT.TIS
#define	TAUJ0CMUR1	TAUJ0.CMUR1.UINT8
#define	TAUJ0CMUR2	TAUJ0.CMUR2.UINT8
#define	TAUJ0CMUR3	TAUJ0.CMUR3.UINT8
#define	TAUJ0CSR0	TAUJ0.CSR0.UINT8
#define	TAUJ0OVF	TAUJ0.CSR0.BIT.OVF
#define	TAUJ0CSR1	TAUJ0.CSR1.UINT8
#define	TAUJ0CSR2	TAUJ0.CSR2.UINT8
#define	TAUJ0CSR3	TAUJ0.CSR3.UINT8
#define	TAUJ0CSC0	TAUJ0.CSC0.UINT8
#define	TAUJ0CLOV	TAUJ0.CSC0.BIT.CLOV
#define	TAUJ0CSC1	TAUJ0.CSC1.UINT8
#define	TAUJ0CSC2	TAUJ0.CSC2.UINT8
#define	TAUJ0CSC3	TAUJ0.CSC3.UINT8
#define	TAUJ0TE	TAUJ0.TE.UINT8
#define	TAUJ0TE00	TAUJ0.TE.BIT.TE00
#define	TAUJ0TE01	TAUJ0.TE.BIT.TE01
#define	TAUJ0TE02	TAUJ0.TE.BIT.TE02
#define	TAUJ0TE03	TAUJ0.TE.BIT.TE03
#define	TAUJ0TS	TAUJ0.TS.UINT8
#define	TAUJ0TS00	TAUJ0.TS.BIT.TS00
#define	TAUJ0TS01	TAUJ0.TS.BIT.TS01
#define	TAUJ0TS02	TAUJ0.TS.BIT.TS02
#define	TAUJ0TS03	TAUJ0.TS.BIT.TS03
#define	TAUJ0TT	TAUJ0.TT.UINT8
#define	TAUJ0TT00	TAUJ0.TT.BIT.TT00
#define	TAUJ0TT01	TAUJ0.TT.BIT.TT01
#define	TAUJ0TT02	TAUJ0.TT.BIT.TT02
#define	TAUJ0TT03	TAUJ0.TT.BIT.TT03
#define	TAUJ0TO	TAUJ0.TO.UINT8
#define	TAUJ0TO00	TAUJ0.TO.BIT.TO00
#define	TAUJ0TO01	TAUJ0.TO.BIT.TO01
#define	TAUJ0TO02	TAUJ0.TO.BIT.TO02
#define	TAUJ0TO03	TAUJ0.TO.BIT.TO03
#define	TAUJ0TOE	TAUJ0.TOE.UINT8
#define	TAUJ0TOE00	TAUJ0.TOE.BIT.TOE00
#define	TAUJ0TOE01	TAUJ0.TOE.BIT.TOE01
#define	TAUJ0TOE02	TAUJ0.TOE.BIT.TOE02
#define	TAUJ0TOE03	TAUJ0.TOE.BIT.TOE03
#define	TAUJ0TOL	TAUJ0.TOL.UINT8
#define	TAUJ0TOL00	TAUJ0.TOL.BIT.TOL00
#define	TAUJ0TOL01	TAUJ0.TOL.BIT.TOL01
#define	TAUJ0TOL02	TAUJ0.TOL.BIT.TOL02
#define	TAUJ0TOL03	TAUJ0.TOL.BIT.TOL03
#define	TAUJ0RDT	TAUJ0.RDT.UINT8
#define	TAUJ0RDT00	TAUJ0.RDT.BIT.RDT00
#define	TAUJ0RDT01	TAUJ0.RDT.BIT.RDT01
#define	TAUJ0RDT02	TAUJ0.RDT.BIT.RDT02
#define	TAUJ0RDT03	TAUJ0.RDT.BIT.RDT03
#define	TAUJ0RSF	TAUJ0.RSF.UINT8
#define	TAUJ0RSF00	TAUJ0.RSF.BIT.RSF00
#define	TAUJ0RSF01	TAUJ0.RSF.BIT.RSF01
#define	TAUJ0RSF02	TAUJ0.RSF.BIT.RSF02
#define	TAUJ0RSF03	TAUJ0.RSF.BIT.RSF03
#define	TAUJ0CMOR0	TAUJ0.CMOR0.UINT16
#define	TAUJ0MD	TAUJ0.CMOR0.BIT.MD
#define	TAUJ0COS	TAUJ0.CMOR0.BIT.COS
#define	TAUJ0STS	TAUJ0.CMOR0.BIT.STS
#define	TAUJ0MAS	TAUJ0.CMOR0.BIT.MAS
#define	TAUJ0CCS	TAUJ0.CMOR0.BIT.CCS
#define	TAUJ0CKS	TAUJ0.CMOR0.BIT.CKS
#define	TAUJ0CMOR1	TAUJ0.CMOR1.UINT16
#define	TAUJ0CMOR2	TAUJ0.CMOR2.UINT16
#define	TAUJ0CMOR3	TAUJ0.CMOR3.UINT16
#define	TAUJ0TPS	TAUJ0.TPS.UINT16
#define	TAUJ0PRS0	TAUJ0.TPS.BIT.PRS0
#define	TAUJ0PRS1	TAUJ0.TPS.BIT.PRS1
#define	TAUJ0PRS2	TAUJ0.TPS.BIT.PRS2
#define	TAUJ0PRS3	TAUJ0.TPS.BIT.PRS3
#define	TAUJ0BRS	TAUJ0.BRS
#define	TAUJ0TOM	TAUJ0.TOM.UINT8
#define	TAUJ0TOM00	TAUJ0.TOM.BIT.TOM00
#define	TAUJ0TOM01	TAUJ0.TOM.BIT.TOM01
#define	TAUJ0TOM02	TAUJ0.TOM.BIT.TOM02
#define	TAUJ0TOM03	TAUJ0.TOM.BIT.TOM03
#define	TAUJ0TOC	TAUJ0.TOC.UINT8
#define	TAUJ0TOC00	TAUJ0.TOC.BIT.TOC00
#define	TAUJ0TOC01	TAUJ0.TOC.BIT.TOC01
#define	TAUJ0TOC02	TAUJ0.TOC.BIT.TOC02
#define	TAUJ0TOC03	TAUJ0.TOC.BIT.TOC03
#define	TAUJ0RDE	TAUJ0.RDE.UINT8
#define	TAUJ0RDE00	TAUJ0.RDE.BIT.RDE00
#define	TAUJ0RDE01	TAUJ0.RDE.BIT.RDE01
#define	TAUJ0RDE02	TAUJ0.RDE.BIT.RDE02
#define	TAUJ0RDE03	TAUJ0.RDE.BIT.RDE03
#define	TAUJ0RDM	TAUJ0.RDM.UINT8
#define	TAUJ0RDM00	TAUJ0.RDM.BIT.RDM00
#define	TAUJ0RDM01	TAUJ0.RDM.BIT.RDM01
#define	TAUJ0RDM02	TAUJ0.RDM.BIT.RDM02
#define	TAUJ0RDM03	TAUJ0.RDM.BIT.RDM03
#define	TAUJ0RDM03	TAUJ0.RDM.BIT.RDM03

2 - CM460A_Tauj1CfgAndUse_Design_PeerReviewChkList

Nexteer_Template_V1.0

Overview

Peer Review Instructions
Technical Review Checklist
Template Change Log

Sheet 1: Peer Review Instructions

Instructions for Functional Design Package Peer Review

PRE-MEETING
	Function Owner	Confirm that requirements are reviewed and approved PRIOR to the FDP peer review
	Function Owner	Start with latest version of the template for any "first reviews" - Continue to use existing temmplate for re-reviews
	Function Owner	Provide the functional design package (changed documents) to the invited attendees 1-2 working days in advance of review
	Function Owner	Notify the assigned peer reviewer and make sure they are prepared to do their function in the meeting
	Function Owner	Identify necessary attendance and invite to meeting
	Function Owner	Complete the "Author" column information for sections 1 through 5 prior to the review
	Function Owner	Complete the attendance invitation list in section 7
	Function Owner	For Re-reviews only: Complete the column "remarks by author" to identify actions taken to address items found in earlier reviews.

DURING MEETING
	Function Owner	Present document changes to the review team
	Peer Reviewer	Capture attendance of the review
	Peer Reviewer	Capture actions and issues in section 6. Identify issue summary, Document type, Reference (Requirement ID, section number, etc), Defect Type and indicate status as "OPEN"

POST MEETING
	Function Owner	Follow up on all "open" items. Update "Summary of Resolution" to indicate what was done or decided.
	Function Owner	Schedule follow up review OR review open items with peer reviewer and obtain agreement to close
	Peer Reviewer	Close change request in system and confirm all associated tasks are complete. Upload peer review checklist (this document) with any FDP updates

Sheet 2: Technical Review Checklist

Technical Review Checklist - Template Version 02.02.00

Product Name

Electric Power Steering

Electrical Arch.

Review Scope

Defect Type

Numbers

Yes

Closed

Function ID

CM460A_Tauj0CfgAndUse

Control #:EA4#4642
-Anomaly EA4#2363 fixed.
-Added a range limitter for delta value of each phase
feedback count accumulator to avoid overflow for phase on time measured.
- Changes are highlighted with red foreground color

Requirement

Rejected

FDD

Long Name

Tauj1 Configuration And Use

Interface

Open

Model

Version that you started from. NOT the version you hope to release. If this will be v1.0.0, enter NA. Starting Baseline

1.1.0

Effort

Design

FMEA

Author

Review Effort(Hrs.)

Standards

*.m File

Corr+Verf effort(Hrs.)

Documentation

Cal Process

Total Effort (Hrs.)

0.00

Others

Total

Checklist No.

Description of Check

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

Section 1: Data Dictionary

Is Filename of Data Dictionary in correct format?

Yes

Is the FDD.Version property correctly updated?

Yes

Is the Data Dictionary Verification report error free?

Some violations are present for signals not avaiable in the Nexteer list and some variables are not in the Nexteer pattern. Correction of these violations are out of anomaly/work CR scope

Does FDD Long Name, Short Name, and Description match requirements?

Yes

Are all runnables defined?

Yes

Do runnables have the correct time step?

Yes

Do server runnables correctly define arguments?

Yes

Are all clients defined?

Do client definitions match the corresponding server runnable?

Does name and metadata of every signal match its corresponding interface signal?

Yes

Do output signal ranges match requirements (check DOOR min/max attributes too)?

Yes

Are calibration tables named correctly (e.g. AssiX and AssiY)?

Are all data types represented by released Data_Management classes?

Yes

Do all calibrations have correct values for all metadata?

Is NVM defined in the appropriate number of blocks?

Are constants defined with proper scope (local vs global)?

Yes

Are all dependent constants and calibrations included in one file?

Does FDD.DesignASIL match requirements?

Yes

Section 2: Model

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

Is filename of model in correct format?

Yes

Is Top level of model annotated with Requirements Baseline?

Yes

Is the Top level of the model annotated with Tool Dependencies?

Yes

Is Top level of model annotated with Change Log or History?

Yes

Is the 2nd level of model free from subsystems that are not Function-Call Subsystems?

Yes

Is the 2nd level of model free from arithmetic and logic operations?

Yes

Are the Runnable trigger signals named as "call_<Runnable>"?

Yes

Does 2nd level of model have a properly updated annotation with name, description, and intended baseline number?

Yes

Are all data flow layers free of Function-Call Subsystems and Memory Store blocks?

Yes

Does the Model have the confidentiality and copyright information inside all its Subsystems?

Yes

Are all the Memory Store blocks for PIM and Display Variables located on the 2nd level of model?

Yes

Is each diagnostic (NTC) capable of being set to "PASS"?

Does non-zero intialization of PIM occur in the function's Init runnable?

Does design properly include Set Ram Block Status when NVM RAM values change?

Does model include appropriate logic for dealing with missing or corrupted NVM data?

Does model execute without errors/warnings after loading NxtrMBDConfig configuration set?

Yes

Section 3: Requirements Linking

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

Are all requirements links of the format <FDDNumber>_<ObjectID>?

Yes

Does requirements HTML report reference only the DOORS module of this component for all links in the design?

Yes

Are linked blocks linked to the correct requirements(s)? (watch for problems due to copy/pasted blocks)

Yes

Is the list of unlinked blocks acceptable?

Yes

Section 4: Model Advisor

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

Was Model Advisor run with the correct configuration settings?

Yes

Is the Model Advisor rerport free from "Fails".

Yes

Are Model Advisor report "Warnings" acceptable?

Yes

Section 5: Delivery Package

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

Does Design folder contain only the model, data dictionary, and (optionally) a simulation setup script?

Yes

Does Doc folder contain a zipped HTML webview model?

Yes

Was webview model created without requirements highlighted?

Yes

Does Reports folder contain only the data dictionary verification report, Model Advisor report, and zipped requirements traceability report?

Yes

Section 6: Other Issus/Actions Identified

Document

Reference

Summary of resolution

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Section 7: APPROVALS

Role

First Review

Date

Attendance

Approval?

Function Owner*

Muragesh Asundi

3/14/2016

Yes

Peer Reviewer*

Jason Erlenbeck

Yes

Safety

Software

ESG / Systems

EPDT / CSE

Hardware

Test

Role

Second Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

Safety

Software

ESG / Systems

EPDT / CSE

Hardware

Test

Role

Third Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

Safety

Software

ESG / Systems

EPDT / CSE

Hardware

Test

Role

Fourth Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

Safety

Software

ESG / Systems

EPDT / CSE

Hardware

Test

Role

Add more if necessary

Date

Attendance

Approval?

P.S.:

Yes indicates adherence

No indicates non-adherence, reviewer shall provide suitable comments at the end of this document for each point.

NA indicates not applicable

Sheet 3: Template Change Log

Rev	Change	Author
01.00.05	Added lesson learned #3.5	MDK
01.00.06	Added lesson learned #3.6, 3.7 - Structure and writing of NVM in mfiles and models.	MDK
02.00.00	Combined ESG and Systems into one, compatible with Data_Management 2.13.0 of CreateDD and VerifyDD.	K. Derry
02.01.00	Added: Does FDD.DesignASIL match requirements? Added: Was webview model created without requirements highlighted? Removed: Redundant row in Data Dictionary section. Formatting: Column C now consistently center-justified.	K. Derry
02.02.00	Added: Are all data types represented by released Data_Management classes? Removed: Are all runnables defined? Rationale: Automated tools checking. Removed: Does the Component shortname match data dictionary FDD metadata? Removed: "Data store name must resolve to Simulink signal object" Edited: Model Advisor report should now be left unzipped.	K. Derry