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Component Design

1: CM475A_TSG31RegisterConfiguration
2: CM475A TSG31 DFMEA

Component Design

Module Detailled Design

CM475A_TSG31RegisterConfiguration.html

Component Documentation

CM475A TSG31 DFMEA.html

1 - CM475A_TSG31RegisterConfiguration

Overview

FieldNames
Registers

Sheet 1: FieldNames

Field Names

Address
(Hex)

Address
(Dec)

Setting

Setting Description

Requirement

Mode

Notes

Init

Periodic

Write Constraints

TSG31CTL0

TSG3nDWD

The output pulse width is set to 8 clocks.

Any

Diagnostic output is not used

Can be written at field or register level

TSG31CTL0

TSG3nMD[2:0]

001

Set HT-PWM mode (HT-PWM)

CM475A_57

HT-PWM

Can be written at field or register level

TSG31CTL1

TBA2

Disables detection of simultaneous active states of the TSG3nO5 and TSG3nO6 pins.

Any

The gate drive prevents simultaneous conduction. This extra protection is not needed

Can be written at field or register level

TSG31CTL1

TBA1

Disables detection of simultaneous active states of the TSG3nO3 and TSG3nO4 pins.

Any

The gate drive prevents simultaneous conduction. This extra protection is not needed

Can be written at field or register level

TSG31CTL1

TBA0

Disables detection of simultaneous active states of the TSG3nO1 and TSG3nO2 pins.

Any

The gate drive prevents simultaneous conduction. This extra protection is not needed

Can be written at field or register level

TSG31CTL1

PPC

Disables detection of I/O pattern difference.

120-DC

Mode not used

Can be written at field or register level

TSG31CTL1

PEC

Disables detection of the pattern error of the TSG3nPTSI2-0 pins.

120-DC

Mode not used

Can be written at field or register level

TSG31CTL1

TDC

Disables detection of the simultaneous trigger of the TSG3nOPCI0 and TSG3nOPCI1.

120-DC

Mode not used

Can be written at field or register level

TSG31CTL1

NDC

Disables detection of the noise generation on the TSG3nPTSI2-0 pins.

120-DC

Mode not used

Can be written at field or register level

TSG31CTL1

PRC

0: Disables detection of the reversal of the pattern of the TSG3nPTSI2-0 pins.

120-DC

Mode not used

Can be written at field or register level

TSG31CTL1

TSG3nPTC[1:0]

Disables detection of an abnormal toggle of the TSG3nPTSI2-0 pins.

120-DC

Mode not used

Can be written at field or register level

TSG31CTL2

CKS

Selects PCLK as a count clock.

Any

Other option is to use external clock

Can be written at field or register level

TSG31CTL3

RIA

The reload timing is set to peak reload timing (set by TSG3nCTL4.TSG3nPRE) and valley reload timing (set by TSG3nCTL4.TSG3nVRE).

Any

Selects the reload timing of the compare register values

Can be written at field or register level

TSG31CTL3

RMC

Reload mode (simultaneous rewrite)
Writing to registers to be reloaded enables reloading and the register values are rewritten simultaneously at the next reload timing. Writing to any register other than registers to be reloaded does not enable reloading.

Any

Can be written at field or register level

TSG31CTL4

PRE

Model

Disables reload operation at the peak timing of the 18-bit counter.

Any

Can be written at field or register level

TSG31CTL4

VRE

Model

Enables reload operation at the valley timing of the 18-bit counter.

Any

Can be written at field or register level

TSG31CTL4

PIE

Model

Disables generation of a peak interrupt (INTTSG3nIPEK) at the peak timing of the 18-bit counter. Interrupts are not skipped.

Any

Can be written at field or register level

TSG31CTL4

VIE

Model

Disables generation of a valley interrupt (INTTSG3nIVLY) at the valley timing of the 18-bit counter. Interrupts are not skipped.

CM475A_61
CM475A_64
CM475A_63

Any

Used for Valley DMA Trigger

Can be written at field or register level

TSG31CTL4

RCC

Model

Specifies the skipping rate of the interrupts (INTTSG3nIPEK and INTTSG3nIVLY) and reload. Skipping disabled.

Any

Don’t want to skip any reloads, all should happen immediately

Can be written at field or register level

TSG31CTL5

ACC

Specifies the skipping rate of the A/D conversion trigger

Any

Don't want to skip any ADC SOC triggers

Can be written at field or register level

TSG31CTL5

AT09

Disables generation of the A/D conversion trigger at the peak timing of the 18-bit sub-counter.

Any

Can be written at field or register level

TSG31CTL5

AT08

Disables generation of the A/D conversion trigger at the valley timing of the 18-bit sub-counter

Any

Can be written at field or register level

TSG31CTL5

AT07

Disables generation of the A/D conversion trigger at the match timing of the 18-bit counter value during decrementation with the TSG3nDCMP2E value.

Any

Can be written at field or register level

TSG31CTL5

AT06

Disables generation of the A/D conversion trigger at the match timing of the 18-bit counter value during incrementation with the TSG3nDCMP2E value

Any

Can be written at field or register level

TSG31CTL5

AT05

Enables generation of the A/D conversion trigger at the match timing of the 18-bit counter value during decrementation with the TSG3nDCMP1E value

Any

Can be written at field or register level

TSG31CTL5

AT04

Disables generation of the A/D conversion trigger at the match timing of the 18-bit counter value during incrementation with the TSG3nDCMP1E.

Any

Can be written at field or register level

TSG31CTL5

AT03

Disables generation of the A/D conversion trigger at the match timing of the 18-bit counter value during decrementation with the TSG3nDCMP0E value

Any

Can be written at field or register level

TSG31CTL5

AT02

Enables generation of the A/D conversion trigger at the timing of the 18-bit counter value during incrementation with the TSG3nDCMP0E.

Any

MtrCtrl - Peak

Can be written at field or register level

TSG31CTL5

AT01

Disables generation of the A/D conversion trigger at the timing of a peak interrupt (INTTSG3nIPEK) after being skipped.

Any

Can be written at field or register level

TSG31CTL5

AT00

Disables generation of the A/D conversion trigger at the timing of a valley interrupt (INTTSG3nIVLY) after being skipped.

Any

Can be written at field or register level

TSG31CTL6

ACC

Specifies the skipping rate of the A/D conversion trigger

Any

Can be written at field or register level

TSG31CTL6

AT19

Disables generation of the A/D conversion trigger at the peak timing of the 18-bit sub-counter.

Any

Can be written at field or register level

TSG31CTL6

AT18

Disables generation of the A/D conversion trigger at the valley timing of the 18-bit sub-counter

Any

Can be written at field or register level

TSG31CTL6

AT17

Disables generation of the A/D conversion trigger at the match timing of the 18-bit counter value during decrementation with the TSG3nDCMP2E value.

Any

Can be written at field or register level

TSG31CTL6

AT16

Disables generation of the A/D conversion trigger at the match timing of the 18-bit counter value during incrementation with the TSG3nDCMP2E value

Any

Can be written at field or register level

TSG31CTL6

AT15

Enables generation of the A/D conversion trigger at the match timing of the 18-bit counter value during decrementation with the TSG3nDCMP1E value

Any

2mSec

Can be written at field or register level

TSG31CTL6

AT14

Disables generation of the A/D conversion trigger at the match timing of the 18-bit counter value during incrementation with the TSG3nDCMP1E.

Any

Can be written at field or register level

TSG31CTL6

AT13

Disables generation of the A/D conversion trigger at the match timing of the 18-bit counter value during decrementation with the TSG3nDCMP0E value

Any

Can be written at field or register level

TSG31CTL6

AT12

Disables generation of the A/D conversion trigger at the timing of the 18-bit counter value during incrementation with the TSG3nDCMP0E.

Any

Can be written at field or register level

TSG31CTL6

AT11

Disables generation of the A/D conversion trigger at the timing of a peak interrupt (INTTSG3nIPEK) after being skipped.

Any

Can be written at field or register level

TSG31CTL6

AT10

Disables generation of the A/D conversion trigger at the timing of a valley interrupt (INTTSG3nIVLY) after being skipped.

Any

Can be written at field or register level

TSG31IOC0

TOE6

Enables control of TSG3nO6 to TSG3nO1 by rewriting TSG3nIOC2

Any

Can be written at field or register level

TSG31IOC0

TOE5

Enables control of TSG3nO6 to TSG3nO1 by rewriting TSG3nIOC2

Any

Can be written at field or register level

TSG31IOC0

TOE4

Enables control of TSG3nO6 to TSG3nO1 by rewriting TSG3nIOC2

Any

Can be written at field or register level

TSG31IOC0

TOE3

Enables control of TSG3nO6 to TSG3nO1 by rewriting TSG3nIOC2

Any

Can be written at field or register level

TSG31IOC0

TOE2

Enables control of TSG3nO6 to TSG3nO1 by rewriting TSG3nIOC2

Any

Can be written at field or register level

TSG31IOC0

TOE1

Enables control of TSG3nO6 to TSG3nO1 by rewriting TSG3nIOC2

Any

Can be written at field or register level

TSG31IOC1

PTS

Disables output of the toggle signal by edge detection of TSG3nPTSI0 to TSG3nPTSI2.

Any

Can be written at field or register level

TSG31IOC1

EOC

Disables generation of an error interrupt

Any

Can be written at field or register level

TSG31IOC1

WOC

Disables generation of a warning interrupt

Any

Can be written at field or register level

TSG31IOC1

TGS

Selects A/D conversion trigger output

Any

Not used

Can be written at field or register level

TSG31IOC1

TOS

Outputs the up/down count flag of the 18-bit counter

Any

Not used

Can be written at field or register level

TSG31IOC2

OL6

Active level is high level

Any

Can be written at field or register level

TSG31IOC2

OL5

Active level is high level

Any

Can be written at field or register level

TSG31IOC2

OL4

Active level is high level

Any

Can be written at field or register level

TSG31IOC2

OL3

Active level is high level

Any

Can be written at field or register level

TSG31IOC2

OL2

Active level is high level

Any

Can be written at field or register level

TSG31IOC2

OL1

Active level is high level

Any

Can be written at field or register level

TSG31IOC2

TO6

Latch level of output buffer is low level

Any

Can be written at field or register level

TSG31IOC2

TO5

Latch level of output buffer is low level

Any

Can be written at field or register level

TSG31IOC2

TO4

Latch level of output buffer is low level

Any

Can be written at field or register level

TSG31IOC2

TO3

Latch level of output buffer is low level

Any

Can be written at field or register level

TSG31IOC2

TO2

Latch level of output buffer is low level

Any

Can be written at field or register level

TSG31IOC2

TO1

Latch level of output buffer is low level

Any

Can be written at field or register level

TSG31IOC3

TOL6

Outputs the normal level.

Any

TSG3nTOL6 to 1 should be set to 0 in HT-PWM mode

Can be written at field or register level

TSG31IOC3

TOL5

Outputs the normal level.

Any

TSG3nTOL6 to 1 should be set to 0 in HT-PWM mode

Can be written at field or register level

TSG31IOC3

TOL4

Outputs the normal level.

Any

TSG3nTOL6 to 1 should be set to 0 in HT-PWM mode

Can be written at field or register level

TSG31IOC3

TOL3

Outputs the normal level.

Any

TSG3nTOL6 to 1 should be set to 0 in HT-PWM mode

Can be written at field or register level

TSG31IOC3

TOL2

Outputs the normal level.

Any

TSG3nTOL6 to 1 should be set to 0 in HT-PWM mode

Can be written at field or register level

TSG31IOC3

TOL1

Outputs the normal level.

Any

TSG3nTOL6 to 1 should be set to 0 in HT-PWM mode

Can be written at field or register level

TSG31STC

TBR2

Does not clear TSG3nTBF2

Any

TSG3n Status Clear Trigger Register

Can be written at field or register level

TSG31STC

TBR1

Does not clear TSG3nTBF1

Any

TSG3n Status Clear Trigger Register

Can be written at field or register level

TSG31STC

TBR0

Does not clear TSG3nTBF0

Any

TSG3n Status Clear Trigger Register

Can be written at field or register level

TSG31STC

PPR

Does not clear TSG3nPPF

Any

TSG3n Status Clear Trigger Register

Can be written at field or register level

TSG31STC

PER

Does not clear TSG3nPEF

Any

TSG3n Status Clear Trigger Register

Can be written at field or register level

TSG31STC

TDR

Does not clear TSG3nTDF

Any

TSG3n Status Clear Trigger Register

Can be written at field or register level

TSG31STC

NDR

Does not clear TSG3nNDF

Any

TSG3n Status Clear Trigger Register

Can be written at field or register level

TSG31STC

PRR

Does not clear TSG3nPRF

Any

TSG3n Status Clear Trigger Register

Can be written at field or register level

TSG31STC

PTR

Does not clear TSG3nPTF

Any

TSG3n Status Clear Trigger Register

Can be written at field or register level

TSG31TRG2

IMT

Disabled

Any

Anytime Rewrite Trigger

Can be written at field or register level

TSG31DTC0W

WRITE PROTECTION CODE CHECK

000000000000000

Any

Need to ask Milsap if this feature is required

Write at field level

TSG31DTC1W

WRITE PROTECTION CODE CHECK

000000000000000

Any

Need to ask Milsap if this feature is required

Write at field level

TSG31DTPR

DTCM

Any

Need to ask Milsap if this feature is required

Write at field level

TSG31DTPR

WROTE PROTECTION CODE CHECK

000000000000000

Any

Need to ask Milsap if this feature is required

Write at field level

TSG31TRG0

The timer is started

Any

TSG31DTC0W

DTC0 - DEAD TIME COMPARE

Model

Static

Any

TRUE

FALSE

Can be written at field or register level

TSG31DTC1W

DTC1 - DEAD TIME COMPARE

Model

Static

Any

TRUE

FALSE

Can be written at field or register level

TSG31DCMP2E

140

320

------

Any

------

TSG31DCMP1E

144

324

Model

Static

CM475A_56

Any

AdcStrtOfCnvn2

TRUE

FALSE

2mSec ADC SOC

TSG31DCMP0E

148

328

Model

Dynamic

CM475A_51

Any

AdcStrtOfCnvnMotCtrlPeak

TRUE

MtrCtrl Peak ADC SOC

TSG31CMP0E

14C

332

Model

Dynamic

Any

PWM Period

TRUE

Period

TSG31CMP12E

150

336

Model

Dynamic

CM475A_90

Any

DmaMotAg0SpiStrt

TRUE

MtrPos SPI

TSG31CMP11E

154

340

Model

Static

CM475A_65

Any

DmaTSG31Upd

TRUE

FALSE

TSG Update

TSG31CMP10E

158

344

From CMPWE

------

Any

PhaCUpprCmd

------

TSG31CMP9E

15C

348

From CMPWE

------

Any

PhaCLowrCmd

------

TSG31CMP8E

160

352

Model

------

CM475A_62

Any

DmaMotAg0SpiStrt

TRUE

FALSE

------

TSG31CMP7E

164

356

Model

Static

CM475A_52

Any

AdcStrtOfCnvnMotCtrlVly

TRUE

FALSE

MtrCtrl Valley ADC SOC

TSG31CMP6E

168

360

From CMPVE

------

Any

PhaBUpprCmd

------

100

TSG31CMP5E

16C

364

From CMPVE

------

Any

PhaBLowrCmd

------

101

TSG31CMP4E

170

368

------

Any

------

102

TSG31CMP3E

174

372

------

Any

------

103

TSG31CMP2E

178

376

From CMPUE

------

Any

PhaAUpprCmd

------

104

TSG31CMP1E

17C

380

From CMPUE

------

Any

PhaALowrCmd

------

105

TSG31CMPWE

180

384

Model

Dynamic

Any

------

TRUE

Phase A

106

TSG31CMPVE

184

388

Model

Dynamic

Any

------

TRUE

Phase B

107

TSG31CMPUE

188

392

Model

Dynamic

Any

------

TRUE

Phase C

108

109

TSG31CMP0

Never Write

Dynamic

Any

Period

Not applicable

110

TSG31DCMP0W

Never Write

Static, Dynamic

Any

2mSec ADC SOC, MtrCtrl Peak ADC SOC

Not applicable

111

TSG31DCMP2

Never Write

------

Any

------

Not applicable

112

TSG31CMP1

128

Never Write

------

Any

------

Not applicable

113

TSG31CMP2

132

Never Write

------

Any

------

Not applicable

114

TSG31CMP5

136

Never Write

------

Any

------

Not applicable

115

TSG31CMP6

140

Never Write

------

Any

------

Not applicable

116

TSG31CMP9

144

Never Write

------

Any

------

Not applicable

117

TSG31CMP10

148

Never Write

------

Any

------

Not applicable

118

TSG31CMP3

152

Never Write

------

Any

------

Not applicable

119

TSG31CMP4

156

Never Write

------

Any

------

Not applicable

120

TSG31CMP7

160

Never Write

Static

Any

MtrCtrl Valley ADC SOC

Not applicable

121

TSG31CMP8

164

Never Write

------

Any

------

Not applicable

122

TSG31CMP11

168

Never Write

Static

Any

TSG Update

Not applicable

123

TSG31CMP12

172

Never Write

Dynamic

Any

MtrPos SPI

Not applicable

124

TSG31CMPU

176

Never Write

Dynamic

Any

Phase C

Not applicable

125

TSG31CMPV

180

Never Write

Dynamic

Any

Phase B

Not applicable

126

TSG31CMPW

184

Never Write

Dynamic

Any

Phase A

Not applicable

127

128

TSG31CMP1W

Never Write

Any

Not applicable

129

TSG31CMP3W

Never Write

Any

Not applicable

130

TSG31CMP5W

Never Write

Any

Not applicable

131

TSG31CMP7W

Never Write

Any

Not applicable

132

TSG31CMP9W

Never Write

Any

Not applicable

133

TSG31CMP11W

Never Write

Any

Not applicable

134

135

TSG31CNT

Read Only

Any

Not applicable

136

TSG31CNTE

Read Only

Any

Not applicable

137

TSG31SBC

Read Only

Any

Not applicable

138

TSG31SBCE

Read Only

Any

Not applicable

139

TSG31STR0

CUF

Read Only

Any

140

TSG31STR0

SUF

Read Only

Any

141

TSG31STR0

RSF

Read Only

Any

142

TSG31STR0

Read Only

Any

143

TSG31STR1

TSF

Read Only

Any

144

TSG31STR1

OPF[2:0]

Read Only

Any

145

TSG31STR2

TBF2

Read Only

Any

146

TSG31STR2

TBF1

Read Only

Any

147

TSG31STR2

TBF0

Read Only

Any

148

TSG31STR2

PPF

Read Only

Any

149

TSG31STR2

PEF

Read Only

Any

150

TSG31STR2

TDF

Read Only

Any

151

TSG31STR2

NDF

Read Only

Any

152

TSG31STR2

PRF

Read Only

Any

153

TSG31STR2

PTF

Read Only

Any

154

155

TSG31TRG1

Never Write

Any

Do not write to this register

156

TSG31PAT0W

PAT5T

Never Write

120-DC

157

TSG31PAT0W

PAT4T

Never Write

120-DC

158

TSG31PAT0W

PAT3T

Never Write

120-DC

159

TSG31PAT0W

PAT2T

Never Write

120-DC

160

TSG31PAT0W

PAT1T

Never Write

120-DC

161

TSG31PAT0W

PAT0T

Never Write

120-DC

162

TSG31PAT1W

PAT5B

Never Write

120-DC

163

TSG31PAT1W

PAT4B

Never Write

120-DC

164

TSG31PAT1W

PAT3B

Never Write

120-DC

165

TSG31PAT1W

PAT2B

Never Write

120-DC

166

TSG31PAT1W

PAT1B

Never Write

120-DC

167

TSG31PAT1W

PAT0B

Never Write

120-DC

168

TSG31UPW

Never Write

SP-PWM

Not applicable

169

TSG31VPW

Never Write

SP-PWM

Not applicable

170

TSG31WPW

Never Write

SP-PWM

Not applicable

171

TSG31UPWE

Never Write

SP-PWM

Not applicable

172

TSG31VPWE

Never Write

SP-PWM

Not applicable

173

TSG31WPWE

Never Write

SP-PWM

Not applicable

174

TSG31HSPSHWE

Never Write

HSP-PWM

Not applicable

175

TSG31HSPSHVE

Never Write

HSP-PWM

Not applicable

176

TSG31HSPSHUE

Never Write

HSP-PWM

Not applicable

177

TSG31HSPCMWE

Never Write

HSP-PWM

Not applicable

178

TSG31HSPCMVE

Never Write

HSP-PWM

Not applicable

179

TSG31HSPCMUE

Never Write

HSP-PWM

Not applicable

180

TSG31CTL7

SPSTL2

Never Write

SP-PWM mode

SP-PWM

181

TSG31CTL7

SPSTL1

Never Write

SP-PWM mode

SP-PWM

182

TSG31CTL7

SPSTLO

Never Write

SP-PWM mode

SP-PWM

183

TSG31CTL8

120DCMC

Never Write

120-DC

184

TSG31OPT0

SOC

Never Write

Disables control by software

120-DC

185

TSG31OPT0

STE

Never Write

Disables the TSG3nPTSI0 to TSG3nPTSI2 and TSG3nOPCI0, and TSG3nOPCI1 inputs

120-DC

186

TSG31OPT0

POT

Never Write

Switches the output pattern by the external pattern input pins (TSG3nPTSI0 to TSG3nPTSI2) (pattern switch method)

120-DC

187

TSG31OPT0

PSS

Never Write

The pattern output order is not switched by TSG3nPSC

120-DC

188

TSG31OPT0

IDC

Never Write

Determines the output pattern from the TSG3nO1 to TSG3nO6 pins in combination with the TSG3nIDC and TSG3nSTR1.TSG3nTSF and TSG3nPSC signals

120-DC

189

TSG31OPT0

PSC

Never Write

Switches the timer output (TSG3nO1 to TSG3nO6) in the normal rotation

120-DC

190

TSG31OPT1

SPC[2:0]

Never Write

Specifies the timer output pattern when software output function is enabled and in 120-DC mode.

120-DC

Sheet 2: Registers

Data
Sheet
Order

Name

Symbol

Address

Reload

TSG3n control register 0

TSG3nCTL0

208H

Disabled

Config

8 bit Register

Reserved

TSG3nDWD

Reserved

TSG3nMD[2:0]

TSG3n control register 0

TSG3nCTL0

208H

Disabled

Init

Select HT-PWM Mode

TSG3n control register 1

TSG3nCTL1

20CH

Disabled

Config

16 bit Register

Reserved

TBA2

TBA1

TAB0

PPC

PEC

TDC

NDC

PRC

TSG3nPTC[1:0]

TSG3n control register 1

TSG3nCTL1

20CH

Disabled

Init

Enable detection of simultaneous pins on

TSG3n control register 2

TSG3nCTL2

780H

Disabled

Config

Reserved

CKS

TSG3n control register 2

TSG3nCTL2

780H

Disabled

Init

Selects PCLK as count clock

TSG3n control register 3

TSG3nCTL3

004H

Disabled

Config

8 bit Register

Reserved

RIA

RMC

TSG3n control register 3

TSG3nCTL3

004H

Disabled

Init

Set Reload mode, location set by CTL4

TSG3n control register 4

TSG3nCTL4

07CH

Enabled

Config

Reserved

PRE

VRE

PIE

VIE

RCC

TSG3n control register 4

TSG3nCTL4

07CH

Enabled

Init

Reload at Valley, no interrupts

TSG3n control register 5

TSG3nCTL5

008H

Disabled

Config

16 bit Register

Reserved

ACC

AT09

AT08

AT07

AT06

AT05

AT04

AT03

AT02

AT01

AT00

TSG3n control register 5

TSG3nCTL5

008H

Disabled

Init

Enables ADTRG0 on DCMP0E incrementing

TSG3n control register 6

TSG3nCTL6

00CH

Disabled

Config

16 bit Register

Reserved

ACC

AT19

AT18

AT07

AT06

AT05

AT04

AT03

AT02

AT01

AT00

TSG3n control register 6

TSG3nCTL6

00CH

Disabled

Init

Enables ADTRG0 on DCMP0E incrementing

TSG3n control register 7

TSG3nCTL7

218H

Disabled

Config

8 bit Register

Reserved

SPSTL2

SPSTL1

SPSTLO

TSG3n control register 7

TSG3nCTL7

218H

Disabled

Init

N/A for HT-PWM Mode

TSG3n control register 8

TSG3nCTL8

21CH

Disabled

Config

8 bit Register

Reserved

120DCMC

TSG3n control register 8

TSG3nCTL8

21CH

Disabled

Init

N/A for HT-PWM Mode

TSG3n I/O control register 0

TSG3nIOC0

200H

Disabled

Config

8 bit Register

Reserved

TOE6

TOE5

TOE4

TOE3

TOE2

TOE1

Reserved

TSG3n I/O control register 0

TSG3nIOC0

200H

Disabled

Init

TSG3n I/O control register 1

TSG3nIOC1

204H

Disabled

Config

8 bit Register

Reserved

PTS

EOC

WOC

TGS

TOS

TSG3n I/O control register 1

TSG3nIOC1

204H

Disabled

Init

TSG3n I/O control register 2

TSG3nIOC2

000H

Disabled

Config

16 bit Register

Reserved

OL6

OL5

OL4

OL3

OL2

OL1

RESERVED

TO6

TO5

TO4

TO3

TO2

TO1

RESERVED

TSG3n I/O control register 2

TSG3nIOC2

000H

Disabled

Init

TSG3n I/O control register 3

TSG3nIOC3

074H

Enabled

Config

RESERVED

TOL6

TOL5

TOL4

TOL3

TOL2

TOL1

RESERVED

TSG3n I/O control register 3

TSG3nIOC3

074H

Enabled

Init

TSG3n status register 0

TSG3nSTR0

010H

Disabled

Config

8 bit Register

Reserved

CUF

SUF

RSF

TSG3n status register 0

TSG3nSTR0

010H

Disabled

Init

TSG3n status register 1

TSG3nSTR1

014H

Disabled

Config

8 bit Register

Reserved

TSF

OPF[2:0]

TSG3n status register 1

TSG3nSTR1

014H

Disabled

Init

TSG3n status register 2

TSG3nSTR2

018H

Disabled

Config

16 bit Register

Reserved

TBF2

TBF1

TBF0

PPF

PEF

TDF

NDF

PRF

PTF

RESERVED

TSG3n status register 2

TSG3nSTR2

018H

Disabled

Init

TSG3n status clear trigger register

TSG3nSTC

01CH

Disabled

Config

16 bit Register

Reserved

TBR2

TBR1

TBR0

PPR

PER

TDR

NDR

PRR

PTR

RESERVED

TSG3n status clear trigger register

TSG3nSTC

01CH

Disabled

Init

TSG3n option register 0

TSG3nOPT0

020H

Disabled

Config

8 bit Register

Reserved

SOC

STE

POT

PSS

IDC

PSC

RESERVED

TSG3n option register 0

TSG3nOPT0

020H

Disabled

Init

TSG3n option register 1

TSG3nOPT1

024H

Disabled

Config

8 bit Register

Reserved

SPC[2:0]

TSG3n option register 1

TSG3nOPT1

024H

Disabled

Init

TSG3n trigger register 0

TSG3nTRG0

030H

Disabled

Config

8 bit Register

Reserved

TSG3n trigger register 0

TSG3nTRG0

030H

Disabled

Init

TSG3n trigger register 1

TSG3nTRG1

034H

Disabled

Config

8 bit Register

Reserved

TSG3n trigger register 1

TSG3nTRG1

034H

Disabled

Init

TSG3n trigger register 2

TSG3nTRG2

038H

Disabled

Config

8 bit Register

Reserved

IMT

TSG3n trigger register 2

TSG3nTRG2

038H

Disabled

Init

TSG3n counter read buffer register

TSG3nCNT

028H

Disabled

Config

16 bit Register

LOWER 16 BITS OF 18 BIT COUNTER

TSG3n counter read buffer register

TSG3nCNT

028H

Disabled

Init

TSG3n bit extended counter read buffer register

TSG3nCNTE

1A0H

Disabled

Config

RESERVED

18 BIT COUNTER

TSG3n bit extended counter read buffer register

TSG3nCNTE

1A0H

Disabled

Init

TSG3n sub-counter read buffer register

TSG3nSBC

02CH

Disabled

Config

16 bit Register

LOWER 16 BITS OF 18 BIT SUB COUNTER

TSG3n sub-counter read buffer register

TSG3nSBC

02CH

Disabled

Init

TSG3n bit extended sub-counter read buffer register

TSG3nSBCE

1A4H

Disabled

Config

RESERVED

18 BIT SUB COUNTER

TSG3n bit extended sub-counter read buffer register

TSG3nSBCE

1A4H

Disabled

Init

TSG3n compare register 0

TSG3nCMP0

058H

Enabled

Config

16 bit Register

LOWER 16 BITS OF 18 BIT COMPARE REGISTER

TSG3n compare register 0

TSG3nCMP0

058H

Enabled

Init

TSG3n bit extended compare register 0

TSG3nCMP0E

14CH

Enabled

Config

RESERVED

18 BIT COMPARE REGISTER

TSG3n bit extended compare register 0

TSG3nCMP0E

14CH

Enabled

Init

TSG3n compare register 1, 2

TSG3nCMP1W

040H

Enabled

Config

LOWER 16 BITS OF COMPARE 2

LOWER 16 BITS OF COMPARE 1

TSG3n compare register 1, 2

TSG3nCMP1W

040H

Enabled

Init

TSG3n compare register 3, 4

TSG3nCMP3W

04CH

Enabled

Config

LOWER 16 BITS OF COMPARE 4

LOWER 16 BITS OF COMPARE 3

TSG3n compare register 3, 4

TSG3nCMP3W

04CH

Enabled

Init

TSG3n compare register 5, 6

TSG3nCMP5W

044H

Enabled

Config

LOWER 16 BITS OF COMPARE 6

LOWER 16 BITS OF COMPARE 5

TSG3n compare register 5, 6

TSG3nCMP5W

044H

Enabled

Init

TSG3n compare register 7, 8

TSG3nCMP7W

050H

Enabled

Config

LOWER 16 BITS OF COMPARE 8

LOWER 16 BITS OF COMPARE 7

TSG3n compare register 7, 8

TSG3nCMP7W

050H

Enabled

Init

TSG3n compare register 9, 10

TSG3nCMP9W

048H

Enabled

Config

LOWER 16 BITS OF COMPARE 10

LOWER 16 BITS OF COMPARE 9

TSG3n compare register 9, 10

TSG3nCMP9W

048H

Enabled

Init

TSG3n compare register 11, 12

TSG3nCMP11W

054H

Enabled

Config

LOWER 16 BITS OF COMPARE 12

LOWER 16 BITS OF COMPARE 11

TSG3n compare register 11, 12

TSG3nCMP11W

054H

Enabled

Init

TSG3n compare register 1

TSG3nCMP1

080H

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 1

TSG3n compare register 1

TSG3nCMP1

080H

Enabled

Init

TSG3n compare register 2

TSG3nCMP2

084H

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 2

TSG3n compare register 2

TSG3nCMP2

084H

Enabled

Init

TSG3n compare register 3

TSG3nCMP3

098H

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 3

TSG3n compare register 3

TSG3nCMP3

098H

Enabled

Init

TSG3n compare register 4

TSG3nCMP4

09CH

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 4

TSG3n compare register 4

TSG3nCMP4

09CH

Enabled

Init

TSG3n compare register 5

TSG3nCMP5

088H

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 5

TSG3n compare register 5

TSG3nCMP5

088H

Enabled

Init

TSG3n compare register 6

TSG3nCMP6

08CH

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 6

TSG3n compare register 6

TSG3nCMP6

08CH

Enabled

Init

TSG3n compare register 7

TSG3nCMP7

0A0H

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 7

TSG3n compare register 7

TSG3nCMP7

0A0H

Enabled

Init

TSG3n compare register 8

TSG3nCMP8

0A4H

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 8

TSG3n compare register 8

TSG3nCMP8

0A4H

Enabled

Init

TSG3n compare register 9

TSG3nCMP9

090H

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 9

TSG3n compare register 9

TSG3nCMP9

090H

Enabled

Init

TSG3n compare register 10

TSG3nCMP10

094H

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 10

TSG3n compare register 10

TSG3nCMP10

094H

Enabled

Init

TSG3n compare register 11

TSG3nCMP11

0A8H

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 11

TSG3n compare register 11

TSG3nCMP11

0A8H

Enabled

Init

TSG3n compare register 12

TSG3nCMP12

0ACH

Enabled

Config

RESERVED

LOWER 16 BITS OF COMPARE 12

TSG3n compare register 12

TSG3nCMP12

0ACH

Enabled

Init

TSG3n bit extended compare register 1

TSG3nCMP1E

17CH

Enabled

Config

RESERVED

EXTENDED COMPARE 1

TSG3n bit extended compare register 1

TSG3nCMP1E

17CH

Enabled

Init

TSG3n bit extended compare register 2

TSG3nCMP2E

178H

Enabled

Config

RESERVED

EXTENDED COMPARE 2

TSG3n bit extended compare register 2

TSG3nCMP2E

178H

Enabled

Init

TSG3n bit extended compare register 3

TSG3nCMP3E

164H

Enabled

Config

RESERVED

EXTENDED COMPARE 3

TSG3n bit extended compare register 3

TSG3nCMP3E

164H

Enabled

Init

TSG3n bit extended compare register 4

TSG3nCMP4E

160H

Enabled

Config

RESERVED

EXTENDED COMPARE 4

TSG3n bit extended compare register 4

TSG3nCMP4E

160H

Enabled

Init

TSG3n bit extended compare register 5

TSG3nCMP5E

174H

Enabled

Config

RESERVED

EXTENDED COMPARE 5

TSG3n bit extended compare register 5

TSG3nCMP5E

174H

Enabled

Init

TSG3n bit extended compare register 6

TSG3nCMP6E

170H

Enabled

Config

RESERVED

EXTENDED COMPARE 6

TSG3n bit extended compare register 6

TSG3nCMP6E

170H

Enabled

Init

TSG3n bit extended compare register 7

TSG3nCMP7E

15CH

Enabled

Config

RESERVED

EXTENDED COMPARE 7

TSG3n bit extended compare register 7

TSG3nCMP7E

15CH

Enabled

Init

TSG3n bit extended compare register 8

TSG3nCMP8E

158H

Enabled

Config

RESERVED

EXTENDED COMPARE 8

TSG3n bit extended compare register 8

TSG3nCMP8E

158H

Enabled

Init

TSG3n bit extended compare register 9

TSG3nCMP9E

16CH

Enabled

Config

RESERVED

EXTENDED COMPARE 9

TSG3n bit extended compare register 9

TSG3nCMP9E

16CH

Enabled

Init

TSG3n bit extended compare register 10

TSG3nCMP10E

168H

Enabled

Config

RESERVED

EXTENDED COMPARE 10

TSG3n bit extended compare register 10

TSG3nCMP10E

168H

Enabled

Init

TSG3n bit extended compare register 11

TSG3nCMP11E

154H

Enabled

Config

RESERVED

EXTENDED COMPARE 11

TSG3n bit extended compare register 11

TSG3nCMP11E

154H

Enabled

Init

TSG3n bit extended compare register 12

TSG3nCMP12E

150H

Enabled

Config

RESERVED

EXTENDED COMPARE 12

TSG3n bit extended compare register 12

TSG3nCMP12E

150H

Enabled

Init

TSG3n diagnostic output compare register 0, 1

TSG3nDCMP0W

05CH

Enabled

Config

LOWER 16 BITS OF DCMP1E

LOWER 16 BITS OF DCMP0E

TSG3n diagnostic output compare register 0, 1

TSG3nDCMP0W

05CH

Enabled

Init

TSG3n diagnostic output compare register 2

TSG3nDCMP2

060H

Enabled

Config

RESERVED

LOWER 16 BITS OF DCMP2E

TSG3n diagnostic output compare register 2

TSG3nDCMP2

060H

Enabled

Init

TSG3n bit extended diagnostic output compare register 0

TSG3nDCMP0E

148H

Enabled

Config

RESERVED

EXTENDED DIAGNOSTIC OUTPUT COMPARE 0

TSG3n bit extended diagnostic output compare register 0

TSG3nDCMP0E

148H

Enabled

Init

TSG3n bit extended diagnostic output compare register 1

TSG3nDCMP1E

144H

Enabled

Config

RESERVED

EXTENDED DIAGNOSTIC OUTPUT COMPARE 1

TSG3n bit extended diagnostic output compare register 1

TSG3nDCMP1E

144H

Enabled

Init

TSG3n bit extended diagnostic output compare register 2

TSG3nDCMP2E

140H

Enabled

Config

RESERVED

EXTENDED DIAGNOSTIC OUTPUT COMPARE 2

TSG3n bit extended diagnostic output compare register 2

TSG3nDCMP2E

140H

Enabled

Init

TSG3n pattern register 0

TSG3nPAT0W

064H

Enabled

Config

RESERVED

PAT5T

PAT4T

PAT3T

PAT2T

PAT1T

PAT0T

TSG3n pattern register 0

TSG3nPAT0W

064H

Enabled

Init

TSG3n pattern register 1

TSG3nPAT1W

068H

Enabled

Config

RESERVED

PAT5B

PAT4B

PAT3B

PAT2B

PAT1B

PAT0B

TSG3n pattern register 1

TSG3nPAT1W

068H

Enabled

Init

TSG3n dead time control register 0

TSG3nDTC0W

06CH

Enabled

Config

RESERVED

WRITE PROTECTION CODE CHECK

RESERVED

DTC0 - DEAD TIME COMPARE

TSG3n dead time control register 0

TSG3nDTC0W

06CH

Enabled

Init

TSG3n dead time control register 1

TSG3nDTC1W

070H

Enabled

Config

RESERVED

WRITE PROTECTION CODE CHECK

RESERVED

DTC1 - DEAD TIME COMPARE

TSG3n dead time control register 1

TSG3nDTC1W

070H

Enabled

Init

TSG3n HT-PWM U phase compare register

TSG3nCMPU

0B0H

Enabled

Config

16 bit Register

LOWER 16 BITS OF CMPUE

TSG3n HT-PWM U phase compare register

TSG3nCMPU

0B0H

Enabled

Init

TSG3n HT-PWM V phase compare register

TSG3nCMPV

0B4H

Enabled

Config

16 bit Register

LOWER 16 BITS OF CMPVE

TSG3n HT-PWM V phase compare register

TSG3nCMPV

0B4H

Enabled

Init

TSG3n HT-PWM W phase compare register

TSG3nCMPW

0B8H

Enabled

Config

16 bit Register

LOWER 16 BITS OF CMPWE

TSG3n HT-PWM W phase compare register

TSG3nCMPW

0B8H

Enabled

Init

TSG3n bit extended HT-PWM U phase compare register

TSG3nCMPUE

188H

Enabled

Config

RESERVED

EXTENDED U PHASE COMPARE

TSG3n bit extended HT-PWM U phase compare register

TSG3nCMPUE

188H

Enabled

Init

TSG3n bit extended HT-PWM V phase compare register

TSG3nCMPVE

184H

Enabled

Config

RESERVED

EXTENDED V PHASE COMPARE

TSG3n bit extended HT-PWM V phase compare register

TSG3nCMPVE

184H

Enabled

Init

TSG3n bit extended HT-PWM W phase compare register

TSG3nCMPWE

180H

Enabled

Config

RESERVED

EXTENDED W PHASE COMPARE

TSG3n bit extended HT-PWM W phase compare register

TSG3nCMPWE

180H

Enabled

Init

TSG3n SP-PWM U phase active width register

TSG3nUPW

0BCH

Enabled

Config

16 bit Register

LOWER 16 BITS OF EXTENDED U PHASE ACTIVE WIDTH

TSG3n SP-PWM U phase active width register

TSG3nUPW

0BCH

Enabled

Init

TSG3n SP-PWM V phase active width register

TSG3nVPW

0C0H

Enabled

Config

16 bit Register

LOWER 16 BITS OF EXTENDED V PHASE ACTIVE WIDTH

TSG3n SP-PWM V phase active width register

TSG3nVPW

0C0H

Enabled

Init

TSG3n SP-PWM W phase active width register

TSG3nWPW

0C4H

Enabled

Config

16 bit Register

LOWER 16 BITS OF EXTENDED W PHASE ACTIVE WIDTH

TSG3n SP-PWM W phase active width register

TSG3nWPW

0C4H

Enabled

Init

TSG3n bit extended SP-PWM U phase active width register

TSG3nUPWE

198H

Enabled

Config

RESERVED

EXTENDED U PHASE ACTIVE WIDTH

TSG3n bit extended SP-PWM U phase active width register

TSG3nUPWE

198H

Enabled

Init

TSG3n bit extended SP-PWM V phase active width register

TSG3nVPWE

194H

Enabled

Config

RESERVED

EXTENDED V PHASE ACTIVE WIDTH

TSG3n bit extended SP-PWM V phase active width register

TSG3nVPWE

194H

Enabled

Init

TSG3n bit extended SP-PWM W phase active width register

TSG3nWPWE

190H

Enabled

Config

RESERVED

EXTENDED W PHASE ACTIVE WIDTH

TSG3n bit extended SP-PWM W phase active width register

TSG3nWPWE

190H

Enabled

Init

TSG3n HSP-PWM W phase shift register

TSG3nHSPSHWE

120H

Enabled

Config

RESERVED

EXTENDED PWM MODE W PHASE SHIFT REGISTER

TSG3n HSP-PWM W phase shift register

TSG3nHSPSHWE

120H

Enabled

Init

TSG3n HSP-PWM V phase shift register

TSG3nHSPSHVE

124H

Enabled

Config

RESERVED

EXTENDED PWM MODE V PHASE SHIFT REGISTER

TSG3n HSP-PWM V phase shift register

TSG3nHSPSHVE

124H

Enabled

Init

TSG3n HSP-PWM U phase shift register

TSG3nHSPSHUE

128H

Enabled

Config

RESERVED

EXTENDED PWM MODE U PHASE SHIFT REGISTER

TSG3n HSP-PWM U phase shift register

TSG3nHSPSHUE

128H

Enabled

Init

TSG3n HSP-PWM W phase compare register

TSG3nHSPCMWE

12CH

Enabled

Config

RESERVED

EXTENDED PWM MODE W PHASE COMPARE REGISTER

TSG3n HSP-PWM W phase compare register

TSG3nHSPCMWE

12CH

Enabled

Init

TSG3n HSP-PWM V phase compare register

TSG3nHSPCMVE

130H

Enabled

Config

RESERVED

EXTENDED PWM MODE V PHASE COMPARE REGISTER

TSG3n HSP-PWM V phase compare register

TSG3nHSPCMVE

130H

Enabled

Init

TSG3n HSP-PWM U phase compare register

TSG3nHSPCMUE

134H

Enabled

Config

RESERVED

EXTENDED PWM MODE U PHASE COMPARE REGISTER

TSG3n HSP-PWM U phase compare register

TSG3nHSPCMUE

134H

Enabled

Init

TSG3n dead time protection register

TSG3nDTPR

210H

Disabled

Config

16 bit Register

DTCM

WROTE PROTECTION CODE CHECK

TSG3n dead time protection register

TSG3nDTPR

210H

Disabled

Init

2 - CM475A TSG31 DFMEA

Overview

Detailed Drawing
IOBlock
Sheet3

Sheet 1: Detailed Drawing

Sheet 2: IOBlock

Sheet 3: Sheet3

Output	Failure	Functional Effect	System Response
AdcStrtOfCnvn2	Stuck On	Multiple 2mSec ADC reads, ADC accuracy degredation
AdcStrtOfCnvn2	Stuck Off	No 2mSec ADC, values stuck at last value
AdcStrtOfCnvnMotCtrlPeak	Stuck On	Multiple MtrCtrl ADC reads, Multiple MtrCtrlISRs, Processor starvation
AdcStrtOfCnvnMotCtrlPeak	Stuck Off	No MtrCtrlADC read, loss of MtrCtrlISR
AdcStrtOfCnvnMotCtrlVly	Stuck On	Multiple MtrCtrl Valley ADC reads, ADC accuracy degredation
AdcStrtOfCnvnMotCtrlVly	Stuck Off	No MtrCtrl Valley ADC reads, loss of shunt current
DmaMotPosnSpiStrt	Stuck On	Mulitple MtrPos SPI starts, DMA starvation - delayed data
DmaMotPosnSpiStrt	Stuck Off	No SPI based MtrPos reads
DMATSG31Update	Stuck On	Continually update TSG31 updates, DMA starvation (extinguished)
DMATSG31Update	Stuck Off	No TSG31 updates, stuck on last value
DmaVlyTrig	Stuck On	DMA starvation
DmaVlyTrig	Stuck Off	Loss of interloop data transfer, data stuck at last value
DataTrfToMotCtrl1MilliSec	Stuck On	DMA starvation
DataTrfToMotCtrl1MilliSec	Stuck Off	Loss of interloop data transfer, data stuck at last value
DataTrfTo2MilliSecMotCtrl	Stuck On	DMA starvation
DataTrfTo2MilliSecMotCtrl	Stuck Off	Loss of interloop data transfer, data stuck at last value
DataTrfTo1MilliSecMotCtrl	Stuck On	DMA starvation
DataTrfTo1MilliSecMotCtrl	Stuck Off	Loss of interloop data transfer, data stuck at last value
PhaALowrCmd	Stuck On	Wrong output torque
PhaALowrCmd	Stuck Off	Wrong output torque
PhaALowrCmd	Loss of deadtime	Bridge shoot through
PhaAUpprCmd	Stuck On	Wrong output torque
PhaAUpprCmd	Stuck Off	Wrong output torque
PhaAUpprCmd	Loss of deadtime	Bridge shoot through
PhaBLowrCmd	Stuck On	Wrong output torque
PhaBLowrCmd	Stuck Off	Wrong output torque
PhaBLowrCmd	Loss of deadtime	Bridge shoot through
PhaBUpprCmd	Stuck On	Wrong output torque
PhaBUpprCmd	Stuck Off	Wrong output torque
PhaBUpprCmd	Loss of deadtime	Bridge shoot through
PhaCLowrCmd	Stuck On	Wrong output torque
PhaCLowrCmd	Stuck Off	Wrong output torque
PhaCLowrCmd	Loss of deadtime	Bridge shoot through
PhaCUpprCmd	Stuck On	Wrong output torque
PhaCUpprCmd	Stuck Off	Wrong output torque
PhaCUpprCmd	Loss of deadtime	Bridge shoot through