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Component Implementation

1: requirements
2: TSG31CfgAndUse Integration Manual
3: TSG31CfgAndUse_MDD
4: TSG31CfgAndUse_Peer_Review

Component Implementation

Component Documentation

1 - requirements

FDD	ID	Source	Function	Line(s)	Status	Comment
		.SwFileName	.SwFuncName	.SwLines	.SwStatus	.SwComment
CM475A	15	CDD_TSG31CfgAndUse.c	TSG31CfgAndUsePer2	475-523,674-692,711-719	I
CM475A	58	CDD_TSG31CfgAndUse.c	TSG31CfgAndUseInit1	220,221	I
CM475A	67	CDD_TSG31CfgAndUse.c	TSG31CfgAndUsePer2	480-528,679-697	I
CM475A	71	CDD_TSG31CfgAndUse.c	TSG31CfgAndUsePer2	476-524,675-693	I
CM475A	70	CDD_TSG31CfgAndUse.c	TSG31CfgAndUsePer2	477-525,676-694	I
CM475A	68	CDD_TSG31CfgAndUse.c	TSG31CfgAndUsePer2	479-527,678-696	I
CM475A	69	CDD_TSG31CfgAndUse.c	TSG31CfgAndUsePer2	478-526,677-695	I
CM475A	80	CDD_TSG31CfgAndUse.c	TSG31CfgAndUseInit1	225	I
CM475A	86	CDD_TSG31CfgAndUse.c	TSG31CfgAndUsePer2	472	I

2 - TSG31CfgAndUse Integration Manual

TSG31CfgAndUse

Integration Manual

VERSION: 1.0

DATE: 28-Apr-2015

Revision History

Sl. No.	Description	Author	Version	Date
1	Initial version	K Creager	1.0	28-Apr-2015

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 Non RTE NvM Blocks 10

7.4 RTE NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

Abbreviation	Description
DFD	Design functional diagram
MDD	Module design Document
FDD	Functional Design Document

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.	Title	Version
<1>	MDD Guidelines	Software Process Release 03.06.00
<2>	Software Naming Conventions	Software Process Release 03.06.00
<3>	Design and Coding Standards	Software Process Release 03.06.00
<4>	FDD: CM475A_TSG31CfgAndUse_Design	See Synergy subproject version

Dependencies

SWCs

Module	Required Feature
<Name of SWC>	<Addition of global data, function>*.

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

See FDD – CM475A_TSG31CfgAndUse_DataDict.m file

Configuration REQUIREMeNTS

Build Time Config

Modules	Notes
None

Configuration Files to be provided by Integration Project

Da Vinci Parameter Configuration Changes

Parameter	Notes	SWC
<Configurator Changes for parameters>

DaVinci Interrupt Configuration Changes

ISR Name	VIM #	Priority Dependency	Notes
<Configurator Changes for Interrupts>

Manual Configuration Changes

Constant	Notes	SWC
<Additional configuration changes>

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

See FDD – CM475A_TSG31CfgAndUse_DataDict.m file

Required Global Data Outputs

See FDD – CM475A_TSG31CfgAndUse_DataDict.m file

Specific Include Path present

Yes

Runnable Scheduling

This section specifies the required runnable scheduling.

Init	Scheduling Requirements	Trigger
TSG31CfgAndUseInit1	None	RTE/ Init

Runnable	Scheduling Requirements	Trigger
TSG31CfgAndUsePer1	None	Motor control runnable
TSG31CfgAndUsePer2	None	RTE/2 ms

Memory Map REQUIREMENTS

Mapping

Memory Section	Contents	Notes
MotCtrl_START_SEC_CODE	Motor Control runnables

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Feature	RAM	ROM
<Memmap usuage info>

Table 1: ARM Cortex R4 Memory Usage

Non RTE NvM Blocks

Block Name

<NVM block used Non RTE functions >

Note : Size of the NVM block if configured in developer

RTE NvM Blocks

Block Name

<NVM block used in RTE functions >

Note : Size of the NVM block if configured in developer

Compiler Settings

Preprocessor MACRO

<Define all the preprocessor Macros needed and conditions when needed>.

Optimization Settings

<Define Optimization levels that are needed and conditions when needed>.

Appendix

<This section is for appendix>

3 - TSG31CfgAndUse_MDD

TSG31 Timer Subsystem Configuration and Use

Module Design Document

VERSION: 2.0

DATE: 20-Jun-2015

Revision History

Description	Author	Version	Date
Initial Version	K. Creager	1.0	28-Apr-2015
Remove CnvNanoSecToHalfTmrCnt() function and add masking constant for changes in FDD ver 1.3.0	K. Creager	2.0	20-Jun-2015

Table of Contents

1 Abbrevations And Acronyms 5

2 References 6

3 TSG31CfgAndUse High-Level Description 7

3.1 Design details of software module 7

3.2 Graphical representation of CDD_TSG31CfgAndUse 7

3.3 Data Flow Diagram 7

3.3.1 Module level DFD 8

3.3.2 Sub-Module level DFD 8

3.4 COMPONENT FLOW DIAGRAM 8

4 Variable Data Dictionary 9

4.1 User defined typedef definition/declaration 9

4.2 Variable definition for enumerated types 9

5 Constant Data Dictionary 10

5.1 Program(fixed) Constants 10

5.1.1 Embedded Constants 10

5.1.1.1 Local 10

5.1.1.2 Global 10

5.1.2 Module specific Lookup Tables Constants 10

6 Software Module Implementation 11

6.1 Sub-Module Functions 11

6.1.1 Motor Control Periodic: TSG31CfgAndUsePer1 11

6.1.1.1 Design Rationale 11

6.2 Initialization Functions 11

6.2.1 Init: TSG31CfgAndUseInit1 11

6.2.1.1 Design Rationale 11

6.2.1.2 Module Outputs 11

6.2.1.3 Module Internal 11

6.3 PERIODIC FUNCTIONS 11

6.3.1 Per: TSG31CfgAndUsePer2 11

6.3.1.1 Design Rationale 11

6.3.1.2 Store Module Inputs to Local copies 11

6.3.1.3 (Processing of function)……… 11

6.3.1.4 Store Local copy of outputs into Module Outputs 11

6.4 Interrupt Functions 12

6.5 Serial Communication Functions 12

6.6 Local Function/Macro Definitions 12

6.6.1 Local Function #1 12

6.6.1.1 Description 12

6.6.2 Local Function #2 12

6.6.2.1 Description 12

6.6.3 Local Function #3 12

6.6.3.1 Description 12

6.6.4 Local Function #4 12

6.6.4.1 Description 13

6.6.5 Local Function #5 13

6.6.5.1 Description 13

6.6.6 Local Function #6 13

6.6.6.1 Description 13

6.6.7 Local Function #7 13

6.6.7.1 Description 13

6.6.7.2 Design Rationale 13

6.6.8 Local Function #8 14

6.6.8.1 Description 14

6.6.8.2 Design Rationale 14

6.7 GLObAL Function/Macro Definitions 14

6.8 TRANSIENT FUNCTIONS 14

7 Known Limitations With Design 15

8 UNIT TEST CONSIDERATION 16

9 Appendix 17

Abbrevations And Acronyms

Abbreviation	Description
DFD	Design functional diagram
MDD	Module design Document
FDD	Functional Design Document

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.	Title	Version
<1>	MDD Guidelines	Software Process Release 04.00.00
<2>	Software Naming Conventions	Software Process Release 04.00.00
<3>	Design and Coding standards	Software Process Release 04.00.00
<4>	FDD: CM475A_TSG31CfgAndUse_Design	See Synergy subproject version

TSG31CfgAndUse High-Level Description

The CDD_TSG31CfgAndUse component is the complex driver for the TSG31 timer subsystem. The timer subsystem is used to trigger DMA transfers and SPI transfers, and to set the GPIO pins for the three phase PWM outputs. The component contains two .c source files, both described in this MDD: CDD_TSG31CfgAndUse.c contains the RTE runnables; CDD_TSG31CfgAndUse_MotCtrl.c contains the motor control runnable.

Design details of software module

See FDD.

Graphical representation of CDD_TSG31CfgAndUse

Data Flow Diagram

See FDD.

Module level DFD

See FDD.

Sub-Module level DFD

See FDD.

COMPONENT FLOW DIAGRAM

See FDD.

Variable Data Dictionary

User defined typedef definition/declaration

<This section documents any user types uniquely used for the module.>

Typedef Name

Element Name

User Defined Type

Legal Range

(min)

Legal Range

(max)

<(Name given for the user defined typdef of type struct/union)

(Variable name as qualified Refer[2])>

<(Variable name qualified Refer[2])>

<(Variable name qualified Refer[2>

Variable definition for enumerated types

Enum Name

Element Name

Value

SysSt1

SYSST_DI

SYSST_OFF

SYSST_ENA

SYSST_WRMININ

MotCurrEolCalSt2

MCECS_OFFSCMDSTRT

MCECS_OFFSCMDHI

MCECS_OFFSCMDLO

MCECS_OFFSCMDZERO

MCECS_OFFSCMDEND

MCECS_GAINCMDAD

MCECS_GAINCMDBE

MCECS_GAINCMDCF

MCECS_CMDSAFEST

Constant Data Dictionary

Program(fixed) Constants

Embedded Constants

< All program specific constants will be defined in detail >

Local

Constant Name	Resolution	Units	Value
ROUNDGTERM_CNT_U13P19	P19	Cnt	262144 counts = 0.5 p19
PWMTMRPERDIVSSCAG_CNT_U16	1	Cnt	19
CLRBIT0MASK_CNT_U32	1	Cnt	0xFFFFFFFE

Global

<This section lists the global constants used by the module. For details on global constants, refer to the Data Dictionary for the application>

Constant Name

See FDD – CM475A_TSG31CfgAndUse_DataDict.m file

Module specific Lookup Tables Constants

<(This is for lookup tables (arrays) with fixed values, same name as other tables)>

Constant Name	Resolution	Value	Software Segment
<Refer Constant name qualified in [2]>	<Refer MDD guidelines [1]>	<Refer MDD guidelines [1]>	<Refer MDD guidelines [1]>

Software Module Implementation

Note: All the non RTE signals defined in m file are implemented as global varibles managed by motor control manager. RTE can not manage motor control runnables inputs and outputs.

Sub-Module Functions

Motor Control Periodic: TSG31CfgAndUsePer1

See FDD TSG31CfgAndUsePer1 model block.

Design Rationale

The truth table in the TSG31CfgAndUsePer1 model block is just selecting between four sets of statements based on the value of a single variable. This was implemented as an if/else if. For run-time efficiency, since this is a motor control runnable, the “normal operation” case was checked first; since the normal operation and default cases are the same, the statements in this row of the truth table action table are repeated in the trailing else of the if/else.

Initialization Functions

Init: TSG31CfgAndUseInit1

Design Rationale

All register initialization that is allowed at the register level (see FieldNames tab of the CM475A_TSG31RegisterConfiguration.xlms spreadsheet in the FDD) is done at the register level to save execution time as compared to the read/modify/writes that would be needed to initialize at the field level. Field level initialization done only where required by the spreadsheet.

Module Outputs

See FDD: TSG31CfgAndUseInit1 model block and the FieldNames tab of the CM475A_TSG31RegisterConfiguration.xlms spreadsheet.

Module Internal

See FDD: TSG31CfgAndUseInit1 model block for Per Instance Memory initialization.

PERIODIC FUNCTIONS

Per: TSG31CfgAndUsePer2

Design Rationale

Each action block of the switch/case was implemented as a local function. To minimize complexity, the “Out1” truth table output and the switch case block were combined in the implementation with nested “if”s which directly call the switch/case action functions

Store Module Inputs to Local copies

See FDD: TSG31CfgAndUsePer2 model block.

(Processing of function)………

See FDD: TSG31CfgAndUsePer2 model block.

Store Local copy of outputs into Module Outputs

See FDD: TSG31CfgAndUsePer2 model block

Interrupt Functions

None

Serial Communication Functions

None

Local Function/Macro Definitions

Local Function #1

Function Name	NoTranSysStIsEn	Type	Min	Max
Arguments Passed	MotCurrEolCalSt_Cnt_T_enum	MotCurrEolCalSt2	0	8
Return Value	N/A

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/No Transition SysState = Enable

Local Function #2

Function Name	TranFromEn	Type	Min	Max
Arguments Passed	None
Return Value	N/A

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/Transition from Enable

Local Function #3

Function Name	TranToEn	Type	Min	Max
Arguments Passed	None
Return Value	N/A

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/Transition to Enable

Local Function #4

Function Name	NoTranSysStNotEn	Type	Min	Max
Arguments Passed	None
Return Value	N/A

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/No Transition SysState != Enable

Local Function #5

Function Name	MapFetCtrlSigToGpioAndSetLow	Type	Min	Max
Arguments Passed	None
Return Value	N/A

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/Transition from Enable/Map FET Ctrl Signals to GPIO and Set Low (also same block name in other model layers)

Local Function #6

Function Name	MapPinsToGpio	Type	Min	Max
Arguments Passed	None
Return Value	N/A

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/Transition from Enable/Map FET Ctrl Signals to GPIO and Set Low/Map Pins to GPIO (also same block name in other model layers)

Local Function #7

Function Name	CnvNanoSecToTmrCnt	Type	Min	Max
Arguments Passed	Ti_NanoSec_T_u32	uint32	0	100000
Return Value	Timer counts corresponding to the input time	uint32	0	8000

Description

See FDD model block: CM475A_TSG31CfgAndUse_ModelLibrary_Rev001/RawTime_NanoSec to RawTimerCount_Cnt Conversion Block

Design Rationale

Because this function is called by a motor control runnable, it is coded as an inline function to maximize the chance that the compiler will inline it, in order to improve runtime efficiency of the motor control loop.

GLObAL Function/Macro Definitions

None

TRANSIENT FUNCTIONS

None

Known Limitations With Design

Expected input ranges of the nanosecond to timer count conversion functions are based on FDD assumptions about the minimum PWM period that may ever be used, as stated in comments in the FDD model.

UNIT TEST CONSIDERATION

None

Appendix

<This section is for appendix>

4 - TSG31CfgAndUse_Peer_Review

Overview

Summary Sheet
Synergy Project
Source Code
PolySpace

Sheet 1: Summary Sheet

Rev 7.1

8-Jun-15

Peer Review Summary Sheet

Synergy Project Name:

kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. CM475A_TSG31CfgAndUse_Impl

Revision / Baseline:

kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. 1.4.0

Change Owner:

kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Avinash James

Work CR ID:

EA4#8923

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

N/A

MDD

Yes

Source Code

Yes

PolySpace

N/A

Integration Manual

N/A

Davinci Files

Comments:

Conditional Enabling of the peak interrupt for TSG31

General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request. (Note: If this peer review form was not
completed for pervious versions of this component, the Change Owner should review the entire component and complete the checklist in its entirety prior and check
the form into Syngery. This may be done prior to reviewing the modifications for this Change Result)
- The Change Owner shall responsible for completing the entire checklist (Pre and Group review items) prior holding the initial group review.
- New components should include FDD Owner and Intergator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Select "Yes" and add "N/A" to the comments for checklist items that are not applicable for this change
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.

Sheet 2: Synergy Project

Peer Review Meeting Log (Component Synergy Project Review)

Quality Check Items:

Rationale is required for all answers of No

Prep project is updated from correct basline

Yes

Comments:

Project contains necessary subprojects

Yes

Comments:

Project contains the correct version of subprojects

Yes

Comments:

Design subproject is correct version

Yes

Comments:

General Notes / Comments:

LN: Intended Use: Identify who were the reviewers and if the reviewed changes have been approved. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. KMC: Group Review Level removed in Rev 4.0 since the design review is not checked in until approved, so it would always be DR4. Review Board:

Change Owner:

Avinash James

Review Date :

12/16/16

Lead Peer Reviewer:

Jayakrishnan T

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 3: Source Code

Rev 7.1

8-Jun-15

Peer Review Meeting Log (Source Code Review)

Source File Name:

kzshz2: Intended Use: Identify which .asm, .c, or .h file is being reviewed Rationale: Required for traceability. It will help to ensure this sheet is not attached to the wrong design review form. CDD_TSG31CfgAndUse.c

Source File Revision:

kzshz2: Intended Use: Identify which version of the source file is being review. Rationale: Required for traceability between source code and review. Auditors will likely require this. 4

Module Design Document Name:

kzshz2: Intended Use: Identify which version of the MDD this source file was written against. Rationale: Needed for traceability between source code and MDD TSG31CfgAndUse_MDD

MDD Revision:

kzshz2: Intended Use: Identify which version of the MDD this source file was written against. Rationale: Needed for traceability between source code and MDD 2

FDD/SCIR/DSR/FDR/CMS Revision:

nz63rn: Intended Use: Identify which version of which FDD/CMS/SER this source file was written against. Rationale: Needed for traceability between source code and FDD/CMS/SER CM475A_TSG31CfgAndUse_Design_1.7.0

nz63rn: Intended Use: Identify which version of which FDD/CMS/SER this source file was written against. Rationale: Needed for traceability between source code and FDD/CMS/SER

Quality Check Items:

Rationale is required for all answers of No

Working EA4 Software Naming Convention followed:

for variable names

N/A

Comments:

N/A for this change

for constant names

N/A

Comments:

N/A for this change

for function names

N/A

Comments:

N/A for this change

for other names (component, memory

Yes

Comments:

mapping handles, typedefs, etc.)

All paths assign a value to outputs, ensuring

N/A

Comments:

all outputs are initialized prior to being written

N/A for this change

All source code changes have Requirements Tracability

N/A

Comments:

tags in the component

N/A for this change

No Variables are declared at the Module level.

N/A

Comments:

N/A for this change

Synergy version matches change history

kzshz2: Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). Rationale: There have been many occassions where versions were not updated in files and as a result Unit Test were referencing wrong versions. This often time leads to the need to re-run of batch tests.

Yes

Comments:

and Version Control version in file comment block

Change log contains detailed description of changes

Yes

Comments:

and Work CR number

Code accurately implements FDD (Document or Model)

Yes

Comments:

No Compiler Errors or Warnings verified

KMC: Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). Rationale: This is needed to ensure there will be no errors discovered at the time of integration. A Sandox project should be used; QAC can find compiler errors but not warnings.

Yes

Comments:

Is component.h included

N/A

Comments:

N/A for this change

Are all includes actually needed? System includes

Yes

Comments:

only allowed in Nexteer library components

Software Design and Coding Standards followed:

Version: 2.1

Code comments are clear, correct, and adequate

N/A

Comments:

and have been updated for the change: [N40] and

N/A for this change

all other rules in the same section as rule [N40],

plus [N75], [N12], [N23], [N33], [N37], [N38],

[N48], [N54], [N77], [N79], [N72]

Source file (.c and .h) comment blocks are per

Yes

Comments:

standards and contain correct information: [N41], [N42]

Function comment blocks are per standards and

N/A

Comments:

contain correct information: [N43]

N/A for this change

Code formatting (indentation, placement of

N/A

Comments:

braces, etc.) is per standards: [N5], [N55], [N56],

N/A for this change

[N57], [N58], [N59]

Embedded constants used per standards; no

Yes

Comments:

"magic numbers": [N12]

Memory mapping for non-RTE code, function parameters

N/A

Comments:

N/A for this change

All execution-order-dependent code can be

N/A

Comments:

recognized by the compiler: [N80]

N/A for this change

No possibility of a non-terminating loop: [N63]

N/A

Comments:

N/A for this change

No possibility of divide by zero: [N65]

N/A

Comments:

N/A for this change

All integer division and modulus operations

N/A

Comments:

handle negative numbers correctly: [N76]

N/A for this change

All typecasting and fixed point arithmetic,

N/A

Comments:

including all use of fixed point macros and

N/A for this change

timer functions, is correct and has no possibility

of unintended overflow or underflow: [N66]

No possibility of converting a negative floating

N/A

Comments:

point value to an unsigned type: [N67]

N/A for this change

All conversions between signed and unsigned

N/A

Comments:

types handle msb==1 as intended: [N78]

N/A for this change

No possibility of dereferencing a null

N/A

Comments:

pointer: [N70]

N/A for this change

Module outputs are limited to the legal range

N/A

Comments:

defined in the FDD DataDict.m file : [N53]

N/A for this change

All code is mapped with FDD (all FDD

N/A

Comments:

subfunctions and/or model blocks identified

N/A for this change

with code comments; all code corresponds to

some FDD subfunction and/or model block): [N40]

No violations of other coding standard rules

Yes

Comments:

identified during review

Incorrect items that require FDD changes

Comments:

ie (display variables used incorrectly, limiting on outputs,

No incorrect items

NvM struct types, divide by zero, other?)

General Notes / Comments:

Change Owner:

Avinash James

Review Date :

12/16/16

Lead Peer Reviewer:

Jayakrishnan T

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 4: PolySpace

Rev 7.1

8-Jun-15

Peer Review Meeting Log (QAC/PolySpace Review)

Module Name:

kzshz2: Intended Use: Identify which .c file is being analyzed Rationale: Required for traceability. It will help to ensure this sheet is not attached to the wrong design review form. CDD_TSG31CfgAndUse.c

Source File Revision:

Module

Compliance Guidelines Version:

kzshz2: Intended Use: Identify specific changes in results (new violation present, previous violation corrected, etc.). Changes to the version of the tool or the way the results were gathered should be described here also. This should be filled out prior to the review by the change owner. Rationale: Gives reviewers an what needs to be focused on. Forces the change owner to compare with previous results to catch any differences that may otherwise go unoticed Brief Summary of Changes (In Results or Tool):

Quality Check Items:

Rationale is required for all answers of No

PolySpace version is correct and did not change (List version)

kzshz2: Intended Use: Identify which version of the QAC Subproject was used and if any of the personalities may have changed. Rationale: Will help ensure this is factored into evaluating the results

Yes

Comments:

Not yet in Synergy

QAC version is correct and did not change (List version)

kzshz2: Intended Use: Identify which version of the QAC Subproject was used and if any of the personalities may have changed. Rationale: Will help ensure this is factored into evaluating the results

Yes

Comments:

TL100A_QACSuprt_1.1.0

Contract Folder's header files are appropriate

kzshz2: Intended Use: Identify that the contract folder contains only the information required for this component. All other variables, constants, function prototypes, etc. should be removed. Rationale: This will help avoid unit testers having to considers object not used. It will also avoid having other files required for QAC.

Yes

Comments:

function prototypes match the latest component version

100% Compliance to the MISRA Compliance Guidelines

Yes

Comments:

Are previously added suppression comments still

Creager, Kathleen: use Browse Function Metrics, STCYC and STPTH

Yes

Comments:

appropriate

Cyclomatic complexity and Static path count ok per

Creager, Kathleen: use Browse Function Metrics, STCYC and STPTH

Yes

Comments:

Design and Coding Standards rule [N47]

General Notes / Comments:

Change Owner:

Avinash James

Review Date :

12/16/16

Lead Peer Reviewer:

Jayakrishnan T

Approved by Reviewer(s):

Yes

Other Reviewer(s):