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Component Design

Component Design

Component Documentation

Reports

1 - SF001A_Assi_Design_PeerReviewChkList

Nexteer_Template_V1.0

Overview

Peer Review Instructions
Technical Review Checklist
Template Change Log

Sheet 1: Peer Review Instructions

Instructions for Functional Design Package Peer Review




PRE-MEETING


Function OwnerConfirm that requirements are reviewed and approved PRIOR to the FDP peer review

Function OwnerStart with latest version of the template for any "first reviews" - Continue to use existing temmplate for re-reviews

Function OwnerProvide the functional design package (changed documents) to the invited attendees 1-2 working days in advance of review

Function OwnerNotify the assigned peer reviewer and make sure they are prepared to do their function in the meeting

Function OwnerIdentify necessary attendance and invite to meeting

Function OwnerComplete the "Author" column information for sections 1 through 5 prior to the review

Function OwnerComplete the attendance invitation list in section 7

Function OwnerFor Re-reviews only: Complete the column "remarks by author" to identify actions taken to address items found in earlier reviews.



DURING MEETING


Function OwnerPresent document changes to the review team

Peer ReviewerCapture attendance of the review

Peer ReviewerCapture actions and issues in section 6. Identify issue summary, Document type, Reference (Requirement ID, section number, etc), Defect Type and indicate status as "OPEN"



POST MEETING


Function OwnerFollow up on all "open" items. Update "Summary of Resolution" to indicate what was done or decided.

Function OwnerSchedule follow up review OR review open items with peer reviewer and obtain agreement to close

Peer ReviewerClose change request in system and confirm all associated tasks are complete. Upload peer review checklist (this document) with any FDP updates

Sheet 2: Technical Review Checklist

Technical Review Checklist - Template Version 02.02.00







Product NameElectric Power SteeringElectrical Arch.4Review ScopeDefect TypeNumbers




YesClosedFR
Function IDSF001A_Assi

No design is changed, but the imported cal name SysGlbPrmVehSpd is updated to SysGlbPrmVehSpdBilnrSeln.Requirement0




NoRejectedFDD
Long NameAssist

Interface0




NAOpenModel
Version that you started from. NOT the version you hope to release. If this will be v1.0.0, enter NA. Starting Baseline1.4.0EffortDesign0






FMEA
AuthorXingye ZhangReview Effort(Hrs.)
Standards0






*.m File


Corr+Verf effort(Hrs.)
Documentation0






Cal Process


Total Effort (Hrs.)0.00Others0













Total0







Checklist No.Description of CheckAuthor: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. AuthorAuthor: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. ReviewerAuthor: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewerAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status







1Section 1: Data Dictionary














Is Filename of Data Dictionary in correct format?YesYes












Is the FDD.Version property correctly updated?YesYes












Is the Data Dictionary Verification report error free?NoNo
AssiLnrGain cannot match name to list of known Nexteer signals.









Does FDD Long Name, Short Name, and Description match requirements?YesYes












Are all runnables defined?YesYes












Do runnables have the correct time step?YesYes












Do server runnables correctly define arguments?NANA












Are all clients defined?YesYes












Do client definitions match the corresponding server runnable?YesYes












Does name and metadata of every signal match its corresponding interface signal?YesYes












Do output signal ranges match requirements (check DOOR min/max attributes too)?YesYes












Are calibration tables named correctly (e.g. AssiX and AssiY)?YesYes












Are all data types represented by released Data_Management classes?YesYes












Do all calibrations have correct values for all metadata?YesYes












Is NVM defined in the appropriate number of blocks?NANA












Are constants defined with proper scope (local vs global)?YesYes












Are all dependent constants and calibrations included in one file?YesYes












Does FDD.DesignASIL match requirements?YesYes



























2Section 2: ModelAuthor: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. AuthorAuthor: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. ReviewerAuthor: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewerAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status








Is filename of model in correct format?YesYes












Is Top level of model annotated with Requirements Baseline?YesYes












Is the Top level of the model annotated with Tool Dependencies?NoNo












Is Top level of model annotated with Change Log or History?YesYes












Is the 2nd level of model free from subsystems that are not Function-Call Subsystems?YesYes












Is the 2nd level of model free from arithmetic and logic operations?YesYes












Are the Runnable trigger signals named as "call_<Runnable>"?YesYes












Does 2nd level of model have a properly updated annotation with name, description, and intended baseline number?YesYes












Are all data flow layers free of Function-Call Subsystems and Memory Store blocks?YesYes












Does the Model have the confidentiality and copyright information inside all its Subsystems?YesYes












Are all the Memory Store blocks for PIM and Display Variables located on the 2nd level of model?YesYes












Is each diagnostic (NTC) capable of being set to "PASS"?NANA












Does non-zero intialization of PIM occur in the function's Init runnable?NANA












Does design properly include Set Ram Block Status when NVM RAM values change?NANA












Does model include appropriate logic for dealing with missing or corrupted NVM data?NANA












Does model execute without errors/warnings after loading NxtrMBDConfig configuration set?NANA



























3Section 3: Requirements LinkingAuthor: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. AuthorAuthor: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. ReviewerAuthor: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewerAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status








Are all requirements links of the format <FDDNumber>_<ObjectID>?YesYes












Does requirements HTML report reference only the DOORS module of this component for all links in the design?YesYes












Are linked blocks linked to the correct requirements(s)? (watch for problems due to copy/pasted blocks)YesYes












Is the list of unlinked blocks acceptable?YesYes



























4Section 4: Model AdvisorAuthor: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. AuthorAuthor: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. ReviewerAuthor: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewerAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status








Was Model Advisor run with the correct configuration settings?YesYes












Is the Model Advisor rerport free from "Fails".YesYes












Are Model Advisor report "Warnings" acceptable?YesYes



























5Section 5: Delivery PackageAuthor: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. AuthorAuthor: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. ReviewerAuthor: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewerAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status








Does Design folder contain only the model, data dictionary, and (optionally) a simulation setup script?YesYes












Does Doc folder contain a zipped HTML webview model?YesYes












Was webview model created without requirements highlighted?NoYes












Does Reports folder contain only the data dictionary verification report, Model Advisor report, and zipped requirements traceability report?YesYes



























6Section 6: Other Issus/Actions IdentifiedDocumentReferenceSummary of resolutionAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status







6.1














6.2














6.3














6.4














6.5














6.6














6.7














6.8














6.9














6.10














6.11














6.12














6.13














6.14














6.15














6.16














6.17














6.18














6.19














6.20














6.21














6.22














6.23














6.24














6.25














7Section 7: APPROVALS













RoleFirst ReviewDateAttendanceApproval?










Function Owner*Xingye Zhang













Peer Reviewer*Price Lefler












Safety<Name - if invited>












Software<Name - if invited>












ESG / Systems<Name - if invited>












EPDT / CSE<Name - if invited>












Hardware<Name - if invited>












Test<Name - if invited>












RoleSecond Review (if required)DateAttendanceApproval?










Function Owner*<Owner Name>













Peer Reviewer*<Name>












Safety<Name - if invited>












Software<Name - if invited>












ESG / Systems<Name - if invited>












EPDT / CSE<Name - if invited>












Hardware<Name - if invited>












Test<Name - if invited>












RoleThird Review (if required)DateAttendanceApproval?










Function Owner*<Owner Name>













Peer Reviewer*<Name>












Safety<Name - if invited>












Software<Name - if invited>












ESG / Systems<Name - if invited>












EPDT / CSE<Name - if invited>












Hardware<Name - if invited>












Test<Name - if invited>












RoleFourth Review (if required)DateAttendanceApproval?










Function Owner*<Owner Name>













Peer Reviewer*<Name>












Safety<Name - if invited>












Software<Name - if invited>












ESG / Systems<Name - if invited>












EPDT / CSE<Name - if invited>












Hardware<Name - if invited>












Test<Name - if invited>












RoleAdd more if necessaryDateAttendanceApproval?










































P.S.:Yes indicates adherence














No indicates non-adherence, reviewer shall provide suitable comments at the end of this document for each point.














NA indicates not applicable













Sheet 3: Template Change Log

RevChangeAuthor
01.00.05Added lesson learned #3.5MDK
01.00.06Added lesson learned #3.6, 3.7 - Structure and writing of NVM in mfiles and models.MDK
02.00.00Combined ESG and Systems into one, compatible with Data_Management 2.13.0 of CreateDD and VerifyDD.K. Derry
02.01.00Added: Does FDD.DesignASIL match requirements?
Added: Was webview model created without requirements highlighted?
Removed: Redundant row in Data Dictionary section.
Formatting: Column C now consistently center-justified.		K. Derry
02.02.00Added: Are all data types represented by released Data_Management classes?
Removed: Are all runnables defined? Rationale: Automated tools checking.
Removed: Does the Component shortname match data dictionary FDD metadata?
Removed: "Data store name must resolve to Simulink signal object"
Edited: Model Advisor report should now be left unzipped.		K. Derry











































































2 - SF001A_Assi_ModelAdvisor

Model Advisor Report for 'SF001A_Assi'
Model Advisor Report - SF001A_Assi.slx
Simulink version: 8.2Model version: 1.240
System: SF001A_AssiCurrent run: 08-Aug-2016 11:26:07
 Model Advisor configuration: ...NxtrModelAdvisorConfig.mat

Run Summary
PassFailWarningNot RunTotal
   54   0   13   133200


By Task

    Code Generation Efficiency

 Check optimization settings

You should turn on the following optimization(s):

  • Block reduction
  • Remove code from floating-point to integer conversions that wraps out-of-range values
  • Inline invariant signals
  • The Simulation range checking diagnostic is enabled. Because this diagnostic can increase the time it takes to simulate your model, you should consider turning it off, by setting its value to none.
  • Ignore testpoints when generating code
  • Pass reusable subsystem outputs as individual arguments



    •     Frequency Response Estimation

        Managing Data Store Memory Blocks

        Managing Library Links And Variants

        Model Referencing

        Modeling Guidelines for MISRA-C:2004

        Modeling Physical Systems

        Modeling Signals and Parameters using Buses

        Modeling Single-Precision Systems

        Modeling Standards for DO-178C/DO-331

        Modeling Standards for EN 50128

        Modeling Standards for IEC 61508

        Modeling Standards for ISO 26262

     Display model metrics and complexity report

    Display number of elements and name, level, and depth of subsystems for the model or subsystem

    Model metrics information
    Display number of elements for Simulink blocks and Stateflow constructs


    Summary

    Element TypeCount
    Inport53
    Outport20
    SubSystem24


    Simulink

    Block TypeCount
    Inport53
    Constant32
    SubSystem24
    Outport20
    S-Function18
    From8
    Math8
    Product7
    DataTypeConversion7
    Width7
    Goto4
    UnaryMinus4
    ActionPort2
    DataStoreWrite2
    DataStoreMemory2
    TriggerPort1
    Merge1
    Terminator1
    If1
    Sum1
    ∧ Less

    Model complexity information
    Display name, level, and depth of subsystems


    Maximum Subsystem Depth: 5

    Subsystem Depth

    Subsystem NameLevelDepth
    Assi14
    Assi/AssiPer123
    Assi/AssiPer1/CopyRight231
    Assi/AssiPer1/Defeat_Tables32
    Assi/AssiPer1/Defeat_Tables/CopyRight241
    Assi/AssiPer1/FltInj_Sim31
    Assi/AssiPer1/LimStat_f131
    Assi/AssiPer1/LimStat_f3231
    Assi/AssiPer1/Normal_Operation32
    Assi/AssiPer1/Normal_Operation/BilnrIntrpnWithRound_s16_u16MplXs16MplY141
    Assi/AssiPer1/Normal_Operation/BilnrIntrpnWithRound_s16_u16MplXs16MplY241
    Assi/AssiPer1/Normal_Operation/BilnrIntrpnWithRound_u16_u16MplXu16MplY41
    Assi/AssiPer1/Normal_Operation/CopyRight241
    Assi/AssiPer1/Normal_Operation/FixdToFloat_f32_s141
    Assi/AssiPer1/Normal_Operation/FixdToFloat_f32_s1641
    Assi/AssiPer1/Normal_Operation/FixdToFloat_f32_u141
    Assi/AssiPer1/Normal_Operation/FixdToFloat_f32_u1641
    Assi/AssiPer1/Normal_Operation/FloatToFixd_u16_f141
    Assi/AssiPer1/Normal_Operation/FloatToFixd_u16_f241
    Assi/AssiPer1/Normal_Operation/FloatToFixd_u16_f341
    Assi/AssiPer1/Normal_Operation/FloatToFixd_u16_f3241
    Assi/AssiPer1/Normal_Operation/LnrIntrpn_u16_u16VariXu16VariY41
    Assi/CopyRight221
    CopyRight211
    ∧ Less


     Check for root Inports with missing properties

    Identify Inport blocks in the top-level of the model with missing or inherited sample times, data types, or port dimensions

    Warning
    The following Inport blocks have undefined or inherited sample times, data types or port dimensions

    InportLinkConditions
    1SF001A_Assi/In2Missing port dimension
    Missing signal data type
    Missing port sample time
    2SF001A_Assi/In3Missing port dimension
    Missing signal data type
    Missing port sample time
    3SF001A_Assi/In4Missing port dimension
    Missing signal data type
    Missing port sample time
    4SF001A_Assi/In5Missing port dimension
    Missing signal data type
    Missing port sample time
    5SF001A_Assi/In6Missing port dimension
    Missing signal data type
    Missing port sample time
    6SF001A_Assi/In7Missing port dimension
    Missing signal data type
    Missing port sample time
    7SF001A_Assi/In8Missing port dimension
    Missing signal data type
    Missing port sample time
    8SF001A_Assi/In9Missing port dimension
    Missing signal data type
    Missing port sample time
    9SF001A_Assi/In10Missing port dimension
    Missing signal data type
    Missing port sample time


    Recommended Action
    Explicitly define all missing Inport block properties identified in the results
    • Missing port dimension: Model contains Inport blocks with inherited port dimension (-1). Specify port dimension for the listed Inport blocks.
    • Missing signal data type: Model contains Inport blocks with inherited data type. Specify a data type for the listed Inport blocks.
    • Missing port sample time: Model contains Inport blocks with inherited sample time (-1). Specify sample time information for the listed Inport blocks. Note: The sample time of root Inports with bus type must match the sample times specified at the leaf elements of the bus object.

     Check for model objects that do not link to requirements

    Check Simulink blocks and Stateflow objects that do not link to a requirements document

    Warning
    The following blocks do not link to a requirement document:

    ∧ Less
    Recommended Action
    For each object in the list, in the Model Editor, right-click the block, select Requirements, and specify a requirement.



        Modeling Standards for MAAB

            Naming Conventions

     Check port block names

    Identify names of Inport or Outport blocks that use characters that are not correct in C code.

    See Also

    Warning
    The following Inport and Outport block names contain incorrect characters:

    ErrorIncorrect port block
    Name contains incorrect characters.SF001A_Assi/Assi/call_AssiPer1


    Recommended Action
    Rename the Inport or Outport blocks to use correct characters.



            Model Architecture

            Model Configuration Options

            Simulink

     Check for Simulink diagrams using nonstandard display attributes

    Identify nonstandard display attributes in Simulink diagrams.

    See Also

    _________________________________________________________________________________________

    Check format settings
    Identify incorrect model-level format options.

    Warning
    The following format display options are incorrect.

    Display AttributeRecommended ValueActual Value
    Display > Signals & Ports > Wide Nonscalar Linesonoff
    View > Model Browser Options > Model Browseroffon


    Recommended Action
    Set the format options to the recommended value.
    _________________________________________________________________________________________

    Check block colors
    Identify blocks using nonstandard colors.

    Warning
    The following blocks use nonstandard colors:

    ∧ Less
    Recommended Action
    Set the block foreground color to black and the background color to white.
    _________________________________________________________________________________________

    Check canvas colors
    Identify canvases that are not white.

    Passed
    All diagrams use a white canvas.
    _________________________________________________________________________________________

    Check diagram zoom
    Identify diagrams that do not have zoom factor set to 100 %.

    Warning
    The following diagrams do not have zoom factor set to 100 percent:

    Recommended Action
    For each listed diagram, select View > Zoom > Normal View (100%).

     Check font formatting

    Identify inconsistent formatting of text.

    See Also

    Warning
    Font formatting is not consistent.

    The following font characteristics are used in the model/subsystem. Font characteristics are sorted by number of occurrences. The most common characteristics are bold.
    Font NameFont SizeFont Style

    Helvetica
    Arial

    10
    14

    normal



    Recommended Action
    To have consistent font formatting, click Modify All Fonts to apply the font formatting selected in the input parameters above to all objects.

    Input Parameters Selection
    NameValue
    Font NameCommon
    Font SizeCommon
    Font StyleCommon

     Check positioning and configuration of ports

    Identify input and output ports with incorrect positioning and configurations.

    See Also

    _________________________________________________________________________________________

    Check Inport blocks position
    Identify Inport blocks that result in left-flowing signals.

    Passed
    There are no Inport blocks in the model that result in left-flowing signals.
    _________________________________________________________________________________________

    Check Outport block position
    Identify Outport blocks that result in left-flowing signals.

    Passed
    There are no Outport blocks in the model that result in left-flowing signals.
    _________________________________________________________________________________________

    Check port orientation
    Identify port blocks with nondefault orientation.

    Passed
    All ports use the default orientation.
    _________________________________________________________________________________________

    Check for duplicate Inports blocks
    Identify duplicate Inport blocks.

    Passed
    All Inport blocks in the model are used once.

     Check visibility of block port names

    Identify port block names that are not uniformly displayed. The block names must all be displayed or none displayed. Library blocks are an exception to this rule. This check ignores masked and subsystem blocks.

    See Also

    _________________________________________________________________________________________

    Check for incorrect port name display
    Identify ports that are incorrectly displaying names.

    Passed
    Subsystem blocks are correctly displayed.
    _________________________________________________________________________________________

    Check for incorrect subsystem port name display
    Identify subsystems that are incorrectly displaying names.

    Passed
    Subsystem blocks are correctly displayed.

    Input Parameters Selection
    NameValue
    Display all port names (Diagram > Format > Show Block Name).true

     Check the display attributes of block names

    Identify whether to display block names.

    See Also

    _________________________________________________________________________________________

    Check for blocks with hidden names and obvious function
    Identify block names that are displayed but can be hidden due to obvious behavior.

    Passed
    All blocks with obvious behavior have hidden names.
    _________________________________________________________________________________________

    Check for non-descriptive displayed block names
    Identify block names that are displayed but should be hidden due to a lack of a descriptive name.

    Passed
    All displayed names provide descriptive information.
    _________________________________________________________________________________________

    Check for missing block names
    Identify block names that are hidden but should be displayed to show a descriptive name.

    Passed
    All displayed names provide descriptive information.

     Check signal line labels

    Identify blocks that require labeled signals. A subset of source and destination blocks require labeled signals.

    See Also

    _________________________________________________________________________________________

    Check source block labels
    The following source blocks require labeled signals; Inport, From, Data Store Read, Constant, Bus Selector, Demux, Selector. If the signal name is visible on the block, this rule is considered met.

    Warning
    The following signals have no label:

    ∧ Less
    Recommended Action
    Add a new or propagated label to the signal line.
    _________________________________________________________________________________________

    Check destination block labels
    The following destination blocks require labeled signals; Outport, Goto, Data Store Write, Bus Creator, Mux, Subsystem, Chart. If the signal name is visible on the source block, this rule is considered met.

    Warning
    The following signals have no label:

    ∧ Less
    Recommended Action
    Add a new or propagated label to the signal line.

     Check for propagated signal labels

    Identify propagated labels on signal lines.

    See Also

    _________________________________________________________________________________________

    Check subsystem input labels
    Identify subsystem inputs that are labeled and display propagated signals.

    Passed
    All inputs to the subsystem have labels and display propagated signals.
    _________________________________________________________________________________________

    Check subsystem output labels
    Identify outputs from subsystems that are labeled and display signal propagation.

    Passed
    All outputs from the subsystem have labels and display propagated signals.
    _________________________________________________________________________________________

    Signal propagation for nonsubsystem blocks
    Identify the signal propagation status for both transformative and nontransformative blocks.

    Passed
    All outputs from non subsystem blocks correctly use labels and display propagated signals.



            Stateflow

     Check usage of exclusive and default states in state machines

    Identify Stateflow charts and substates that incorrectly use or define exclusive and default states.
    Note: This check does not support charts that use MATLAB as the action language.

    See Also

    _________________________________________________________________________________________

    Check Stateflow charts for exclusive states
    Identify Stateflow charts that have singular exclusive (OR) states.

    Passed
    The Stateflow charts do not have singular exclusive (OR) states.
    _________________________________________________________________________________________

    Check Stateflow charts for undefined default states
    Identify Stateflow charts that do not define default states.

    Passed
    Each Stateflow chart defines a default state.
    _________________________________________________________________________________________

    Check for multiple states assigned as the default state
    At the root level in the Stateflow hierarchy only one state should be assigned as the default.

    Passed
    The root level of the chart has only one default state assigned.
    _________________________________________________________________________________________

    Check for substates with singular OR states
    States configured as OR should always be part of a group of states.

    Passed
    No singular OR states were detected.
    _________________________________________________________________________________________

    Check for substates without default states defined
    At every level in the Stateflow hierarchy a default state should be assigned.

    Passed
    All substates have default states assigned.
    _________________________________________________________________________________________

    Check for substates with multiple default states defined
    At every level in the Stateflow hierarchy only one state should be assigned as the default.

    Passed
    All levels of the chart have only one default state assigned.

     Check transition orientations in flowcharts

    Identify transitions in Stateflow flowcharts that are drawn incorrectly.

    See Also

    _________________________________________________________________________________________

    Check for conditions drawn vertically
    Condition expressions should be drawn on the horizontal segments of flowcharts.

    Passed
    All conditions expressions were drawn horizontally.
    _________________________________________________________________________________________

    Check for action transitions drawn vertically
    Transition actions should be drawn on the vertical segments of flowcharts.

    Passed
    All transitions actions where drawn vertically.
    _________________________________________________________________________________________

    Check for junctions for default transitions
    All Junctions in a flow chart should have a default exit transition.

    Passed
    All Junctions have a default exit transition.
    _________________________________________________________________________________________

    Check for transitions that combine condition and action
    Flowcharts should not combine condition evaluations and action expressions in a single transition.

    Passed
    No combined expressions where found in the chart.



            MATLAB Functions

        Requirements Consistency Checking

        Simulation Accuracy

        Simulation Runtime Accuracy Diagnostics

        Simulink Model File Integrity

        Upgrading to the Current Simulink Version