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Component Implementation

Component Implementation

Component Documentation

1 - HysCmp_DesignReview


Overview

Summary Sheet
Synergy Project


Sheet 1: Summary Sheet
























Rev 1.28-Jun-15

Peer Review Summary Sheet


























Synergy Project Name:


kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. SF012A_HysCmp_Impl
Revision / Baseline:


kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. SF012A_HysCmp_Impl_1.3.0

























Change Owner:


kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Nick Saxton
Work CR ID:


EA4#2334





























kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:















































































































































































kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:






















































Reviewed:
































MDD



Source Code



PolySpace










































Integration Manual



Davinci Files








































































Comments:

Only change was pulling in updated FDD to match implementation



























































































General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include FDD Owner and Integrator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.





















Sheet 2: Synergy Project

Peer Review Meeting Log (Component Synergy Project Review)



















































Quality Check Items:




































Rationale is required for all answers of No










New baseline version name from Summary Sheet follows








Yes
Comments:



naming convention





































Project contains necessary subprojects








Yes
Comments:










































Project contains the correct version of subprojects








Yes
Comments:










































Design subproject is correct version








Yes
Comments:











































General Notes / Comments:



























































LN: Intended Use: Identify who were the reviewers and if the reviewed changes have been approved. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. KMC: Group Review Level removed in Rev 4.0 since the design review is not checked in until approved, so it would always be DR4. Review Board:


























Change Owner:

Nick Saxton


Review Date :

04/04/16
































Lead Peer Reviewer:


Krishna Anne


Approved by Reviewer(s):



Yes































Other Reviewer(s):









































































2 - HysCmp_IntegrationManual

Integration Manual

For

HysCmp

VERSION: 1.0

DATE: 04-Aug-2015

Prepared By:

Spandana Balani,

Nexteer Automotive,

Saginaw, MI, USA

Location: The official version of this document is stored in the Nexteer Configuration Management System.

Revision History

Sl. No.DescriptionAuthorVersionDate
1Initial versionSB1.004-Aug-2015

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

AbbreviationDescription
DFDDesign functional diagram
MDDModule design Document
<ADD more to the table if applicable>

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.TitleVersion
<1><MDD Guidelines>Process 04.02.00
<2><Software Naming Conventions>Process 04.02.00
<3><Coding standards>Process 04.02.00
<4>FDD – SF012A_HysCmp_DesignSee Synergy Subproject version

Dependencies

SWCs

ModuleRequired Feature
None

Global Functions(Non RTE) to be provided to Integration Project

None

Configuration REQUIREMeNTS

Build Time Config

ModulesNotes
None

Configuration Files to be provided by Integration Project

Include NxtrFil.h in Rte_UserTypes.h header file

Da Vinci Parameter Configuration Changes

ParameterNotesSWC
N/A

DaVinci Interrupt Configuration Changes

ISR NameVIM #Priority DependencyNotes
N/A

Manual Configuration Changes

ConstantNotesSWC
N/A

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer DataDict.m file

Required Global Data Outputs

Refer DataDict.m file

Specific Include Path present

No

Runnable Scheduling

This section specifies the required runnable scheduling.

InitScheduling RequirementsTrigger
HysCmpInit1RTE_Init
RunnableScheduling RequirementsTrigger
HysCmpPer1NoneRTE(2ms)

.

Memory Map REQUIREMENTS

Mapping

Memory SectionContentsNotes
None

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

FeatureRAMROM
None

Table 1: ARM Cortex R4 Memory Usage

NvM Blocks

None

Compiler Settings

Preprocessor MACRO

None

Optimization Settings

None

Appendix

None

3 - HysCmp_MDD

Module Design Document

For

HysCmp

Aug 4, 2015

Prepared For:

Software Engineering

Nexteer Automotive,

Saginaw, MI, USA

Prepared By:

Spandana Balani,

Nexteer Automotive,

Saginaw, MI, USA
Change History

DescriptionAuthorVersionDate
Initial VersionSB1.004-Aug-2015


Table of Contents

1 Introduction 5

1.1 Purpose 5

1.2 Scope 5

2 HysCmp & High-Level Description 6

3 Design details of software module 7

3.1 Graphical representation of HysCmp 7

3.2 Data Flow Diagram 8

3.2.1 Component level DFD 8

3.2.2 Function level DFD 8

4 Constant Data Dictionary 9

4.1 Program (fixed) Constants 9

4.1.1 Embedded Constants 9

5 Software Component Implementation 10

5.1 Sub-Module Functions 10

5.1.1 Init: HysCmpInit1 10

5.1.2 Per: HysCmpPer1 10

5.2 Server Runables 10

5.3 Interrupt Functions 10

5.4 Module Internal (Local) Functions 10

5.4.1 Local Function #1 10

5.4.1.1 Design Rationale 10

5.4.1.2 Processing 10

5.4.2 Local Function #1 10

5.4.2.1 Design Rationale 10

5.4.2.2 Processing 11

5.4.3 Local Function #1 11

5.4.3.1 Design Rationale 11

5.4.3.2 Processing 11

5.5 GLOBAL Function/Macro Definitions 11

6 Known Limitations with Design 12

7 UNIT TEST CONSIDERATION 13

Appendix A Abbreviations and Acronyms 14

Appendix B Glossary 15

Appendix C References 16

Introduction

Purpose

Scope

HysCmp & High-Level Description

Refer FDD

Design details of software module

Refer FDD

Graphical representation of HysCmp

Data Flow Diagram

Refer FDD

Component level DFD

Refer FDD

Function level DFD

Refer FDD

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Constant NameResolutionUnitsValue
Refer .m file

Software Component Implementation

Refer FDD

Sub-Module Functions

Init: HysCmpInit1

Refer FDD

Per: HysCmpPer1

Refer FDD

Server Runables

None

Interrupt Functions

None

Module Internal (Local) Functions

Local Function #1

Function NameMoreCmpTypeMinMax
Arguments PassedTqChg_HwNwtMtr_T_f32Float32020
*RiseXPtr_HwNwtMtr_T_f32Float3201
*RiseXFac_HwNwtMtr_T_f32Float3201
Return ValueRiseY_Uls_T_f32Float3201

Design Rationale

None

Processing

Refer ‘MoreCmp’ block in Simulink model

Local Function #1

Function NameLessCmpTypeMinMax
Arguments PassedTqChg_HwNwtMtr_T_f32Float32020
*RiseYPtr_Uls_T_f32Float3201
*RiseXFac_HwNwtMtr_T_f32Float3201
Return ValueRiseY_Uls_T_f32Float3201

Design Rationale

None

Processing

Refer ‘LessCmp’ block in Simulink model

Local Function #1

Function NameCalcAvlCmpTypeMinMax
Arguments PassedHwTqFildVal_HwNwtMtr_T_f32Float32-1010
AssiCmdFildVal_HwNwtMtr_T_f32Float32-352352
Return ValueHysCmpAvl_HwNwtMtr_T_f32Float32-8.88.8

Design Rationale

None

Processing

Refer ‘CalcAvlCmp’ block in Simulink model

GLOBAL Function/Macro Definitions

None

Known Limitations with Design

None

UNIT TEST CONSIDERATION

None

Abbreviations and Acronyms

Abbreviation or AcronymDescription

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

  • ISO 9000

  • ISO/IEC 12207

  • ISO/IEC 15504

  • Automotive SPICE® Process Reference Model (PRM)

  • Automotive SPICE® Process Assessment Model (PAM)

  • ISO/IEC 15288

  • ISO 26262

  • IEEE Standards

  • SWEBOK

  • PMBOK

  • Existing Nexteer Automotive documentation

TermDefinitionSource
MDDModule Design Document
DFDData Flow Diagram

References

Ref. #TitleVersion
1AUTOSAR Specification of Memory Mapping (Link:AUTOSAR_SWS_MemoryMapping.pdf)v1.3.0 R4.0 Rev 2
2MDD GuidelineProcess 04.02.00
3Software Naming Conventions.docProcess 04.02.00
4Software Design and Coding Standards.docProcess 04.02.00
5FDD – SF012A_HysCmp_DesignSee Synergy SubProject version