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Component Design

Component Design

Component Documentation

Reports

1 - SF106A_MotRplCoggCfg_Design_PeerReviewChkList

Nexteer_Template_V1.0

Overview

Peer Review Instructions
Technical Review Checklist
Template Change Log

Sheet 1: Peer Review Instructions

Instructions for Functional Design Package Peer Review




PRE-MEETING


Function OwnerConfirm that requirements are reviewed and approved PRIOR to the FDP peer review

Function OwnerStart with latest version of the template for any "first reviews" - Continue to use existing temmplate for re-reviews

Function OwnerProvide the functional design package (changed documents) to the invited attendees 1-2 working days in advance of review

Function OwnerNotify the assigned peer reviewer and make sure they are prepared to do their function in the meeting

Function OwnerIdentify necessary attendance and invite to meeting

Function OwnerComplete the "Author" column information for sections 1 through 5 prior to the review

Function OwnerComplete the attendance invitation list in section 7

Function OwnerFor Re-reviews only: Complete the column "remarks by author" to identify actions taken to address items found in earlier reviews.



DURING MEETING


Function OwnerPresent document changes to the review team

Peer ReviewerCapture attendance of the review

Peer ReviewerCapture actions and issues in section 6. Identify issue summary, Document type, Reference (Requirement ID, section number, etc), Defect Type and indicate status as "OPEN"



POST MEETING


Function OwnerFollow up on all "open" items. Update "Summary of Resolution" to indicate what was done or decided.

Function OwnerSchedule follow up review OR review open items with peer reviewer and obtain agreement to close

Peer ReviewerClose change request in system and confirm all associated tasks are complete. Upload peer review checklist (this document) with any FDP updates

Sheet 2: Technical Review Checklist

Technical Review Checklist - Template Version 02.02.00







Product NameElectric Power SteeringElectrical Arch.4Review ScopeDefect TypeNumbers




YesClosedFR
Function IDSF106A_MotRplCoggCfg

Added constant SCADMOTVELHILIM_MOTRADPERSEC_F32 and
SCADMOTVELLOLIM_MOTRADPERSEC_F32 and saturation blocks to
to fix the floating point exception.		Requirement0




NoRejectedFDD
Long NameMotor Ripple Cogging Configuration

Interface0




NAOpenModel
Version that you started from. NOT the version you hope to release. If this will be v1.0.0, enter NA. Starting Baseline1.5.0EffortDesign0






FMEA
AuthorFei YuanReview Effort(Hrs.)
Standards0






*.m File


Corr+Verf effort(Hrs.)
Documentation0






Cal Process


Total Effort (Hrs.)0.00Others0













Total0







Checklist No.Description of CheckAuthor: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. AuthorAuthor: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. ReviewerAuthor: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewerAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status







1Section 1: Data Dictionary














Is Filename of Data Dictionary in correct format?














Is the FDD.Version property correctly updated?Yes













Is the Data Dictionary Verification report error free?No


Few Output signals need to be added to the global EA4 signal list.









Does FDD Long Name, Short Name, and Description match requirements?














Are all runnables defined?














Do runnables have the correct time step?














Do server runnables correctly define arguments?














Are all clients defined?














Do client definitions match the corresponding server runnable?














Does name and metadata of every signal match its corresponding interface signal?Yes













Do output signal ranges match requirements (check DOOR min/max attributes too)?














Are calibration tables named correctly (e.g. AssiX and AssiY)?














Are all data types represented by released Data_Management classes?














Do all calibrations have correct values for all metadata?Yes













Is NVM defined in the appropriate number of blocks?














Are constants defined with proper scope (local vs global)?














Are all dependent constants and calibrations included in one file?














Does FDD.DesignASIL match requirements?





























2Section 2: ModelAuthor: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. AuthorAuthor: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. ReviewerAuthor: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewerAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status








Is filename of model in correct format?














Is Top level of model annotated with Requirements Baseline?Yes













Is the Top level of the model annotated with Tool Dependencies?Yes













Is Top level of model annotated with Change Log or History?Yes













Is the 2nd level of model free from subsystems that are not Function-Call Subsystems?














Is the 2nd level of model free from arithmetic and logic operations?














Are the Runnable trigger signals named as "call_<Runnable>"?














Does 2nd level of model have a properly updated annotation with name, description, and intended baseline number?














Are all data flow layers free of Function-Call Subsystems and Memory Store blocks?














Does the Model have the confidentiality and copyright information inside all its Subsystems?














Are all the Memory Store blocks for PIM and Display Variables located on the 2nd level of model?














Is each diagnostic (NTC) capable of being set to "PASS"?














Does non-zero intialization of PIM occur in the function's Init runnable?














Does design properly include Set Ram Block Status when NVM RAM values change?














Does model include appropriate logic for dealing with missing or corrupted NVM data?














Does model execute without errors/warnings after loading NxtrMBDConfig configuration set?





























3Section 3: Requirements LinkingAuthor: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. AuthorAuthor: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. ReviewerAuthor: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewerAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status








Are all requirements links of the format <FDDNumber>_<ObjectID>?Yes













Does requirements HTML report reference only the DOORS module of this component for all links in the design?Yes













Are linked blocks linked to the correct requirements(s)? (watch for problems due to copy/pasted blocks)Yes













Is the list of unlinked blocks acceptable?Yes




























4Section 4: Model AdvisorAuthor: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. AuthorAuthor: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. ReviewerAuthor: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewerAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status








Was Model Advisor run with the correct configuration settings?Yes













Is the Model Advisor rerport free from "Fails".Yes













Are Model Advisor report "Warnings" acceptable?Yes




























5Section 5: Delivery PackageAuthor: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. AuthorAuthor: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. ReviewerAuthor: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewerAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status








Does Design folder contain only the model, data dictionary, and (optionally) a simulation setup script?Yes













Does Doc folder contain a zipped HTML webview model?Yes













Was webview model created without requirements highlighted?Yes













Does Reports folder contain only the data dictionary verification report, Model Advisor report, and zipped requirements traceability report?Yes




























4Section 6: Other Issus/Actions IdentifiedDocumentReferenceSummary of resolutionAuthor: Defect type to be selected. Defect TypeAuthor: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By AuthorAuthor: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status







4.1














4.2














4.3














4.4














4.5














4.6














4.7














4.8














4.9














4.10














4.11














4.12














4.13














4.14














4.15














4.16














4.17














4.18














4.19














4.20














4.21














4.22














4.23














4.24














4.25














5Section 7: APPROVALS













RoleFirst ReviewDateAttendanceApproval?










Function Owner*Prerit Pramod5/13/2016YesYes










Peer Reviewer*Sudeep ShankarYesYes










Safety<Name - if invited>












SoftwareKrishna AnneYesYes










ESG / Systems<Name - if invited>












EPDT / CSE<Name - if invited>












Hardware<Name - if invited>












Test<Name - if invited>












RoleSecond Review (if required)DateAttendanceApproval?










Function Owner*<Owner Name>













Peer Reviewer*<Name>












Safety<Name - if invited>












Software<Name - if invited>












ESG / Systems<Name - if invited>












EPDT / CSE<Name - if invited>












Hardware<Name - if invited>












Test<Name - if invited>












RoleThird Review (if required)DateAttendanceApproval?










Function Owner*<Owner Name>













Peer Reviewer*<Name>












Safety<Name - if invited>












Software<Name - if invited>












ESG / Systems<Name - if invited>












EPDT / CSE<Name - if invited>












Hardware<Name - if invited>












Test<Name - if invited>












RoleFourth Review (if required)DateAttendanceApproval?










Function Owner*<Owner Name>













Peer Reviewer*<Name>












Safety<Name - if invited>












Software<Name - if invited>












ESG / Systems<Name - if invited>












EPDT / CSE<Name - if invited>












Hardware<Name - if invited>












Test<Name - if invited>












RoleAdd more if necessaryDateAttendanceApproval?










































P.S.:Yes indicates adherence














No indicates non-adherence, reviewer shall provide suitable comments at the end of this document for each point.














NA indicates not applicable













Sheet 3: Template Change Log

RevChangeAuthor
01.00.05Added lesson learned #3.5MDK
01.00.06Added lesson learned #3.6, 3.7 - Structure and writing of NVM in mfiles and models.MDK
02.00.00Combined ESG and Systems into one, compatible with Data_Management 2.13.0 of CreateDD and VerifyDD.K. Derry
02.01.00Added: Does FDD.DesignASIL match requirements?
Added: Was webview model created without requirements highlighted?
Removed: Redundant row in Data Dictionary section.
Formatting: Column C now consistently center-justified.		K. Derry
02.02.00Added: Are all data types represented by released Data_Management classes?
Removed: Are all runnables defined? Rationale: Automated tools checking.
Removed: Does the Component shortname match data dictionary FDD metadata?
Removed: "Data store name must resolve to Simulink signal object"
Edited: Model Advisor report should now be left unzipped.		K. Derry











































































2 - SF106A_MotRplCoggCfg_ModelAdvisor

Model Advisor Report for 'SF106A_MotRplCoggCfg'
Model Advisor Report - SF106A_MotRplCoggCfg.slx
Simulink version: 8.2Model version: 1.300
System: SF106A_MotRplCoggCfgCurrent run: 13-May-2016 11:10:12
 Model Advisor configuration: ...NxtrModelAdvisorConfig.mat

Run Summary
PassFailWarningNot RunTotal
   53   0   14   292359


Model Advisor

    By Product

        Simulink

        Simulink Coder

        Embedded Coder

        Simscape

        Simulink Verification and Validation

            Modeling Standards

                DO-178C/DO-331 Checks

                IEC 61508, ISO 26262, and EN 50128 Checks

                MathWorks Automotive Advisory Board Checks

            Requirements Consistency

        Simulink Control Design

    By Task

        Code Generation Efficiency

 Check optimization settings

You should turn on the following optimization(s):

  • Block reduction
  • Remove code from floating-point to integer conversions that wraps out-of-range values
  • Inline invariant signals
  • The Simulation range checking diagnostic is enabled. Because this diagnostic can increase the time it takes to simulate your model, you should consider turning it off, by setting its value to none.
  • Ignore testpoints when generating code
  • Pass reusable subsystem outputs as individual arguments



    •         Frequency Response Estimation

            Managing Data Store Memory Blocks

            Managing Library Links And Variants

            Model Referencing

            Modeling Guidelines for MISRA-C:2004

            Modeling Physical Systems

            Modeling Signals and Parameters using Buses

            Modeling Single-Precision Systems

            Modeling Standards for DO-178C/DO-331

            Modeling Standards for EN 50128

            Modeling Standards for IEC 61508

            Modeling Standards for ISO 26262

     Display model metrics and complexity report

    Display number of elements and name, level, and depth of subsystems for the model or subsystem

    Model metrics information
    Display number of elements for Simulink blocks and Stateflow constructs


    Summary

    Element TypeCount
    Inport162
    Outport167
    SubSystem114


    Simulink

    Block TypeCount
    Outport167
    Inport162
    Constant155
    SubSystem114
    S-Function64
    From35
    Goto27
    DataTypeConversion26
    DataStoreWrite24
    Math24
    Width24
    Sum23
    DataStoreMemory20
    Product17
    UnaryMinus15
    Merge13
    ActionPort13
    DataStoreRead12
    RelationalOperator8
    Terminator6
    If5
    TriggerPort4
    Demux1
    ∧ Less

    Model complexity information
    Display name, level, and depth of subsystems


    Maximum Subsystem Depth: 7

    Subsystem Depth

    Subsystem NameLevelDepth
    CopyRight211
    MotRplCoggCfg16
    MotRplCoggCfg/CopyRight221
    MotRplCoggCfg/GetMotRplCoggPrm21
    MotRplCoggCfg/MotRplCoggCfgInit123
    MotRplCoggCfg/MotRplCoggCfgInit1/CopyRight231
    MotRplCoggCfg/MotRplCoggCfgInit1/Enumerated Constant31
    MotRplCoggCfg/MotRplCoggCfgInit1/Get Error Status31
    MotRplCoggCfg/MotRplCoggCfgInit1/LimStat_s131
    MotRplCoggCfg/MotRplCoggCfgInit1/LimStat_s231
    MotRplCoggCfg/MotRplCoggCfgInit1/LimStat_s331
    MotRplCoggCfg/MotRplCoggCfgInit1/LimStat_s431
    MotRplCoggCfg/MotRplCoggCfgInit1/LimStat_s531
    MotRplCoggCfg/MotRplCoggCfgInit1/LimStat_s631
    MotRplCoggCfg/MotRplCoggCfgInit1/NVM is NOT okay32
    MotRplCoggCfg/MotRplCoggCfgInit1/NVM is NOT okay/CopyRight241
    MotRplCoggCfg/MotRplCoggCfgInit1/NVM is NOT okay/Set Ram Block Status41
    MotRplCoggCfg/MotRplCoggCfgInit1/NVM is okay32
    MotRplCoggCfg/MotRplCoggCfgInit1/NVM is okay/CopyRight241
    MotRplCoggCfg/MotRplCoggCfgPer125
    MotRplCoggCfg/MotRplCoggCfgPer1/CopyRight231
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation34
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/CopyRight241
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation43
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/CopyRight251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/FixdToFloat_f32_u151
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/FixdToFloat_f32_u1651
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/FixdToFloat_f32_u251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/FixdToFloat_f32_u351
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/FixdToFloat_f32_u451
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/FixdToFloat_f32_u551
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/FloatToFixd_u16_f151
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/FloatToFixd_u16_f251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/FloatToFixd_u16_f351
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/FloatToFixd_u16_f3251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/LimStat_f151
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/LimStat_f251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/LimStat_f3251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 1 Response52
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 1 Response/BilnrIntrpnWithRound_u16_u16CmnXu16MplY61
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 1 Response/BilnrIntrpnWithRound_u16_u16CmnXu16MplY161
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 1 Response/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 2 Response52
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 2 Response/BilnrIntrpnWithRound_u16_u16CmnXu16MplY61
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 2 Response/BilnrIntrpnWithRound_u16_u16CmnXu16MplY161
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 2 Response/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 3 Response52
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 3 Response/BilnrIntrpnWithRound_u16_u16CmnXu16MplY61
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 3 Response/BilnrIntrpnWithRound_u16_u16CmnXu16MplY161
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Order 3 Response/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/LimStat_f141
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/LimStat_f241
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/LimStat_f3241
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base42
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/BilnrIntrpnWithRound_s16_u16CmnXs16MplY151
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/BilnrIntrpnWithRound_s16_u16CmnXs16MplY251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/BilnrIntrpnWithRound_s16_u16CmnXs16MplY351
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/BilnrIntrpnWithRound_s16_u16CmnXs16MplY451
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/BilnrIntrpnWithRound_s16_u16CmnXs16MplY551
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/BilnrIntrpnWithRound_s16_u16CmnXs16MplY651
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/CopyRight251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/FixdToFloat_f32_s151
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/FixdToFloat_f32_s1651
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/FixdToFloat_f32_s251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/FixdToFloat_f32_s351
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/FixdToFloat_f32_s451
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/FixdToFloat_f32_s551
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/FloatToFixd_u16_f151
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Torque Ripple Base/FloatToFixd_u16_f3251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order1 Phase43
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order1 Phase/CopyRight251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order1 Phase/If Action Subsystem152
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order1 Phase/If Action Subsystem1/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order1 Phase/If Action Subsystem252
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order1 Phase/If Action Subsystem2/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order1 Phase/If Action Subsystem552
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order1 Phase/If Action Subsystem5/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order2 Phase43
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order2 Phase/CopyRight251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order2 Phase/If Action Subsystem152
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order2 Phase/If Action Subsystem1/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order2 Phase/If Action Subsystem252
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order2 Phase/If Action Subsystem2/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order2 Phase/If Action Subsystem552
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order2 Phase/If Action Subsystem5/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order3 Phase43
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order3 Phase/CopyRight251
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order3 Phase/If Action Subsystem152
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order3 Phase/If Action Subsystem1/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order3 Phase/If Action Subsystem252
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order3 Phase/If Action Subsystem2/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order3 Phase/If Action Subsystem552
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Wrap Order3 Phase/If Action Subsystem5/CopyRight261
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/XY to Magnitude and Phase42
    MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/XY to Magnitude and Phase/CopyRight251
    MotRplCoggCfg/MotRplCoggCfgPer1/MotCurrToMotTqGain Calc33
    MotRplCoggCfg/MotRplCoggCfgPer1/MotCurrToMotTqGain Calc/CopyRight241
    MotRplCoggCfg/MotRplCoggCfgPer1/MotCurrToMotTqGain Calc/LimStat_f3241
    MotRplCoggCfg/MotRplCoggCfgPer1/MotCurrToMotTqGain Calc/Output Directly42
    MotRplCoggCfg/MotRplCoggCfgPer1/MotCurrToMotTqGain Calc/Output Directly/CopyRight251
    MotRplCoggCfg/MotRplCoggCfgPer1/MotCurrToMotTqGain Calc/Set to Default42
    MotRplCoggCfg/MotRplCoggCfgPer1/MotCurrToMotTqGain Calc/Set to Default/CopyRight251
    MotRplCoggCfg/MotRplCoggCfgPer1/Position Delay32
    MotRplCoggCfg/MotRplCoggCfgPer1/Position Delay/CopyRight241
    MotRplCoggCfg/MotRplCoggCfgPer1/Position Delay/LimStat_f3241
    MotRplCoggCfg/SetMotRplCoggPrm22
    MotRplCoggCfg/SetMotRplCoggPrm/CopyRight231
    MotRplCoggCfg/SetMotRplCoggPrm/LimStat_s1031
    MotRplCoggCfg/SetMotRplCoggPrm/LimStat_s1131
    MotRplCoggCfg/SetMotRplCoggPrm/LimStat_s1231
    MotRplCoggCfg/SetMotRplCoggPrm/LimStat_s631
    MotRplCoggCfg/SetMotRplCoggPrm/LimStat_s831
    MotRplCoggCfg/SetMotRplCoggPrm/LimStat_s931
    MotRplCoggCfg/SetMotRplCoggPrm/Set Ram Block Status31
    ∧ Less


     Check for root Inports with missing properties

    Identify Inport blocks in the top-level of the model with missing or inherited sample times, data types, or port dimensions

    Warning
    The following Inport blocks have undefined or inherited sample times, data types or port dimensions

    InportLinkConditions
    1SF106A_MotRplCoggCfg/MotCurrQaxCmdMissing port dimension
    Missing signal data type
    Missing port sample time
    2SF106A_MotRplCoggCfg/MotCurrDaxCmdMissing port dimension
    Missing signal data type
    Missing port sample time
    3SF106A_MotRplCoggCfg/MotTqCmdMrfScadMissing port dimension
    Missing signal data type
    Missing port sample time
    4SF106A_MotRplCoggCfg/MotVelMrfMissing port dimension
    Missing signal data type
    Missing port sample time
    5SF106A_MotRplCoggCfg/MotInduDaxEstimdMissing port dimension
    Missing signal data type
    Missing port sample time
    6SF106A_MotRplCoggCfg/MotInduQaxEstimdMissing port dimension
    Missing signal data type
    Missing port sample time
    7SF106A_MotRplCoggCfg/MotBackEmfConEstimdMissing port dimension
    Missing signal data type
    Missing port sample time
    8SF106A_MotRplCoggCfg/CoggOrder1X_ArgInMissing port dimension
    Missing signal data type
    Missing port sample time
    9SF106A_MotRplCoggCfg/CoggOrder1Y_ArgInMissing port dimension
    Missing signal data type
    Missing port sample time
    10SF106A_MotRplCoggCfg/CoggOrder2X_ArgInMissing port dimension
    Missing signal data type
    Missing port sample time
    11SF106A_MotRplCoggCfg/CoggOrder2Y_ArgInMissing port dimension
    Missing signal data type
    Missing port sample time
    12SF106A_MotRplCoggCfg/CoggOrder3X_ArgInMissing port dimension
    Missing signal data type
    Missing port sample time
    13SF106A_MotRplCoggCfg/CoggOrder3Y_ArgInMissing port dimension
    Missing signal data type
    Missing port sample time
    ∧ Less


    Recommended Action
    Explicitly define all missing Inport block properties identified in the results
    • Missing port dimension: Model contains Inport blocks with inherited port dimension (-1). Specify port dimension for the listed Inport blocks.
    • Missing signal data type: Model contains Inport blocks with inherited data type. Specify a data type for the listed Inport blocks.
    • Missing port sample time: Model contains Inport blocks with inherited sample time (-1). Specify sample time information for the listed Inport blocks. Note: The sample time of root Inports with bus type must match the sample times specified at the leaf elements of the bus object.

     Check for model objects that do not link to requirements

    Check Simulink blocks and Stateflow objects that do not link to a requirements document

    Warning
    The following blocks do not link to a requirement document:

    ∧ Less
    Recommended Action
    For each object in the list, in the Model Editor, right-click the block, select Requirements, and specify a requirement.



            Modeling Standards for MAAB

                Naming Conventions

     Check subsystem names

    Identify subsystem names that use characters that are not correct in C code.

    See Also

    Warning
    The following subsystem names contain incorrect characters:

    ErrorSubsystem block
    Name contains incorrect characters...../MotRplCoggCfgInit1/Get Error Status
    Name contains incorrect characters...../MotRplCoggCfgInit1/NVM is NOT okay
    Name contains incorrect characters...../MotRplCoggCfgInit1/NVM is okay
    Name contains incorrect characters...../Wrap Order1 Phase/If Action Subsystem1
    Name contains incorrect characters...../Wrap Order1 Phase/If Action Subsystem2
    Name contains incorrect characters...../Wrap Order1 Phase/If Action Subsystem5
    Name contains incorrect characters...../Wrap Order2 Phase/If Action Subsystem1
    Name contains incorrect characters...../Wrap Order2 Phase/If Action Subsystem2
    Name contains incorrect characters...../Wrap Order2 Phase/If Action Subsystem5
    Name contains incorrect characters...../Wrap Order3 Phase/If Action Subsystem1
    Name contains incorrect characters...../Wrap Order3 Phase/If Action Subsystem2
    Name contains incorrect characters...../Wrap Order3 Phase/If Action Subsystem5
    Name contains incorrect characters...../MotCurrToMotTqGain Calc/Output Directly
    Name contains incorrect characters...../MotCurrToMotTqGain Calc/Set to Default
    ∧ Less


    Recommended Action
    Rename the subsystem blocks using correct characters.

     Check character usage in block names

    Identify block names that use characters that are not correct in C code.

    See Also

    Warning
    The following block names use characters that are not correct for C code:

    Error typeBlock
    Name contains incorrect characters...../Function-Call Generator


    Recommended Action
    Rename the block using correct characters.



                Model Architecture

     Check for mixing basic blocks and subsystems

    Identify levels in the model that include basic blocks and subsystems. Each level of a model must be designed with blocks of the same level (for example, only subsystems or only basic blocks).

    See Also

    Warning
    The following level(s) in the model include basic blocks and subsystems:

    SystemBlock path
    SF106A_MotRplCoggCfgSF106A_MotRplCoggCfg/CoggOrder1_ArgIn
    SF106A_MotRplCoggCfgSF106A_MotRplCoggCfg/CoggOrder2_ArgIn
    SF106A_MotRplCoggCfgSF106A_MotRplCoggCfg/CoggOrder3_ArgIn
    SF106A_MotRplCoggCfgSF106A_MotRplCoggCfg/CopyRight2
    SF106A_MotRplCoggCfg/MotRplCoggCfg..../MotRplCoggCfg/CopyRight2
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Constant1
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Constant11
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Constant12
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Constant2
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Constant3
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Constant8
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/CopyRight2
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Data Store Write10
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Data Store Write11
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Data Store Write12
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Data Store Write7
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Data Store Write8
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Data Store Write9
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Enumerated Constant
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Get Error Status
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/LimStat_s1
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/LimStat_s2
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/LimStat_s3
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/LimStat_s4
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/LimStat_s5
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/LimStat_s6
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfgInit1/Relational Operator
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfg/MotRplCoggCfgInit1/Sum1
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfg/MotRplCoggCfgInit1/Sum12
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfg/MotRplCoggCfgInit1/Sum2
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfg/MotRplCoggCfgInit1/Sum3
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfg/MotRplCoggCfgInit1/Sum4
    ..../MotRplCoggCfg/MotRplCoggCfgInit1..../MotRplCoggCfg/MotRplCoggCfgInit1/Sum5
    ..../MotRplCoggCfg/MotRplCoggCfgPer1..../MotRplCoggCfgPer1/CopyRight2
    ..../Magnitude and Phase Computation..../Magnitude and Phase Computation/Add1
    ..../Magnitude and Phase Computation..../Magnitude and Phase Computation/Add3
    ..../Magnitude and Phase Computation..../Magnitude and Phase Computation/Add5
    ..../Magnitude and Phase Computation..../CopyRight2
    ..../Magnitude and Phase Computation..../Data Store Write
    ..../Magnitude and Phase Computation..../Data Store Write1
    ..../Magnitude and Phase Computation..../Data Store Write2
    ..../Magnitude and Phase Computation..../LimStat_f1
    ..../Magnitude and Phase Computation..../LimStat_f2
    ..../Magnitude and Phase Computation..../LimStat_f32
    ..../Magnitude and Phase Computation..../Magnitude and Phase Computation/Product1
    ..../Magnitude and Phase Computation..../Magnitude and Phase Computation/Product2
    ..../Magnitude and Phase Computation..../Magnitude and Phase Computation/Product3
    ..../Current Regulator Bandwidth Compensation..../Abslt_f32_f3
    ..../Current Regulator Bandwidth Compensation..../Abslt_f32_f32
    ..../Current Regulator Bandwidth Compensation..../Constant
    ..../Current Regulator Bandwidth Compensation..../Constant1
    ..../Current Regulator Bandwidth Compensation..../Constant2
    ..../Current Regulator Bandwidth Compensation..../Constant3
    ..../Current Regulator Bandwidth Compensation..../Constant4
    ..../Current Regulator Bandwidth Compensation..../Constant5
    ..../Current Regulator Bandwidth Compensation..../Constant6
    ..../Current Regulator Bandwidth Compensation..../Constant7
    ..../Current Regulator Bandwidth Compensation..../CopyRight2
    ..../Current Regulator Bandwidth Compensation..../FixdToFloat_f32_u1
    ..../Current Regulator Bandwidth Compensation..../FixdToFloat_f32_u16
    ..../Current Regulator Bandwidth Compensation..../FixdToFloat_f32_u2
    ..../Current Regulator Bandwidth Compensation..../FixdToFloat_f32_u3
    ..../Current Regulator Bandwidth Compensation..../FixdToFloat_f32_u4
    ..../Current Regulator Bandwidth Compensation..../FixdToFloat_f32_u5
    ..../Current Regulator Bandwidth Compensation..../FloatToFixd_u16_f1
    ..../Current Regulator Bandwidth Compensation..../FloatToFixd_u16_f2
    ..../Current Regulator Bandwidth Compensation..../FloatToFixd_u16_f3
    ..../Current Regulator Bandwidth Compensation..../FloatToFixd_u16_f32
    ..../Current Regulator Bandwidth Compensation..../LimStat_f1
    ..../Current Regulator Bandwidth Compensation..../LimStat_f2
    ..../Current Regulator Bandwidth Compensation..../LimStat_f32
    ..../Current Regulator Bandwidth Compensation..../Product
    ..../Current Regulator Bandwidth Compensation..../Product1
    ..../Current Regulator Bandwidth Compensation..../Product2
    ..../Current Regulator Bandwidth Compensation..../Product3
    ..../Current Regulator Bandwidth Compensation..../Product4
    ..../Current Regulator Bandwidth Compensation..../Product5
    ..../Current Regulator Bandwidth Compensation..../Product6
    ..../Current Regulator Bandwidth Compensation..../Sign_s08_f32
    ..../Wrap Order1 Phase..../Wrap Order1 Phase/Add2
    ..../Wrap Order1 Phase..../Wrap Order1 Phase/Constant1
    ..../Wrap Order1 Phase..../Wrap Order1 Phase/Constant9
    ..../Wrap Order1 Phase..../Wrap Order1 Phase/CopyRight2
    ..../Wrap Order1 Phase..../Wrap Order1 Phase/Data Store Write5
    ..../Wrap Order1 Phase..../Wrap Order1 Phase/Relational Operator
    ..../Wrap Order1 Phase..../Wrap Order1 Phase/Relational Operator1
    ..../Wrap Order2 Phase..../Wrap Order2 Phase/Add2
    ..../Wrap Order2 Phase..../Wrap Order2 Phase/Constant1
    ..../Wrap Order2 Phase..../Wrap Order2 Phase/Constant9
    ..../Wrap Order2 Phase..../Wrap Order2 Phase/CopyRight2
    ..../Wrap Order2 Phase..../Wrap Order2 Phase/Data Store Write5
    ..../Wrap Order2 Phase..../Wrap Order2 Phase/Relational Operator
    ..../Wrap Order2 Phase..../Wrap Order2 Phase/Relational Operator1
    ..../Wrap Order3 Phase..../Wrap Order3 Phase/Add2
    ..../Wrap Order3 Phase..../Wrap Order3 Phase/Constant1
    ..../Wrap Order3 Phase..../Wrap Order3 Phase/Constant9
    ..../Wrap Order3 Phase..../Wrap Order3 Phase/CopyRight2
    ..../Wrap Order3 Phase..../Wrap Order3 Phase/Data Store Write5
    ..../Wrap Order3 Phase..../Wrap Order3 Phase/Relational Operator
    ..../Wrap Order3 Phase..../Wrap Order3 Phase/Relational Operator1
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/Abslt_f32_f32
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/Add
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/Add1
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/Constant1
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/Constant2
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/Constant3
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/Constant4
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/Constant5
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/CopyRight2
    ..../MotCurrToMotTqGain Calc..../Data Store Write5
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/LimStat_f32
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/Product
    ..../MotCurrToMotTqGain Calc..../MotCurrToMotTqGain Calc/Product1
    ..../MotCurrToMotTqGain Calc..../Relational Operator
    ∧ Less


    Recommended Action
    If possible, replace blocks at the identified level of the model hierarchy with basic blocks. Move nonvirtual blocks into the identified subsystem.



                Model Configuration Options

                Simulink

     Check for Simulink diagrams using nonstandard display attributes

    Identify nonstandard display attributes in Simulink diagrams.

    See Also

    _________________________________________________________________________________________

    Check format settings
    Identify incorrect model-level format options.

    Warning
    The following format display options are incorrect.

    Display AttributeRecommended ValueActual Value
    Display > Signals & Ports > Wide Nonscalar Linesonoff
    View > Model Browser Options > Model Browseroffon
    Display > Library Links > Allnonedisabled


    Recommended Action
    Set the format options to the recommended value.
    _________________________________________________________________________________________

    Check block colors
    Identify blocks using nonstandard colors.

    Warning
    The following blocks use nonstandard colors:

    ∧ Less
    Recommended Action
    Set the block foreground color to black and the background color to white.
    _________________________________________________________________________________________

    Check canvas colors
    Identify canvases that are not white.

    Passed
    All diagrams use a white canvas.
    _________________________________________________________________________________________

    Check diagram zoom
    Identify diagrams that do not have zoom factor set to 100 %.

    Warning
    The following diagrams do not have zoom factor set to 100 percent:

    ∧ Less
    Recommended Action
    For each listed diagram, select View > Zoom > Normal View (100%).

     Check font formatting

    Identify inconsistent formatting of text.

    See Also

    Warning
    Font formatting is not consistent.

    The following font characteristics are used in the model/subsystem. Font characteristics are sorted by number of occurrences. The most common characteristics are bold.
    Font NameFont SizeFont Style

    Helvetica
    Arial

    10
    14

    normal



    Recommended Action
    To have consistent font formatting, click Modify All Fonts to apply the font formatting selected in the input parameters above to all objects.

    Input Parameters Selection
    NameValue
    Font NameCommon
    Font SizeCommon
    Font StyleCommon

     Check positioning and configuration of ports

    Identify input and output ports with incorrect positioning and configurations.

    See Also

    _________________________________________________________________________________________

    Check Inport blocks position
    Identify Inport blocks that result in left-flowing signals.

    Passed
    There are no Inport blocks in the model that result in left-flowing signals.
    _________________________________________________________________________________________

    Check Outport block position
    Identify Outport blocks that result in left-flowing signals.

    Passed
    There are no Outport blocks in the model that result in left-flowing signals.
    _________________________________________________________________________________________

    Check port orientation
    Identify port blocks with nondefault orientation.

    Passed
    All ports use the default orientation.
    _________________________________________________________________________________________

    Check for duplicate Inports blocks
    Identify duplicate Inport blocks.

    Passed
    All Inport blocks in the model are used once.

     Check visibility of block port names

    Identify port block names that are not uniformly displayed. The block names must all be displayed or none displayed. Library blocks are an exception to this rule. This check ignores masked and subsystem blocks.

    See Also

    _________________________________________________________________________________________

    Check for incorrect port name display
    Identify ports that are incorrectly displaying names.

    Passed
    Subsystem blocks are correctly displayed.
    _________________________________________________________________________________________

    Check for incorrect subsystem port name display
    Identify subsystems that are incorrectly displaying names.

    Passed
    Subsystem blocks are correctly displayed.

    Input Parameters Selection
    NameValue
    Display all port names (Diagram > Format > Show Block Name).true

     Check the display attributes of block names

    Identify whether to display block names.

    See Also

    _________________________________________________________________________________________

    Check for blocks with hidden names and obvious function
    Identify block names that are displayed but can be hidden due to obvious behavior.

    Warning
    The following block names can be hidden:

    Recommended Action
    Hide the block name by deselecting (Diagram > Format > Show Block Name).
    _________________________________________________________________________________________

    Check for non-descriptive displayed block names
    Identify block names that are displayed but should be hidden due to a lack of a descriptive name.

    Warning
    The following blocks have a name displayed, however, the name is not descriptive:

    ∧ Less
    Recommended Action
    Modify the block name to provide descriptive information, or hide the block name by deselecting (Diagram > Format > Show Block Name).
    _________________________________________________________________________________________

    Check for missing block names
    Identify block names that are hidden but should be displayed to show a descriptive name.

    Warning
    The following blocks have descriptive names, however, the names are hidden:

    ∧ Less
    Recommended Action
    Modify the blocks to show the block name (Diagram > Format > Show Block Name).

     Check signal line labels

    Identify blocks that require labeled signals. A subset of source and destination blocks require labeled signals.

    See Also

    _________________________________________________________________________________________

    Check source block labels
    The following source blocks require labeled signals; Inport, From, Data Store Read, Constant, Bus Selector, Demux, Selector. If the signal name is visible on the block, this rule is considered met.

    Warning
    The following signals have no label:

    ∧ Less
    Recommended Action
    Add a new or propagated label to the signal line.
    _________________________________________________________________________________________

    Check destination block labels
    The following destination blocks require labeled signals; Outport, Goto, Data Store Write, Bus Creator, Mux, Subsystem, Chart. If the signal name is visible on the source block, this rule is considered met.

    Warning
    The following signals have no label:

    ∧ Less
    Recommended Action
    Add a new or propagated label to the signal line.

     Check for propagated signal labels

    Identify propagated labels on signal lines.

    See Also

    _________________________________________________________________________________________

    Check subsystem input labels
    Identify subsystem inputs that are labeled and display propagated signals.

    Passed
    All inputs to the subsystem have labels and display propagated signals.
    _________________________________________________________________________________________

    Check subsystem output labels
    Identify outputs from subsystems that are labeled and display signal propagation.

    Passed
    All outputs from the subsystem have labels and display propagated signals.
    _________________________________________________________________________________________

    Signal propagation for nonsubsystem blocks
    Identify the signal propagation status for both transformative and nontransformative blocks.

    Passed
    All outputs from non subsystem blocks correctly use labels and display propagated signals.



                Stateflow

     Check usage of exclusive and default states in state machines

    Identify Stateflow charts and substates that incorrectly use or define exclusive and default states.
    Note: This check does not support charts that use MATLAB as the action language.

    See Also

    _________________________________________________________________________________________

    Check Stateflow charts for exclusive states
    Identify Stateflow charts that have singular exclusive (OR) states.

    Passed
    The Stateflow charts do not have singular exclusive (OR) states.
    _________________________________________________________________________________________

    Check Stateflow charts for undefined default states
    Identify Stateflow charts that do not define default states.

    Passed
    Each Stateflow chart defines a default state.
    _________________________________________________________________________________________

    Check for multiple states assigned as the default state
    At the root level in the Stateflow hierarchy only one state should be assigned as the default.

    Passed
    The root level of the chart has only one default state assigned.
    _________________________________________________________________________________________

    Check for substates with singular OR states
    States configured as OR should always be part of a group of states.

    Passed
    No singular OR states were detected.
    _________________________________________________________________________________________

    Check for substates without default states defined
    At every level in the Stateflow hierarchy a default state should be assigned.

    Passed
    All substates have default states assigned.
    _________________________________________________________________________________________

    Check for substates with multiple default states defined
    At every level in the Stateflow hierarchy only one state should be assigned as the default.

    Passed
    All levels of the chart have only one default state assigned.

     Check transition orientations in flowcharts

    Identify transitions in Stateflow flowcharts that are drawn incorrectly.

    See Also

    _________________________________________________________________________________________

    Check for conditions drawn vertically
    Condition expressions should be drawn on the horizontal segments of flowcharts.

    Passed
    All conditions expressions were drawn horizontally.
    _________________________________________________________________________________________

    Check for action transitions drawn vertically
    Transition actions should be drawn on the vertical segments of flowcharts.

    Passed
    All transitions actions where drawn vertically.
    _________________________________________________________________________________________

    Check for junctions for default transitions
    All Junctions in a flow chart should have a default exit transition.

    Passed
    All Junctions have a default exit transition.
    _________________________________________________________________________________________

    Check for transitions that combine condition and action
    Flowcharts should not combine condition evaluations and action expressions in a single transition.

    Passed
    No combined expressions where found in the chart.



                MATLAB Functions

            Requirements Consistency Checking

            Simulation Accuracy

            Simulation Runtime Accuracy Diagnostics

     Runtime diagnostics for S-functions

    This model contains the following C-MEX S-functions:

    IDS-FunctionBlock
    1C:\Users\bzhf94\Documents\MATLAB\FDD_Dependencies_v2.39.0\Nexteer_Utilities v4.6.0\EA4_Library\Math\Abslt_f32_f32.mexw64SF106A_MotRplCoggCfg/MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Abslt_f32_f3
      SF106A_MotRplCoggCfg/MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Abslt_f32_f32
      ...
    2C:\Users\bzhf94\Documents\MATLAB\FDD_Dependencies_v2.39.0\Nexteer_Utilities v4.6.0\EA4_Library\Math\Arctan2_f32.mexw64SF106A_MotRplCoggCfg/MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/XY to Magnitude and Phase/Arctan2_f1
      SF106A_MotRplCoggCfg/MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/XY to Magnitude and Phase/Arctan2_f2
      ...
    3C:\Users\bzhf94\Documents\MATLAB\FDD_Dependencies_v2.39.0\Nexteer_Utilities v4.6.0\EA4_Library\Math\Sign_s08_f32.mexw64SF106A_MotRplCoggCfg/MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/Current Regulator Bandwidth Compensation/Sign_s08_f32
      SF106A_MotRplCoggCfg/MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/XY to Magnitude and Phase/Sign_s08_f32
    4C:\Users\bzhf94\Documents\MATLAB\FDD_Dependencies_v2.39.0\Nexteer_Utilities v4.6.0\EA4_Library\Math\Sqrt_f32.mexw64SF106A_MotRplCoggCfg/MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/XY to Magnitude and Phase/Sqrt_f1
      SF106A_MotRplCoggCfg/MotRplCoggCfg/MotRplCoggCfgPer1/Magnitude and Phase Computation/XY to Magnitude and Phase/Sqrt_f2
      ...

    Consider setting Solver data inconsistency [?] to either error or warning (currently set to none) to validate whether S-functions adhere to the ODE solver consistency rules that Simulink applies to its built-in blocks.

    Consider setting ArrayBounds exceeded [?]to either error or warning (currently set to none) to check if S-functions are writing outside array boundaries.

    Note: These runtime diagnostics may slow down simulation considerably. You should set them back to none once you have verified that they do not cause any warnings or errors during simulation.

     Check if Read/Write diagnostics are enabled for Data Store blocks

    Note: These runtime diagnostics may slow down simulation considerably. You should set them back to Disable all once you have verified that they do not cause any warnings or errors during simulation.



            Simulink Model File Integrity

            Upgrading to the Current Simulink Version