1 - SysFricLrng_IntegrationManual

Integration Manual

For

SysFricLrng

VERSION: 1.0

DATE: 30-Mar-2016

Prepared By:

Basavaraja Ganeshappa

Nexteer Automotive,

Saginaw, MI, USA

Location: The official version of this document is stored in the Nexteer Configuration Management System.

Revision History

Sl. NoDescriptionAuthorVersionDate
1Initial versionBasavaraja Ganeshappa1.030-Mar-2016

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

AbbreviationDescription
DFDDesign functional diagram
FDDFunctional Design Document
MDDModule design Document

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.TitleVersion
1MDD GuidelineProcess 4.02.01
2EA4 Software Naming ConventionsProcess 4.02.01
3Software Design and Coding StandardsProcess 4.02.01
4FDD- SF007A_SysFricLrng_DesignSee Synergy sub project version

Dependencies

SWCs

ModuleRequired Feature
None

Global Functions(Non RTE) to be provided to Integration Project

None

Configuration REQUIREMeNTS

Build Time Config

ModulesNotes
None

Configuration Files to be provided by Integration Project

None

Da Vinci Parameter Configuration Changes

ParameterNotesSWC
None

DaVinci Interrupt Configuration Changes

ISR NameVIM #Priority DependencyNotes
None

Manual Configuration Changes

ConstantNotesSWC
None

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer SF007A_SysFricLrng_DataDict.m

Required Global Data Outputs

Refer SF007A_SysFricLrng_DataDict.m

Specific Include Path present

None

Runnable Scheduling

This section specifies the required runnable scheduling.

InitScheduling RequirementsTrigger
StOutpCtrlInit1NoneRTE – Init
RunnableScheduling RequirementsTrigger
StOutpCtrlPer1NoneRTE – 10ms

.

Server RunnableScheduling RequirementsTrigger
ClrFricLrngOperModNoneOn server invocation call
GetFricLrngDataNoneOn server invocation call
GetFricOffsOutpDiNoneOn server invocation call
InitFricLrngTblNoneOn server invocation call
SetFricLrngDataNoneOn server invocation call
SetFricOffsOutpDiNoneOn server invocation call

Memory Map REQUIREMENTS

Mapping

Memory SectionContentsNotes

Usage

FeatureRAMROM
None

Table 1: ARM Cortex R4 Memory Usage

NvM Blocks

  • Refer Data Dict

Compiler Settings

Preprocessor MACRO

FLTINJENA is used for coditionaly injecting fault

Optimization Settings

None

Appendix

<This section is for appendix>

2 - SysFricLrng_MDD

Module Design Document

For

SysFricLrng

Oct 03, 2016

Prepared For:

Software Engineering

Nexteer Automotive,

Saginaw, MI, USA

Prepared By: Krishna Anne

Nexteer Automotive,

Saginaw, MI, USA
Change History

DescriptionAuthorVersionDate
Initial VersionBasavaraja Ganeshappa1.024th Mar 2016
Re base lined by pulling 1.3.1Basavaraja Ganeshappa2.025th Jul 2016
Implementation of SF007A v2.0.0 & v2.1.0Krishna Anne3.03rd Oct 2016

Table of Contents1 Introduction 6

1.1 Purpose 6

1.2 Scope 6

2 SysFricLrng High-Level Description 7

3 Design details of software module 8

3.1 Graphical representation of SysFricLrng 9

3.2 Data Flow Diagram 11

3.2.1 Component level DFD 11

3.2.2 Function level DFD 11

4 Constant Data Dictionary 12

4.1 Program (fixed) Constants 12

4.1.1 Embedded Constants 12

5 Software Component Implementation 13

5.1 Sub-Module Functions 13

5.1.1 Init: SysFricLrngInit1 13

5.1.1.1 Design Rationale 13

5.1.1.2 Module Outputs 13

5.1.2 Per: SysFricLrngPer1 13

5.1.2.1 Design Rationale 13

5.1.2.2 Store Module Inputs to Local copies 13

5.1.2.3 (Processing of function)……… 13

5.1.2.4 Store Local copy of outputs into Module Outputs 13

5.2 Server Runnables 13

5.2.1 Server Runnable Name 13

5.2.1.1 Design Rationale 13

5.2.1.2 (Processing of function)……… 13

5.3 Server Runnables 14

5.3.1 Server Runnable Name 14

5.3.1.1 Design Rationale 14

5.3.1.2 (Processing of function)……… 14

5.3.2 Server Runnable Name 14

5.3.2.1 Design Rationale 14

5.3.2.2 (Processing of function)……… 14

5.3.3 Server Runnable Name 14

5.3.3.1 Design Rationale 14

5.3.3.2 (Processing of function)……… 14

5.3.4 Server Runnable Name 14

5.3.4.1 Design Rationale 14

5.3.4.2 (Processing of function)……… 14

5.3.5 Server Runnable Name 14

5.3.5.1 Design Rationale 15

5.3.5.2 (Processing of function)……… 15

5.4 Interrupt Functions 15

5.4.1 Interrupt Function Name 15

5.4.1.1 Design Rationale 15

5.4.1.2 (Processing of the ISR function)….. 15

5.5 Module Internal (Local) Functions 15

5.5.1 Local Function #1 15

5.5.1.1 Design Rationale 15

5.5.1.2 Processing 15

5.5.2 Local Function #2 16

5.5.2.1 Design Rationale 16

5.5.2.2 Processing 16

5.5.3 Local Function #3 16

5.5.3.1 Design Rationale 16

5.5.3.2 Processing 16

5.5.4 Local Function #4 16

5.5.4.1 Design Rationale 17

5.5.4.2 Processing 17

5.5.5 Local Function #5 17

5.5.5.1 Design Rationale 17

5.5.5.2 Processing 17

5.5.6 Local Function #6 17

5.5.6.1 Design Rationale 18

5.5.6.2 Processing 18

5.5.7 Local Function #7 18

5.5.7.1 Design Rationale 18

5.5.7.2 Processing 18

5.5.8 Local Function #8 18

5.5.8.1 Design Rationale 18

5.5.8.2 Processing 18

5.5.8.3 18

5.5.9 Local Function #9 19

5.5.9.1 Design Rationale 19

5.5.9.2 Processing 19

5.5.10 Local Function #10 19

5.5.10.1 Design Rationale 19

5.5.10.2 Processing 19

5.5.11 Local Function #11 19

5.5.11.1 Design Rationale 20

5.5.11.2 Processing 20

5.5.12 Local Function #12 20

5.5.12.1 Design Rationale 20

5.5.12.2 Processing 20

5.6 GLOBAL Function/Macro Definitions 20

6 Known Limitations with Design 21

7 UNIT TEST CONSIDERATION 22

Appendix A Abbreviations and Acronyms 23

Appendix B Glossary 24

Appendix C References 25

Introduction

Purpose

Scope

SysFricLrng High-Level Description

Refer FDD

Design details of software module

Refer FDD

Graphical representation of SysFricLrng

Data Flow Diagram

Refer FDD

Component level DFD

Refer FDD

Function level DFD

Refer FDD

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Constant NameResolutionUnitsValue
INDEX0_CNT_U081CNT0U
INDEX1_CNT_U081CNT1U
INDEX2_CNT_U081CNT2U
INDEX3_CNT_U081CNT3U
SYSSATNFRICESTIMDMIN_HWNWMTR_F321HwNwMtr0.0F
SYSSATNFRICESTIMDMAX_HWNWMTR_F32 21HwNwMtr20.0F
SYSFRICESTIMDMIN_HWNWMTR_F321HwNwMtr0.0F
SYSFRICESTIMDMAX_HWNWMTR_F321HwNwMtr20.0F
SYSFRICOFFSMIN_HWNWMTR_F321HwNwMtr-5.0F
SYSFRICOFFSMAX_HWNWMTR_F321HwNwMtr5.0F

For rest of the constants, please refer Data Dictionary

Software Component Implementation

The detailed design of the function is provided in the FDD.

Sub-Module Functions

Init: SysFricLrngInit1

Design Rationale

In MDD, filters are initialized inside the for loop using switch case but in code filters are initialized one by one without any conditions.

In model, filters are initialized twice as it is not possible to use a variable for the filter initialization in the model. This is redundancy is not present in the code as variables are used for initializing the filters.

Module Outputs

Refer FDD

Per: SysFricLrngPer1

Design Rationale

Refer FDD

Store Module Inputs to Local copies

Refer FDD

(Processing of function)………

Refer FDD

Store Local copy of outputs into Module Outputs

Refer FDD

Server Runnables

Server Runnable Name

ClrFricLrngOperMod

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnables

Server Runnable Name

GetFricLrngData

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnable Name

GetFricOffsOutpDi

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnable Name

InitFricLrngTbl

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnable Name

SetFricLrngDatal

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Server Runnable Name

SetFricOffsOutpDi

Design Rationale

Refer FDD

(Processing of function)………

On server invocation call

Interrupt Functions

None

Interrupt Function Name

None

Design Rationale

NA

(Processing of the ISR function)…..

NA

Module Internal (Local) Functions

Local Function #1

Function NameFricLearningTypeMinMax
Arguments PassedSelHwAg_HwDeg_T_f32Float32-1440.01440.0
SelColTq_HwNwtMtr_T_f32Float32-1010
VehSpdIdx_Cnt_T_u16Uint1603
HwVelDir_Cnt_T_u08Uint801
LrngEna_Cnt_T_LoglBooleanFALSETRUE
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘FricLearning’ subsystem in FDD.

Following per instance data is updated.

*Rte_Pim_RawAvrg() (Min:0, Max:20)
Rte_Pim_SatnAvrgFric()[VehSpdIdx_Cnt_T_u16] (Min:0, Max:20)

Also writes the outputs SysFricEstimd and SysSatnFricEstimd

Local Function #2

Function NameRunningAndCalibrationModesTypeMinMax
Arguments Passed*FricOffs_HwNwtMtr_T_f32Float32-5.0+5.0
*LrngEna_Cnt_T_LoglBooleanFALSETRUE
Return ValueNoneNANANA

Design Rationale

Processing

Following PIMs are updated; refer to ‘RunningAndCalibrationModes’ subsystem in the FDD. FricOffs_HwNwtMtr_T_f32 is the output of this function

Rte_Pim_FricLrngData()->FricOffs (Min:-5, Max:5)
*Rte_Pim_RawAvrg() (Min:0, Max:20)
Rte_Pim_SatnAvrgFric()[VehSpdIdx_Cnt_T_u16] (Min:0, Max:20)

Also updates the input argument, *FricOffs_HwNwtMtr_T_f32.

Local Function #3

Function NameRawAvrgCalcTypeMinMax
Arguments PassedVehSpdIdx_Cnt_T_u16Uint1605
DeltaIdxOffsDec_Cnt_T_u16Uint16012
DeltaIdxOffsInc_Cnt_T_u16Uint16013
TotalCounter_Cnt_T_u32Uint32065535
LrngEna_Cnt_T_LoglBooleanFALSETRUE
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘Raw Average Calculation’ subsystem in FDD.

Following per instance data is updated.

*Rte_Pim_RawAvrg() (Min:0, Max:20)
Rte_Pim_SatnAvrgFric()[VehSpdIdx_Cnt_T_u16] (Min:0, Max:20)

Local Function #4

Function NamePhiCalcTypeMinMax
Arguments PassedSelHwAg_HwDeg_T_f32Float32-14401440
Gate_Cnt_T_u16Uint16065535
DeltaIdxOffs_Cnt_T_u16Uint16010
SelColTq_HwNwtMtr_T_f32Float32-1010
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘Raw Average Calculation’ subsystem in FDD.

Following per instance data is updated.

Rte_Pim_FricLrngData()->Hys[DeltaIdxOffs_Cnt_T_u16][Gate_Cnt_T_u16 + 1U] (Min:-127, Max:127)
Rte_Pim_FricLrngData()->Hys[DeltaIdxOffs_Cnt_T_u16][Gate_Cnt_T_u16] (Min:-127, Max:127)

Local Function #5

Function NameRangeCounterManagerTypeMinMax
Arguments PassedDeltaIdxOffs_Cnt_T_u16Uint16010
DeltaIdxOffsDec_Cnt_T_u16Uint16012
DeltaIdxOffsInc_Cnt_T_u16Uint16013
Gate_Cnt_T_u16Uint16065535
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘Range counter manager’ subsystem in FDD.

Following per instance data is updated.

*Rte_Pim_ RngCntrThdExcdd() (Min:0, Max:1)
Rte_Pim_FricLrngData->RngCntr (:,:) (Min:0, Max:65535)

Local Function #6

Function NameNTCSetResetTypeMinMax
Arguments PassedMaxRawAvrgFric_Cnt_T_f32Float32-127254
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘NTC_Pass’ and ‘NTC_Fail’ subsystem in FDD

Sets or resets the NTCNR_0X0A2

Local Function #7

Function NameClearingModeTypeMinMax
Arguments PassednoneNANANA
Return ValuenoneNANANA

Design Rationale

Processing

Refer to ‘Clearing Mode’ subsystem in FDD.

Following per instance data is updated.

*Rte_Pim_FricOffs()(Min:-5, Max:5)

Local Function #8

Function NameResettingModeTypeMinMax
Arguments Passed*FricOffs_HwNwtMtr_T_f32NANANA
Return ValueNoneNANANA

Design Rationale

Processing

Refer to ‘ResettingMode’ subsystem in FDD.

Following per instance data is updated. Also updates the input argument ‘*FricOffs_HwNwtMtr_T_f32’.

Rte_Pim_FricLrngData()->RngCntr(;)
Rte_Pim_AvrgFricLpFilX()->FilSt (X: 1 to 4)
Rte_Pim_FricLrngData()->Hys(;)
Rte_Pim_FricOffs()(Min:-5, Max:5)

Rte_Pim_VehBasLineFric()[] (Min:-0, Max:127)

Rte_Pim_RawAvrgFric()[] (Min:--127, Max:254)

Rte_Pim_FilAvrgFric()[] (Min:--10 , Max: 10)

Rte_Pim_SatnAvrgFric()[](Min:--127, Max:254)

Rte_Pim_FricLrngData()->VehLrndFric[] (0-127)

Local Function #9

Function NameHwAngConstraintTypeMinMax
Arguments PassedFilHwAg_HwDeg_T_f32Float32-14401440
*HwAgOK_Cnt_T_Loglboolean01
*SelHwAg_HwDeg_T_f32Float32-14401440
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘HwAngConstraint‘ subsystem in FDD. Updates the input arguments, *HwAgOK_Cnt_T_Logl and *SelHwAg_HwDeg_T_f32

Local Function #10

Function NameHwVelConstraintTypeMinMax
Arguments PassedHwVel_HwRadPerSec_T_f32Float32-4242
HwVelOK_Cnt_T_LoglBoolean01
HwVelDir_Cnt_T_u08Uint801
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘HwVelConstraint’ subsystem in FDD.

Local Function #11

Function NameVehSpdConstraintTypeMinMax
Arguments PassedVehSpd_Kph_T_f32Float320511
*VehSpdOK_Cnt_T_LoglBoolean01
*VehSpdIdx_Cnt_T_u16Uint1605
Return ValueNoneNANANA

Design Rationale

Code is optimized due to limitation with the model; hence code completely won’t match the model. There won’t be any impact on the functionality.

In the model as it is not possible to break the for loop until the loop iterator reaches the configured constant threshold value, index corresponding to the position in ‘SysFricLrngVehSpd’ which breaches the conditions mentioned in ‘VehSpdIdxCalcn’ subsystem is calculated by successively adding the index value after multiplying it with either the condition true or false based on whether the vehicle speed value breaches the threshold mentioned in the FDD. In code as it is possible to exit the for loop as soon as a value in ‘VehSpdIdxCalcn’ breaches thresholds as mentioned in FDD, no such successive addition of loop counter is required.

Processing

Refer to ‘VehSpdConstraint’ subsystem in FDD.

Local Function #12

Function NameColTqconstraintTypeMinMax
Arguments PassedFilColTq_HwNwtMtr_T_f32Float32-1010
*SelColTq_HwNwtMtr_T_f32Boolean-1010
Return ValueNANANANA

Design Rationale

Processing

Refer to ‘ColTqconstraint’ subsystem in FDD. Updates the *SelColTq_HwNwtMtr_T_f32.

GLOBAL Function/Macro Definitions

NA

Known Limitations with Design

None

UNIT TEST CONSIDERATION

In model, one based indexing is used but in code 0 based indexing is used.

Abbreviations and Acronyms

Abbreviation or AcronymDescription

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

  • ISO 9000

  • ISO/IEC 12207

  • ISO/IEC 15504

  • Automotive SPICE® Process Reference Model (PRM)

  • Automotive SPICE® Process Assessment Model (PAM)

  • ISO/IEC 15288

  • ISO 26262

  • IEEE Standards

  • SWEBOK

  • PMBOK

  • Existing Nexteer Automotive documentation

TermDefinitionSource
MDDModule Design Document
DFDData Flow Diagram

References

Ref. #TitleVersion
1AUTOSAR Specification of Memory Mapping (Link:AUTOSAR_SWS_MemoryMapping.pdf)Process 4.02.01
2MDD GuidelineProcess 4.02.01
3Software Naming Conventions.doc2.0
4Software Design and Coding Standards.doc2.1
5FDD- SF007A_SysFricLrng_DesignSee Synergy sub project version

3 - SysFricLrng_PeerReviewChecklists


Overview

Summary Sheet
Synergy Project
Source Code
PolySpace


Sheet 1: Summary Sheet
























Rev 1.28-Jun-15

Peer Review Summary Sheet


























Synergy Project Name:


kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. SF007A_SysFricLrng_Impl
Revision / Baseline:


kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. SF007A_SysFricLrng_Impl_2.1.0

























Change Owner:


kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Krishna Anne
Work CR ID:


EA44#7896





























kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:















































































































































































kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:






















































Reviewed:































N/AMDD


YesSource Code


YesPolySpace









































N/AIntegration Manual


N/ADavinci Files








































































Comments:

Reviewed changes alone



























































































General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include FDD Owner and Integrator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.





















Sheet 2: Synergy Project

Peer Review Meeting Log (Component Synergy Project Review)



















































Quality Check Items:




































Rationale is required for all answers of No










New baseline version name from Summary Sheet follows








Yes
Comments:



naming convention





































Project contains necessary subprojects








Yes
Comments:










































Project contains the correct version of subprojects








Yes
Comments:










































Design subproject is correct version








Yes
Comments:











































General Notes / Comments:























Mentioned the comment as mentioned in Cr


































LN: Intended Use: Identify who were the reviewers and if the reviewed changes have been approved. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. KMC: Group Review Level removed in Rev 4.0 since the design review is not checked in until approved, so it would always be DR4. Review Board:


























Change Owner:

Krishna Anne


Review Date :

10/03/16
































Lead Peer Reviewer:


Nick Saxton


Approved by Reviewer(s):



Yes































Other Reviewer(s):










































































Sheet 3: Source Code






















Rev 1.28-Jun-15
Peer Review Meeting Log (Source Code Review)

























Source File Name:


SysFricLrng.c

Source File Revision:


4
Header File Name:


NA

Header File Revision:


kzshz2: Intended Use: Identify which version of the source file is being review. Rationale: Required for traceability between source code and review. Auditors will likely require this. NA

























MDD Name:

SF007A_MDD.doc

Revision:
2

























FDD/SCIR/DSR/FDR/CM Name:




SF007A_HowDetn_Design

Revision:
2.1.0


























Quality Check Items:



































Rationale is required for all answers of No









Working EA4 Software Naming Convention followed:















































for variable names







N/A
Comments:

















































for constant names







N/A
Comments:

















































for function names







N/A
Comments:

















































for other names (component, memory







N/A
Comments:










mapping handles, typedefs, etc.)




































All paths assign a value to outputs, ensuring








N/A
Comments:









all outputs are initialized prior to being written





































Requirements Tracability tags in code match the requirements tracability in the FDD








N/A
Comments:









requirements tracability in the FDD











NA anymore
























All variables are declared at the function level.








N/A
Comments:
























Synergy version matches change history





kzshz2: Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). Rationale: There have been many occassions where versions were not updated in files and as a result Unit Test were referencing wrong versions. This often time leads to the need to re-run of batch tests.


Yes
Comments:



and Version Control version in file comment block





































Change log contains detailed description of changes








Yes
Comments:



and Work CR number





































Code accurately implements FDD (Document or Model)








Yes
Comments:










































Verified no Compiler Errors or Warnings


KMC: Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). Rationale: This is needed to ensure there will be no errors discovered at the time of integration. A Sandox project should be used; QAC can find compiler errors but not warnings.





Yes
Comments:
















































Component.h is included








N/A
Comments:
























All other includes are actually needed. (System includes








N/A
Comments:









only allowed in Nexteer library components)





































Software Design and Coding Standards followed:











Version 2.1

























Code comments are clear, correct, and adequate







Yes
Comments:










and have been updated for the change: [N40] and













all other rules in the same section as rule [N40],






















plus [N75], [N12], [N23], [N33], [N37], [N38],






















[N48], [N54], [N77], [N79], [N72]














































Source file (.c and .h) comment blocks are per







Yes
Comments:










standards and contain correct information: [N41], [N42]





































Function comment blocks are per standards and







N/A
Comments:










contain correct information: [N43]





































Code formatting (indentation, placement of







N/A
Comments:










braces, etc.) is per standards: [N5], [N55], [N56],













[N57], [N58], [N59]














































Embedded constants used per standards; no







N/A
Comments:










"magic numbers": [N12]





































Memory mapping for non-RTE code







N/A
Comments:










is per standard





































All execution-order-dependent code can be







Yes
Comments:










recognized by the compiler: [N80]





































All loops have termination conditions that ensure







N/A
Comments:










finite loop iterations: [N63]





































All divides protect against divide by zero







N/A
Comments:










if needed: [N65]





































All integer division and modulus operations







N/A
Comments:










handle negative numbers correctly: [N76]





































All typecasting and fixed point arithmetic,







N/A
Comments:










including all use of fixed point macros and













timer functions, is correct and has no possibility






















of unintended overflow or underflow: [N66]














































All float-to-unsiged conversions ensure the.







N/A
Comments:










float value is non-negative: [N67]





































All conversions between signed and unsigned







N/A
Comments:










types handle msb==1 as intended: [N78]





































All pointer dereferencing protects against







N/A
Comments:










null pointer if needed: [N70]





































Component outputs are limited to the legal range







N/A
Comments:










defined in the FDD DataDict.m file : [N53]





































All code is mapped with FDD (all FDD







Yes
Comments:










subfunctions and/or model blocks identified













with code comments; all code corresponds to






















some FDD subfunction and/or model block): [N40]













































Review did not identify violations of other








Yes
Comments:









coding standard rules





































Anomaly or Design Work CR created








N/A











for any FDD corrections needed































































General Notes / Comments:

















































































LN: Intended Use: Identify who were the reviewers and if the reviewed changes have been approved. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. KMC: Group Review Level removed in Rev 4.0 since the design review is not checked in until approved, so it would always be DR4. Review Board:


























Change Owner:

Krishna Anne


Review Date :

10/06/16
































Lead Peer Reviewer:


Nick Saxton


Approved by Reviewer(s):



Yes































Other Reviewer(s):










































































Sheet 4: PolySpace






















Rev 1.28-Jun-15
Peer Review Meeting Log (QAC/PolySpace Review)


























Source File Name:


SysFricLrng.cSource File Revision:


4

Source File Name:















Source File Revision:





Source File Name:















Source File Revision:






























EA4 Static Analysis Compliance Guideline version:







2







Poly Space version:


Windows User: eg. 2013b 2013b
Polyspace sub project version:




Windows User: eg. TL108a_PolyspaceSuprt_1.0.0 TL108_PolyspaceSuprt_1.0.0

QAC version:


Windows User: eg 8.1.1-R 8.1.1-R
QAC sub project version:




Windows User: eg. TL_100A_1.1.0 TL100A_QACSuprt_1.2.0


























Quality Check Items:




































Rationale is required for all answers of No



































Contract Folder's header files are appropriate and





kzshz2: Intended Use: Identify that the contract folder contains only the information required for this component. All other variables, constants, function prototypes, etc. should be removed. Rationale: This will help avoid unit testers having to considers object not used. It will also avoid having other files required for QAC.


Yes
Comments:




function prototypes match the latest component version







































100% Compliance to the EA4 Static AnalysisYes
Comments:





Compliance Guideline





























Are previously added justification and deviation








Yes
Comments:





comments still appropriate






































Do all MISRA deviation comments use approved








Yes
Comments:





deviation tags






































Cyclomatic complexity and Static path count OK






Creager, Kathleen: use Browse Function Metrics, STCYC and STPTH

Yes
Comments:





for all functions in the component per Design














and Coding Standards rule [N47]

































































































General Notes / Comments:



























































LN: Intended Use: Identify who were the reviewers and if the reviewed changes have been approved. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. KMC: Group Review Level removed in Rev 4.0 since the design review is not checked in until approved, so it would always be DR4. Review Board:


























Change Owner:

Krishna Anne


Review Date :

10/06/16
































Lead Peer Reviewer:


Nick Saxton


Approved by Reviewer(s):



Yes































Other Reviewer(s):