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Component Implementation

1: requirements
2: VehSigCdng_DesignReview
3: VehSigCdng_Integration Manual
4: VehSigCdng_Module Design Document

Component Implementation

Component Documentation

1 - requirements

FDD	ID	Source	Function	Line(s)	Status	Comment
		.SwFileName	.SwFuncName	.SwLines	.SwStatus	.SwComment
SF033A	56	VehSigCdng.c	VehSigCdngPer1	294	I
SF033A	112	VehSigCdng.c	VehSigCdng_VehLatA	464	I
SF033A	98	VehSigCdng.c	VehSigCdng_VehYawRate,VehSigCdng_LatAEstmn	534,565-574	I
SF033A	115	VehSigCdng.c	VehSigCdngPer1	299	I
SF033A	61	VehSigCdng.c	VehSigCdngPer1	291	I
SF033A	62	VehSigCdng.c	VehSigCdng_VehSpd	363	I
SF033A	63	VehSigCdng.c	VehSigCdng_VehLgtA	418	I
SF033A	111	VehSigCdng.c	VehSigCdng_VehLgtA	413	I
SF033A	110	VehSigCdng.c	VehSigCdng_VehSpd	358	I
SF033A	113	VehSigCdng.c	VehSigCdng_VehYawRate	518	I
SF033A	103	VehSigCdng.c	VehSigCdng_VehLatA	461	I
SF033A	82	VehSigCdng.c	VehSigCdngPer1	296	I
SF033A	83	VehSigCdng.c	VehSigCdngPer1	297	I
SF033A	80	VehSigCdng.c	VehSigCdngPer1	293	I
SF033A	81	VehSigCdng.c	VehSigCdngPer1	295	I
SF033A	86	VehSigCdng.c	VehSigCdng_VehLgtA	429	I
SF033A	87	VehSigCdng.c	VehSigCdng_VehLatA	476	I
SF033A	84	VehSigCdng.c	VehSigCdng_VehYawRate	523	I
SF033A	85	VehSigCdng.c	VehSigCdng_VehLatA,VehSigCdng_VehYawRate	472,522	I
SF033A	108	VehSigCdng.c	VehSigCdng_VehLatA	475	I
SF033A	104	VehSigCdng.c	VehSigCdng_VehYawRate	516	I
SF033A	9	VehSigCdng.c	VehSigCdngPer1	256	I
SF033A	68	VehSigCdng.c	VehSigCdng_VehSpd,VehSigCdng_LatAEstmn	378,587	I
SF033A	146	VehSigCdng.c	VehSigCdng_VehSpd	339-352	I
SF033A	97	VehSigCdng.c	VehSigCdng_LatAEstmn	576-588	I
SF033A	120	VehSigCdng.c	VehSigCdngPer1	263	I
SF033A	121	VehSigCdng.c	VehSigCdngPer1	264	I
SF033A	122	VehSigCdng.c	VehSigCdngPer1	265	I
SF033A	74	VehSigCdng.c	VehSigCdngPer1	258	I
SF033A	73	VehSigCdng.c	VehSigCdng_VehLgtA	410	I
SF033A	72	VehSigCdng.c	VehSigCdng_VehSpd	355	I
SF033A	70	VehSigCdng.c	VehSigCdng_VehSpd	369	I
SF033A	91	VehSigCdng.c	VehSigCdng_VehLatA	484	I
SF033A	90	VehSigCdng.c	VehSigCdng_VehLgtA	421	I
SF033A	106	VehSigCdng.c	VehSigCdng_VehSpd	367	I
SF033A	107	VehSigCdng.c	VehSigCdng_VehLgtA	420	I
SF033A	79	VehSigCdng.c	VehSigCdngPer1	262	I
SF033A	78	VehSigCdng.c	VehSigCdngPer1	261	I
SF033A	11	VehSigCdng.c	VehSigCdngPer1	290	I
SF033A	60	VehSigCdng.c	VehSigCdng_VehSpd	364	I
SF033A	39	VehSigCdng.c	VehSigCdngPer1	292	I
SF033A	114	VehSigCdng.c	VehSigCdngPer1	298	I
SF033A	33	VehSigCdng.c	VehSigCdngPer1	255	I
SF033A	30	VehSigCdng.c	VehSigCdng_VehSpd	339-352	I
SF033A	75	VehSigCdng.c	VehSigCdngPer1	260	I
SF033A	34	VehSigCdng.c	VehSigCdngPer1	257	I
SF033A	99	VehSigCdng.c	VehSigCdng_VehYawRate,VehSigCdng_LatAEstmn	526,576-588	I
SF033A	55	VehSigCdng.c	VehSigCdngPer1	259	I
SF033A	109	VehSigCdng.c	VehSigCdng_VehYawRate	525	I
SF033A	64	VehSigCdng.c	VehSigCdng_VehLgtA	417	I
SF033A	65	VehSigCdng.c	VehSigCdng_VehLatA	473	I

2 - VehSigCdng_DesignReview

Overview

Summary Sheet
Synergy Project
Source Code
MDD
PolySpace

Sheet 1: Summary Sheet

Rev 1.2

8-Jun-15

Peer Review Summary Sheet

Synergy Project Name:

kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. SF033A_VehSigCdng_Impl

Revision / Baseline:

kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. 2.2.0

Change Owner:

kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Spandana Balani

Work CR ID:

EA4#7656

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

Yes

MDD

Yes

Source Code

Yes

PolySpace

N/A

Integration Manual

N/A

Davinci Files

Comments:

Only reviewed changes

General Guidelines:
- The reviews shall be performed over the portions of the component that were modified as a result of the Change Request.
- New components should include FDD Owner and Integrator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files)
- Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed.
- To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file.
- .h file should be reviewed with the source file as part of the source file.

Sheet 2: Synergy Project

Peer Review Meeting Log (Component Synergy Project Review)

Quality Check Items:

Rationale is required for all answers of No

New baseline version name from Summary Sheet follows

Yes

Comments:

naming convention

Project contains necessary subprojects

Yes

Comments:

Project contains the correct version of subprojects

Yes

Comments:

Design subproject is correct version

Yes

Comments:

General Notes / Comments:

LN: Intended Use: Identify who were the reviewers and if the reviewed changes have been approved. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. KMC: Group Review Level removed in Rev 4.0 since the design review is not checked in until approved, so it would always be DR4. Review Board:

Change Owner:

Spandana Balani

Review Date :

09/20/16

Lead Peer Reviewer:

Nick Saxton

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 3: Source Code

Rev 1.2

8-Jun-15

Peer Review Meeting Log (Source Code Review)

Source File Name:

VehSigCdng.c

Source File Revision:

Header File Name:

Header File Revision:

kzshz2: Intended Use: Identify which version of the source file is being review. Rationale: Required for traceability between source code and review. Auditors will likely require this.

MDD Name:

VehSigCdng_Module Design Document.docx

Revision:

FDD/SCIR/DSR/FDR/CM Name:

SF033A_VehSigCdng_Design

Revision:

2.2.0

Quality Check Items:

Rationale is required for all answers of No

Working EA4 Software Naming Convention followed:

for variable names

Yes

Comments:

for constant names

N/A

Comments:

for function names

N/A

Comments:

for other names (component, memory

N/A

Comments:

mapping handles, typedefs, etc.)

All paths assign a value to outputs, ensuring

Yes

Comments:

all outputs are initialized prior to being written

Requirements Tracability tags in code match the requirements tracability in the FDD

N/A

Comments:

requirements tracability in the FDD

All variables are declared at the function level.

Yes

Comments:

Synergy version matches change history

kzshz2: Intended Use: Indicate that the the versioning was confirmed by the peer reviewer(s). Rationale: There have been many occassions where versions were not updated in files and as a result Unit Test were referencing wrong versions. This often time leads to the need to re-run of batch tests.

Yes

Comments:

and Version Control version in file comment block

Change log contains detailed description of changes

Yes

Comments:

and Work CR number

Code accurately implements FDD (Document or Model)

Yes

Comments:

Verified no Compiler Errors or Warnings

KMC: Intended Use: To confirm no compiler errors or warnings exist for the code under review (warnings from contract header files may be ignored). Rationale: This is needed to ensure there will be no errors discovered at the time of integration. A Sandox project should be used; QAC can find compiler errors but not warnings.

Yes

Comments:

Component.h is included

N/A

Comments:

All other includes are actually needed. (System includes

Yes

Comments:

only allowed in Nexteer library components)

Software Design and Coding Standards followed:

Version: 2.1

Code comments are clear, correct, and adequate

Yes

Comments:

and have been updated for the change: [N40] and

all other rules in the same section as rule [N40],

plus [N75], [N12], [N23], [N33], [N37], [N38],

[N48], [N54], [N77], [N79], [N72]

Source file (.c and .h) comment blocks are per

Yes

Comments:

standards and contain correct information: [N41], [N42]

Function comment blocks are per standards and

Yes

Comments:

contain correct information: [N43]

Code formatting (indentation, placement of

Yes

Comments:

braces, etc.) is per standards: [N5], [N55], [N56],

[N57], [N58], [N59]

Embedded constants used per standards; no

N/A

Comments:

"magic numbers": [N12]

Memory mapping for non-RTE code

N/A

Comments:

is per standard

No non-RTE code

All execution-order-dependent code can be

N/A

Comments:

recognized by the compiler: [N80]

All loops have termination conditions that ensure

N/A

Comments:

finite loop iterations: [N63]

All divides protect against divide by zero

N/A

Comments:

if needed: [N65]

All integer division and modulus operations

N/A

Comments:

handle negative numbers correctly: [N76]

All typecasting and fixed point arithmetic,

N/A

Comments:

including all use of fixed point macros and

timer functions, is correct and has no possibility

of unintended overflow or underflow: [N66]

All float-to-unsiged conversions ensure the.

N/A

Comments:

float value is non-negative: [N67]

All conversions between signed and unsigned

N/A

Comments:

types handle msb==1 as intended: [N78]

All pointer dereferencing protects against

N/A

Comments:

null pointer if needed: [N70]

Component outputs are limited to the legal range

N/A

Comments:

defined in the FDD DataDict.m file : [N53]

All code is mapped with FDD (all FDD

Yes

Comments:

subfunctions and/or model blocks identified

with code comments; all code corresponds to

some FDD subfunction and/or model block): [N40]

Review did not identify violations of other

Yes

Comments:

coding standard rules

Anomaly or Design Work CR created

N/A

Comments: List Anomaly or CR numbers

for any FDD corrections needed

General Notes / Comments:

Change Owner:

Spandana Balani

Review Date :

09/20/16

Lead Peer Reviewer:

Nick Saxton

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 4: MDD

Rev 1.2

8-Jun-15

Peer Review Meeting Log (MDD Review)

MDD Name:

VehSigCdng_Module Design Document.docx

MDD Revision:

Source File Name:

VehSigCdng.c

Source File Revision:

Source File Name:

Source File Revision:

Source File Name:

Source File Revision:

Quality Check Items:

Rationale is required for all answers of No

Synergy version matches document

Yes

Comments:

Change log contains detailed description of changes

Yes

Comments:

Changes Highlighted (for Unit Tester)

Yes

Comments:

Diagrams have been included per MDD Guideline

N/A

Comments:

and reviewed

All Design Exceptions and Limitations are listed

N/A

Comments:

Design rationale given for all global

N/A

Comments:

data not communicated through RTE ports, per

Design and Coding Standards rules [N9] and [N10].

All implementation details that differ from the FDD are

N/A

Comments:

noted and explained in Design Rationale

All Unit Test Considerations have been described

N/A

Comments:

General Notes / Comments:

Change Owner:

Spandana Balani

Review Date :

09/20/16

Lead Peer Reviewer:

Nick Saxton

Approved by Reviewer(s):

Yes

Other Reviewer(s):

Sheet 5: PolySpace

Rev 1.2

8-Jun-15

Peer Review Meeting Log (QAC/PolySpace Review)

Source File Name:

VehSigCdng.c

Source File Revision:

Source File Name:

Source File Revision:

Source File Name:

Source File Revision:

EA4 Static Analysis Compliance Guideline version:

01.01.00

Poly Space version:

Windows User: eg. 2013b 2013b

Polyspace sub project version:

Windows User: eg. TL108a_PolyspaceSuprt_1.0.0 TL108A_PolyspaceSuprt_1.0.0

QAC version:

Windows User: eg 8.1.1-R 8.1.1-R

QAC sub project version:

Windows User: eg. TL_100A_1.1.0 TL100A_QACSuprt_1.2.0

Quality Check Items:

Rationale is required for all answers of No

Contract Folder's header files are appropriate and

kzshz2: Intended Use: Identify that the contract folder contains only the information required for this component. All other variables, constants, function prototypes, etc. should be removed. Rationale: This will help avoid unit testers having to considers object not used. It will also avoid having other files required for QAC.

Yes

Comments:

function prototypes match the latest component version

100% Compliance to the EA4 Static Analysis

Yes

Comments:

Compliance Guideline

Are previously added justification and deviation

Yes

Comments:

comments still appropriate

Do all MISRA deviation comments use approved

Yes

Comments:

deviation tags

Cyclomatic complexity and Static path count OK

Creager, Kathleen: use Browse Function Metrics, STCYC and STPTH

Yes

Comments:

for all functions in the component per Design

and Coding Standards rule [N47]

General Notes / Comments:

Change Owner:

Spandana Balani

Review Date :

09/20/16

Lead Peer Reviewer:

Nick Saxton

Approved by Reviewer(s):

Yes

Other Reviewer(s):

3 - VehSigCdng_Integration Manual

Integration Manual

For

VehSigCdng

VERSION: 1.0

DATE: 13-July-2015

Prepared By:

Spandana Balani

Location: The official version of this document is stored in the Nexteer Configuration Management System.

Revision History

Sl. No.	Description	Author	Version	Date
1	Initial version	SB	1.0	13-jul-2015

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 file Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

Abbreviation	Description
DFD	Design functional diagram
MDD	Module design Document
	<ADD more to the table if applicable>

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.	Title	Version
<1>	<MDD Guidelines>	Process 4.01.00
<2>	<Software Naming Conventions>	Process 4.01.00
<3>	<Coding standards>	Process 4.01.00
<4>	<FDD SF033A_VehSigCdng_Design >	See Synergy Subproject version

Dependencies

SWCs

Module	Required Feature
None	N/A

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

None

Configuration REQUIREMeNTS

Build Time Config

Constants	Notes
FLTINJENA	Set to STD_ON for Fault injection

Configuration Files to be provided by Integration Project

Include NxtrFil.h in Rte_UserTypes.h header file.

Da Vinci Parameter Configuration Changes

Parameter	Notes	SWC
N/A

DaVinci Interrupt Configuration Changes

ISR Name	VIM #	Priority Dependency	Notes
N/A

Manual Configuration Changes

Constant	Notes	SWC
N/A

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer DataDict.m file

Required Global Data Outputs

Refer DataDict.m file

file Specific Include Path present

Runnable Scheduling

This section specifies the required runnable scheduling.

Init	Scheduling Requirements	Trigger
VehSigCdngInit1	On Init	Rte_Init

Runnable	Scheduling Requirements	Trigger
VehSigCdngPer1	None	RTE(2ms)

Memory Map REQUIREMENTS

Mapping

Memory Section	Contents	Notes
None

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Feature	RAM	ROM
None

Table 1: ARM Cortex R4 Memory Usage

NvM Blocks

None

Compiler Settings

Preprocessor MACRO

None

Optimization Settings

None

Appendix

None

4 - VehSigCdng_Module Design Document

Module Design Document

For

VehSigCdng

Sep 20, 2016

Prepared For:

Software Engineering

Nexteer Automotive,

Saginaw, MI, USA

Prepared By:

Spandana Balani
Change History

Sl. No.	Description	Author	Version	Date
1	Initial Version	SB	1	13-Jul-2015
2	Updated for FDD v2.0.0	NS	2	2-Jun-2016
3	Updated for FDD v2.2.0	SB	3	20-Sep-2016

Table of Contents

1 Introduction 4

1.1 Purpose 4

1.2 Scope 4

2 VehSigCdng High-Level Description 5

3 Design details of software module 6

3.1 Graphical representation of VehSigCdng 6

3.2 Data Flow Diagram 8

3.2.1 Component level DFD 8

3.2.2 Function level DFD 8

4 Constant Data Dictionary 9

4.1 Program (fixed) Constants 9

4.1.1 Embedded Constants 9

5 Software Component Implementation 10

5.1.1 Sub-Module Functions 10

5.1.2 Interrupt Service Routines 10

5.1.3 Server Runnable Functions 10

5.1.4 Module Internal (Local) Functions 10

5.1.5 Transition Functions 11

6 Known Limitations with Design 13

7 UNIT TEST CONSIDERATION 14

Appendix A Abbreviations and Acronyms 15

Appendix B Glossary 16

Appendix C References 17

Introduction

Purpose

Scope

VehSigCdng High-Level Description

Refer to FDD

Design details of software module

Graphical representation of VehSigCdng

Data Flow Diagram

Component level DFD

Refer to FDD

Function level DFD

Refer to FDD

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

See .m file

Software Component Implementation

Sub-Module Functions

Initialization sub-module VehSigCdngInit1()

Periodic sub-module VehSigCdngPer1()

Design Rationale - Fault Injection client call is conditional compiled based on “FLTINJENA” build constant.

Interrupt Service Routines

None

Server Runnable Functions

None

Module Internal (Local) Functions

Local Function #1

Refer to VehSpd block in the model

Function Name	VehSigCdng_VehSpd	Type	Min	Max
Arguments Passed	VehSpdSerlCom_Kph_T_f32	Float32	0	511
	VehSpdVldSerlCom_Cnt_T_lgc	Boolean	FALSE	TRUE
	VehSpdOvrd_Kph_T_f32	Float32	0	511
	VehSpdOvrdVld_Cnt_T_logl	Boolean	FALSE	TRUE
	VehSpd_Kph_T_f32	Float32	0	511
	VehSpdVld_Cnt_T_logl	Boolean	FALSE	TRUE
Return Value	N/A

Notes: VehSpd_Kph_T_f32, VehSpdVld_Cnt_T_logl are the outputs of the function

Local Function #2

Refer to VehLgtA block in the model

Function Name	VehSigCdng_VehLgtA	Type	Min	Max
Arguments Passed	VehLgtASerlCom_MpSecSq_T_f32	Float32	-180	180
	VehLgtAVldSerlCom_Cnt_T_lgc	Boolean	FALSE	TRUE
	VehLgtA_KphpS_T_f32	Float32	-50	50
	VehLgtAVld_Cnt_T_logl	Boolean	FALSE	TRUE
Return Value	(if no value returned, write N/A)

Notes: VehLgtA_KphpS_T_f32, VehLgtAVld_Cnt_T_logl are the outputs of the function

Local Function #3

Refer to VehLatA block in the model

Function Name	VehSigCdng_VehLatA	Type	Min	Max
Arguments Passed	VehLatASerlCom_MpSecSq_T_f32	Float32	-10	10
	VehLatAVldSerlCom_Cnt_T_lgc	Boolean	FALSE	TRUE
	VehLatA_MpSecSq_T_f32	Float32	-10	10
	VehLatAVld_Cnt_T_logl	Boolean	FALSE	TRUE
Return Value	(if no value returned, write N/A)

Notes: VehLatA_MpSecSq_T_f32, VehLatAVld_Cnt_T_logl are the outputs of the function

Local Function #4

Refer to VehYawRate block in the model

Function Name	VehSigCdng_VehYawRate	Type	Min	Max
Arguments Passed	VehYawRateSerlCom_DegpS_T_f32	Float32	-120	120
	VehYawRateVldSerlCom_Cnt_T_lgc	Boolean	FALSE	TRUE
	VehYawRate_DegpS_T_f32	Float32	-120	120
	VehYawRateVld_Cnt_T_logl	Boolean	FALSE	TRUE
Return Value	(if no value returned, write N/A)

Notes: VehYawRate_DegpS_T_f32, VehYawRateVld_Cnt_T_logl are the outputs of the function

Local Function #5

Refer to “Lateral Acceleration Estimation” block in the model

Function Name	VehSigCdng_LatAEstmn	Type	Min	Max
Arguments Passed	VehYawRate_DegpS_T_f32	Float32	-120	120
	VehYawRateVld_Cnt_T_lgc	Boolean	FALSE	TRUE
	VehSpd_Kph_T_f32	Float32	0	511
	VehSpdVld_Cnt_T_logl	Boolean	FALSE	TRUE
	VehLatAEstimd_MtrPerSecSqd_T_f32	Float32	-10	10
	VehLatAEstimdVld_Cnt_T_logl	Boolean	FALSE	TRUE
Return Value	(if no value returned, write N/A)

Notes: VehLatAEstimd_MtrPerSecSqd_T_f32, VehLatAEstimdVld_Cnt_T_logl are the outputs of the function

Transition Functions

None

Known Limitations with Design

None

UNIT TEST CONSIDERATION

Abbreviations and Acronyms

Abbreviation or Acronym	Description

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

ISO 9000
ISO/IEC 12207
ISO/IEC 15504
Automotive SPICE® Process Reference Model (PRM)
Automotive SPICE® Process Assessment Model (PAM)
ISO/IEC 15288
ISO 26262
IEEE Standards
SWEBOK
PMBOK
Existing Nexteer Automotive documentation

Term	Definition	Source
MDD	Module Design Document
DFD	Data Flow Diagram

References

Ref. #	Title	Version
1	AUTOSAR Specification of Memory Mapping (Link:AUTOSAR_SWS_MemoryMapping.pdf)	v1.3.0 R4.0 Rev 2
2	MDD Guideline	EA4 01.00.00
3	Software Naming Conventions.doc	2.0
4	Software Design and Coding Standards.doc	2.1
5	FDD – SF033A_VehSigCdng_Design	See Synergy Sub project version