MotCurrRegVltgLimr_Integration Manual

Integration Manual

For

‘MotCurrRegVltgLimr’

VERSION: 1.0

DATE: 26-May-2015

Prepared By:

Selva Sengottaiyan

Nexteer Automotive,

Saginaw, MI, USA


Revision History

: ARM Cortex R4 Memory Usage

Sl. No.DescriptionAuthorVersionDate
1Initial versionSelva Sengottaiyan1.04-June-2015


Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 Non RTE NvM Blocks 10

7.4 RTE NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

AbbreviationDescription
DFDDesign functional diagram
MDDModule design Document

References

This section lists the title & version of all the documents that are referred for development of this document

Sr. No.TitleVersion
1FDD – SF105A_MotCurrRegVltgLimr_DesignSee Synergy sub project version
2Software Naming ConventionsProcess 4.00.00
3Software Design and Coding StandardsProcess 4.00.00

Dependencies

SWCs

ModuleRequired Feature
None

Global Functions(Non RTE) to be provided to Integration Project

None

Configuration REQUIREMeNTS

Build Time Config

ModulesNotes
None

Configuration Files to be provided by Integration Project

None

Da Vinci Parameter Configuration Changes

ParameterNotesSWC
None

DaVinci Interrupt Configuration Changes

ISR NameVIM #Priority DependencyNotes
None

Manual Configuration Changes

ConstantNotesSWC
None

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer DataDict.m file in the FDD

Required Global Data Outputs

Refer DataDict.m file file in the FDD

Specific Include Path present

Yes

Runnable Scheduling

This section specifies the required runnable scheduling.

InitScheduling RequirementsTrigger
MotCurrRegVltgLimrInit1NoneInit
RunnableScheduling RequirementsTrigger
MotCurrRegVltgLimrPer1Motor Control ISR*2

Memory Map REQUIREMENTS

Mapping

Memory SectionContentsNotes
MotCtrl_START_SEC_CODECode section for Motor Control scheduled functions

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

FeatureRAMROM
<Memmap usuage info>

Non RTE NvM Blocks

Block Name
None

RTE NvM Blocks

Block Name
none

Compiler Settings

Preprocessor MACRO

None.

Optimization Settings

None

Appendix

None

Last modified October 12, 2025: Initial commit (1fadfc4)