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Component Design

1: ES311A_GateDrv0Ctrl_Peer Review Checklist Design
2: Gate Drive Startup Sequence
3: OffStTbl

Component Design

Component Documentation

1 - ES311A_GateDrv0Ctrl_Peer Review Checklist Design

Nexteer_Template_V1.0

Overview

Peer Review Instructions
Technical Review Checklist
Template Change Log

Sheet 1: Peer Review Instructions

Instructions for Functional Design Package Peer Review

PRE-MEETING
	Function Owner	Confirm that requirements are reviewed and approved PRIOR to the FDP peer review
	Function Owner	Start with latest version of the template for any "first reviews" - Continue to use existing temmplate for re-reviews
	Function Owner	Provide the functional design package (changed documents) to the invited attendees 1-2 working days in advance of review
	Function Owner	Notify the assigned peer reviewer and make sure they are prepared to do their function in the meeting
	Function Owner	Identify necessary attendance and invite to meeting
	Function Owner	Complete the "Author" column information for sections 1 through 3 prior to the review
	Function Owner	Complete the attendance invitation list in section 5
	Function Owner	For Re-reviews only: Complete the column "remarks by author" to identify actions taken to address items found in earlier reviews.

DURING MEETING
	Function Owner	Present document changes to the review team
	Peer Reviewer	Capture attendance of the review
	Peer Reviewer	Capture actions and issues in section 4. Identify issue summary, Document type, Reference (Requirement ID, section number, etc), Defect Type and indicate status as "OPEN"

POST MEETING
	Function Owner	Follow up on all "open" items. Update "Summary of Resolution" to indicate what was done or decided.
	Function Owner	Schedule follow up review OR review open items with peer reviewer and obtain agreement to close
	Peer Reviewer	Close change request in system and confirm all associated tasks are complete. Upload peer review checklist (this document) with any FDP updates

Sheet 2: Technical Review Checklist

Technical Review Checklist - Template Version 01.00.09

Product Name

Electric Power Steering

Electrical Arch.

Review Scope

Defect Type

Numbers

Yes

Closed

Function Name

ES311A_GateDrv0Ctrl

Version

1.8.0

Change Control #: EA4#9292

Requirement

Rejected

FDD

Author

Gerald McCann

Interface

Open

Model

Effort

Design

FMEA

Review Effort(Hrs.)

1.50

Standards

*.m File

Corr+Verf effort(Hrs.)

Documentation

Cal Process

Total Effort (Hrs.)

1.50

Others

Total

Checklist No.

Description of Check

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

Section 1: TECHNICAL CHECK

1.1

Confirm that all signal inputs into the FDP (Functional Design Package) are contained within and exactly named as the "Available_Nexteer_Signals.m" states.

Handled by Darryl's tool

Closed

1.2

Confirm any removed signal inputs from the design have been removed from the "Available_Nexteer_Signals.m" file.

Handled by Darryl's tool

Closed

1.3

Confirm all signals and parameters (outputs, calibrations, constants, non-volatile memory) used in the *.m file and the design conform to the AutoSAR naming convention documentation.

VerifyDD returns a couple errors "Name does not match required pattern."

Closed

1.4

Confirm *.m file has been provided to the "Available_Signal_Names" Author.

Handled by Darryl's tool

Closed

1.5

Confirm Electrical Systems interface map is updated to reflect the FDP (signal IO)

Handled by Darryl's tool

Closed

1.6

Confirm that Static Register evaluation has been completed and updated for any register data that is written to.

1.7

Have calibration default values been reviewed for correctness?

No cal changes

Closed

Section 2: Safety CHECK

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

2.1

Confirm that the functional DFMEA is up to date based on the design in the current package.

2.2

Confirm that Safety requirements (ASIL A - D) are referenced in the design documents.

Yes

Section 3: Lessons Learned

Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author

Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer

Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

3.01

Have functions depending upon system state been reviewed for need to be executed at the 2ms rate to avoid system lag issues?

3.02

Have all diagnostics (NTCs) been confirmed to show logic to invoke a diagnostic "PASS" for control of the status byte at the customer level.

Yes

3.03

Has the requirements traceability steps used the RMI steps as defined in the FDD authoring spec to generate the traceability report?

3.04

Has the requirements traceability report been verified to only contain ONLY requirements from the FR.

3.05

Confirm that all PIM that does NOT have an initialization value of zero is initialized in an INIT function.

Yes

3.06

Confirm if NVM is used, the NVM is defined in structures

Yes

3.07

If the function uses NVM, confirm that the m file uses the SetBlockStatus to indicate a write at powerdown

Yes

3.08

Confirm NTCs are not set within an IRQ (not related to the typical periodic OS)

3.09

Confirm NTCs are not set or read in a periodic rate faster than 2 ms (ex. Motor Control Loop)

Yes

3.10

Constants check: Do all constants have the correct scope (local, global) and are they defined in the correct location (this FDD, ES/SF/AR999)?

Yes

3.11

Confirm all calibrations are required (ie they cannot be constants)

Section 4: Issues / Actions Identified

Document

Reference

Summary of resolution

Author: Defect type to be selected. Defect Type

Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author

Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status

4.1

VerifyDD (errors: 15)
DATA CLASS VIOLATION CHECKS
Errors associated with physical signal that are terminated in FDD

*.m File

No change.
Carry over from previous version.

Standards

No functional impact. Limitation of the way physical signals are handled

Rejected

4.2

VerifyDD (errors: 12)
Client: <TriggerName>
Errors associated with Call_Spi_AsyncTransmit, IoHwAb, Spi_ReadIB and Spi_WriteIB

*.m File

No change.
Carry over from previous version.

Design

No functional impact. Limitation of verify DD tool

Rejected

4.3

VerifyDD (errors: 12)
INPUT SIGNALS: <Identity>
Errors associated with physical signal that are terminated in FDD

*.m File

No change.
Carry over from previous version.

Standards

No functional impact. Limitation of the way physical signals are handled

Rejected

4.4

VerifyDD (errors: 20)
OUTPUT SIGNALS: <Identity>
Errors associated with physical signals and matching name to list of known Nexteer signals.

*.m File

No change.
Carry over from previous version.

Standards

No functional impact. Limitation of the way physical signals are handled

Rejected

4.5

VerifyDD (errors: 78)
CONSTANTS:
Errors associated with SpiConf

*.m File

No change.
Carry over from previous version.

Design

No functional impact. Limitation of verify DD tool

Rejected

Change the name of the signal to read GateDrvAllSts

FDD

Signal name changed from GateDrv0StsVal to GateDrvAllSts

Design

No functional impact.

Closed

4.7

Rename subsystem from substem to a decent name

FDD

Changed "subsystem" to "Determine General Gate Drive Fault"

Design

No functional impact.

Closed

4.8

Remove the check for TW in Temperature Diagnostics

FDD

Originally proposed a change to add a check for TW. The original version was determined to be correct. No check for TW needed.

Design

Closed

4.9

Bring the POR check to the top level of the If condition and use the condition if POR == 1, then reset counter, else if status register indicate fault else if physical fault else no fault

FDD

Moved POR check to top level of Operate Fault Monitor State.

Design

Closed

4.10

Move the SetNtcSts to a resonable place to synchronously set the NTC

FDD

Moved NTC call to top level of Operate Fault Monitor State. If POR or FF, SE, EE, OT, TW, then call GateDrv0GenericFlt NTC block.

Design

Closed

4.11

4.12

4.13

4.14

4.15

4.16

4.17

4.18

4.19

4.20

4.21

4.22

4.23

4.24

4.25

Section 5: APPROVALS

Role

First Review

Date

Attendance

Approval?

Function Owner*

Gerald McCann

1/16/2017

Yes

Peer Reviewer*

Samanth Kumaraswamy

Yes

EPDT Engineer

ES Engineer

Software Lead

Rijvi Ahmed

Yes

Hardware Lead

Test Lead

Safety Lead

Role

Second Review (if required)

Date

Attendance

Approval?

Function Owner*

Gerald McCann

1/17/2017

Yes

Peer Reviewer*

Samanth Kumaraswamy

Yes

EPDT Engineer

ES Engineer

Software Lead

Rijvi Ahmed

Yes

Hardware Lead

Test Lead

Safety Lead

Role

Third Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Fourth Review (if required)

Date

Attendance

Approval?

Function Owner*

Peer Reviewer*

<Name>

EPDT Engineer

ES Engineer

Software Lead

Hardware Lead

Test Lead

Safety Lead

Role

Add more if necessary

Date

Attendance

Approval?

P.S.:

Yes indicates adherence

No indicates non-adherence, reviewer shall provide suitable comments at the end of this document for each point.

NA indicates not applicable

Sheet 3: Template Change Log

Rev	Change	Author
01.00.05	Added lesson learned #3.5	MDK
01.00.06	Added lesson learned #3.6, 3.7 - Structure and writing of NVM in mfiles and models.	MDK
01.00.07	Clarified 3.6 and 3.7 Added lessons learned for NTCs not being set in IRQs or periodics faster than 2ms/	MDK
01.00.08	Added section 1.6 to look for critical static register analysis	MDK
01.00.09	Added two checks - default cals and are all cals really required to be a calibration	MDK

2 - Gate Drive Startup Sequence

DBM

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Digital Pin Verification

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DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

CHU

CLU

BHU

BLU

AHU

ALU

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

VSO

VSU

OC3

OC2

OC1

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

CHU

CLU

BHU

BLU

AHU

ALU

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

VSO

VSU

OC3

OC2

OC1

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

CHU

CLU

BHU

BLU

AHU

ALU

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

VSO

VSU

OC3

OC2

OC1

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

CHU

CLU

BHU

BLU

AHU

ALU

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VSO

VSU

OC3

OC2

OC1

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

CHU

CLU

BHU

BLU

AHU

ALU

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

VSO

VSU

OC3

OC2

OC1

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

Tx0

Bootstrap cap under voltage

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

Tx1

POR

CHU

CLU

BHU

BLU

AHU

ALU

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VSO

VSU

OC3

OC2

OC1

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

Tx0

Bootstrap cap under voltage

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

Tx1

POR

CHU

CLU

BHU

BLU

AHU

ALU

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VSO

VSU

OC3

OC2

OC1

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

Tx0

Bootstrap cap under voltage

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

Tx1

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

CHU

CLU

BHU

BLU

AHU

ALU

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VSO

VSU

OC3

OC2

OC1

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

Tx0

Bootstrap cap under voltage

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

Tx1

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

CHU

CLU

BHU

BLU

AHU

ALU

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VSO

VSU

OC3

OC2

OC1

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

Tx0

Bootstrap cap under voltage

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

Tx1

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

CHU

CLU

BHU

BLU

AHU

ALU

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VSO

VSU

OC3

OC2

OC1

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

Tx0

Bootstrap cap under voltage

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

Tx1

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

CHU

CLU

BHU

BLU

AHU

ALU

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VSO

VSU

OC3

OC2

OC1

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

Tx0

Bootstrap cap under voltage

POR

VLO

ETO

LDF

BSU

GSU

DSO

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

Tx1

POR

CHU

CLU

BHU

BLU

AHU

ALU

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

DG1

DG0

ESF

POR

DG1

DG0

ESF

POR

VSO

VSU

OC3

OC2

OC1

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

DG1

DG0

ESF

POR

VLO

ETO

LDF

BSU

GSU

DSO

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

CHU

CLU

BHU

BLU

AHU

ALU

POR

VLO

ETO

LDF

BSU

GSU

DSO

CHU

CLU

BHU

BLU

AHU

ALU

POR

CHU

CLU

BHU

BLU

AHU

ALU

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VSO

VSU

OC3

OC2

OC1

POR

VSO

VSU

OC3

OC2

OC1

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

3 - OffStTbl

Overview

Sheet1
Sheet2

Sheet 1: Sheet1




			Off state Verification Array
			Column 1	Column 2	Column3	4	5	6	7	8
		Case	Tx0	Tx1	MotDrvr0Diag	Status	Diag1	Diag2	VrfyRes0	VrfyRes1
Zeros are essentially don’t cares.		0	GATEDRV0VRFYCMD0WRVAL_CNT_U16 \| 0x0026 20992 + 38	GATEDRV0CTRLVAL_CNT_U16(32320)	0	0	0	0	0	0x0040 (64)	Gate Drive Off Check
		1	GATEDRV0VRFYCMD0WRVAL_CNT_U16 20992	0	0	0	0	0	0	0
		2	GATEDRV0VRFYCMD1WRVAL_CNT_U16 \| 0x0103 22016 + 259	0	0	0x4120	0x0080	0x0030	0	0	VREG UV, VBB OV, VBB UV Check
		3	0	0	0	0	0	0	0	0
		4	0	0	0	0	0	0	0	0
		5	0	0	0	0	0	0	0	0
		6	GATEDRV0VRFYCMD1WRVAL_CNT_U16\| 0x0003	0	0	0	0	0	0	0
Check for PCD, PBD, PAD = 0	y & x = 0	7	GATEDRV0VRFYCMD1WRVAL_CNT_U16\| 0x0083 (131)	0	0	0	0	0	0x0070	0	Phase Disconnect Low Side Check
		8	0	0	0	0	0	0	0	0
		9	0	0	0	0	0	0	0	0
		10	0	0	0	0	0	0	0	0
		11	GATEDRV0VRFYCMD1WRVAL_CNT_U16\| 0x0003	0	0	0	0	0	0	0
Check for PCD, PBD, PAD = 0	y & x = 0	12	GATEDRV0CTRLVAL_CNT_U16 \| 0x002A (42)	0	0	0	0	0	0x0070	0	Phase Disconnect High Side
		13	GATEDRV0VRFYCMD0WRVAL_CNT_U16 \| 0x0010U 20992 \| 0x0010U	0	0	0	0	0	0	0
		14	GATEDRV0VRFYCMD0WRVAL_CNT_U16	0	0	0	0	0	0	0
		15	GATEDRV0CTRLVAL_CNT_U16 \| 0x002A	GATEDRV0VRFYCMD0WRVAL_CNT_U16 \| 0x0080U 20992 \| 0x0080U	0	0x4004	0	0x01C0	0	0	Bootstrap Undervoltage Check
		16	GATEDRV0CTRLVAL_CNT_U16	GATEDRV0VRFYCMD0WRVAL_CNT_U16	0	0	0	0	0	0
		17	GATEDRV0CTRLVAL_CNT_U16 \| 0x0015	GATEDRV0VRFYCMD0WRVAL_CNT_U16 \| 0x0080U 20992 \| 0x0080U	0	0x4001	0x002A	0	0	0	High Side - VDS Overvoltage Fault
		18	GATEDRV0CTRLVAL_CNT_U16	GATEDRV0VRFYCMD0WRVAL_CNT_U16	0	0	0	0	0	0
		19	0	0	1	0x4001	0x0015	0	0	0	Low Side - VDS Overvoltage Faul

Sheet 2: Sheet2

Case

Tx0 and Tx1 Data

6 - Read only Registers

Digital Pin Verification

Tx0

Vreg UV, VBB UV, VBB OV

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

Tx1

DG1

DG0

ESF

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

vrfycmd0wrval

0x0026

POR

VSO

VSU

OC3

OC2

OC1

CtrlWrVal

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

VrfyRes1

0x0040

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

Tx0

Vreg UV, VBB UV, VBB OV

YDO

YRO

YRU

YBU

YLO

YSO

YSU

YGU

POR

VLO

ETO

LDF

BSU

GSU

DSO

Tx1

POR

CHU

CLU

BHU

BLU

AHU

ALU

VrfyCmd0WrVal

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VSO

VSU

OC3

OC2

OC1

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

Phase Disconnect

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

4120

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

VrfyCmd1WrVal

0x0103

259

POR

VSO

VSU

OC3

OC2

OC1

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VSO

VSU

OC3

OC2

OC1

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VSO

VSU

OC3

OC2

OC1

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

POR

VSO

VSU

OC3

OC2

OC1

POR

PCD

PBD

PAD

VBR

LCD

LBD

LAD

POR

GDO

SCS

SBS

SAS

S3D

S2D

S1D

YPH

YPL

YOC

YOL

YOP1

YOP0

Y01

YO2

POR

VLO

ETO

LDF

BSU

GSU

DSO

POR

CHU

CLU

BHU

BLU

AHU

ALU

POR

VRO

VRU

CHO

CLO

BHO

BLO

AHO

ALO

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