Component Implementation

• 1: AdcDiagc_IntegrationManual
• 2: AdcDiagc_MDD
• 3: AdcDiagc_PeerReviewCheckList
• 4: requirements

1 - AdcDiagc_IntegrationManual

Integration Manual

For

AdcDiagc

VERSION: 4.0

DATE: Aug 25, 2016

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA

Location: The official version of this document is stored in the Nexteer Configuration Management System.

Revision History

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

References

This section lists the title & version of all the documents that are referred for development of this document

Dependencies

SWCs

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

Configuration REQUIREMeNTS

Build Time Config

Configuration Files to be provided by Integration Project

No

Da Vinci Parameter Configuration Changes

DaVinci Interrupt Configuration Changes

Manual Configuration Changes

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

Refer DataDict.m file

Required Global Data Outputs

Refer DataDict.m file

Specific Include Path present

None Runnable Scheduling

This section specifies the required runnable scheduling.

Memory Map REQUIREMENTS

Mapping

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Table 1: ARM Cortex R4 Memory Usage

NvM Blocks

*See DataDict.m

Compiler Settings

Preprocessor MACRO

None.

Optimization Settings

None.

Appendix

None.

2 - AdcDiagc_MDD

Module Design Document

For

AdcDiagc

Aug 25, 2016

Prepared For:

Software Engineering

Nexteer Automotive,

Saginaw, MI, USA

Prepared By:

Software Group,

Nexteer Automotive,

Saginaw, MI, USA
Change History

Table of Contents

1 Introduction 5

1.1 Purpose 5

1.2 Scope 5

2 AdcDiagc & High-Level Description 6

3 Design details of software module 7

3.1 Graphical representation of AdcDiagc 7

3.2 Data Flow Diagram 7

3.2.1 Component level DFD 7

3.2.2 Function level DFD 7

4 Constant Data Dictionary 8

4.1 Program (fixed) Constants 8

4.1.1 Embedded Constants 8

5 Software Component Implementation 9

5.1 Sub-Module Functions 9

5.1.1 Init: AdcDiagcInit1 9

5.1.1.1 Design Rationale 9

5.1.1.2 Module Outputs 9

5.1.2 Per: AdcDiagcPer1 9

5.1.2.1 Design Rationale 9

5.1.2.2 Store Module Inputs to Local copies 9

5.1.2.3 (Processing of function)……… 9

5.1.2.4 Store Local copy of outputs into Module Outputs 9

5.2 Server Runables 9

5.2.1 SetAdcParFlt 9

5.2.1.1 Design Rationale 9

5.2.1.2 (Processing of function)……… 9

5.3 Interrupt Functions 10

5.4 Module Internal (Local) Functions 10

5.4.1 Local Function #1 10

5.4.1.1 Design Rationale 10

5.4.1.2 Processing 10

5.4.2 Local Function #2 10

5.4.2.1 Design Rationale 10

5.4.2.2 Processing 10

5.4.3 Local Function #3 10

5.4.3.1 Design Rationale 11

5.4.3.2 Processing 11

5.4.4 Local Function #4 11

5.4.4.1 Design Rationale 11

5.4.4.2 Processing 11

5.4.5 Local Function #5 11

5.4.5.1 Design Rationale 11

5.4.5.2 Processing 11

5.4.6 Local Function #6 11

5.4.6.1 Design Rationale 12

5.4.6.2 Processing 12

5.5 GLOBAL Function/Macro Definitions 12

6 Known Limitations with Design 13

7 UNIT TEST CONSIDERATION 14

Appendix A Abbreviations and Acronyms 15

Appendix B Glossary 16

Appendix C References 17

Introduction

Purpose

MDD for AdcDiagc

Scope

AdcDiagc & High-Level Description

Refer to FDD.

Design details of software module

Graphical representation of AdcDiagc

Data Flow Diagram

None.

Component level DFD

Refer FDD.

Function level DFD

Refer FDD.

Constant Data Dictionary

Program (fixed) Constants

Embedded Constants

Local Constants

Software Component Implementation

Sub-Module Functions

The sub-module functions are grouped based on similar functionality that needs to be executed in a given “State” of the system (refer States and Modes). For a given module, the MDD will identify the type and number of sub-modules required. The sub-module types are described below.

Init:

Design Rationale

None

Module Outputs

None

Per:

Design Rationale

Refer FDD.

Store Module Inputs to Local copies

Refer FDD

(Processing of function)………

Refer FDD

Store Local copy of outputs into Module Outputs

Refer FDD.

Server Runables

Interrupt Functions

None

Module Internal (Local) Functions

Local Function #1

Design Rationale

Processing

See “State 2” block in the Simulink model of the design.

Local Function #2

Design Rationale

Processing

See “State 4” block in the Simulink model of the design.

Local Function #3

Design Rationale

Processing

See “State 6” block in the Simulink model of the design.

Local Function #4

Design Rationale

Processing

See “State 0” block in the Simulink model of the design.

Local Function #5

Design Rationale

Processing

See “Adc0 State Based Processing” block in the Simulink model of the design.

Local Function #6

Design Rationale

Processing

See “Adc1 State Based Processing” block in the Simulink model of the design.

Local Function #7

Design Rationale

Processing

See “Adc Daigc Pointer” block in the Simulink model of the design.

Local Function #8

Design Rationale

Processing

See “Scan Group Accuracy Check” block in the Simulink model of the design.

Local Function #9

Design Rationale

Processing

See “Adc Parity Fault” block in the Simulink model of the design.

GLOBAL Function/Macro Definitions

Note: The server runnable of this component are non-rte. So they are actually global functions which should belong to this section. But as they are already described under Server Runnable section so it’s omitted here.

Known Limitations with Design

None.

UNIT TEST CONSIDERATION

The overflow for the following PIMs are intentional as they are used as rolling counter.

Rte_Pim_Adc0FltCntSt0

Rte_Pim_Adc0FltCntSt2

Rte_Pim_Adc0FltCntSt4

Rte_Pim_Adc0FltCntSt6

Rte_Pim_Adc1FltCntSt0

Rte_Pim_Adc1FltCntSt2

Rte_Pim_Adc1FltCntSt4

Rte_Pim_Adc1FltCntSt6

Abbreviations and Acronyms

Glossary

Note: Terms and definitions from the source “Nexteer Automotive” take precedence over all other definitions of the same term. Terms and definitions from the source “Nexteer Automotive” are formulated from multiple sources, including the following:

• ISO 9000

• ISO/IEC 12207

• ISO/IEC 15504

• Automotive SPICE® Process Reference Model (PRM)

• Automotive SPICE® Process Assessment Model (PAM)

• ISO/IEC 15288

• ISO 26262

• IEEE Standards

• SWEBOK

• PMBOK

• Existing Nexteer Automotive documentation

References

3 - AdcDiagc_PeerReviewCheckList

Rev 1.2

8-Jun-15

Peer Review Summary Sheet

Synergy Project Name:

kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. CM340A_AdcDiagc_Impl

Revision / Baseline:

kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. 1.5.1

Change Owner:

kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Avinash James

Work CR ID:

EA4#9069

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

N/A

MDD

N/A

Source Code

N/A

PolySpace

N/A

Integration Manual

N/A

Davinci Files

Comments:

Clean up changes. Removed unused files

General Guidelines: - The reviews shall be performed over the portions of the component that were modified as a result of the Change Request. - New components should include FDD Owner and Integrator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files) - Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed. - To review a component with multiple source code files use the "Add Source" button to create a Source code tab for each source file. - .h file should be reviewed with the source file as part of the source file.

4 - requirements