Component Design

1: CM200A_DmaCfgAndUse_NexteerDmaRegsh
2: CM200A_DmaCfgAndUse_PeripheralCfg
3: CM200A_DmaCfgAndUse_FDD_CheckList

Component Design

Module Detailled Design

Component Documentation

CM200A_DmaCfgAndUse_FDD_CheckList.html

1 - CM200A_DmaCfgAndUse_NexteerDmaRegsh

Nexteer Dma Regs
Field Reg Name	DMA Channel	Register	Register Field name	Field Length ( Bits)
DMASSDTFR9	9	DTFR	-	32
DMASSDRQC9	9	DTFRRQC	DRQC	1
DMASSTCC9	9	DCSTC	TCC	1
DMASSDTE9	9	DCEN	DTE	1
DMASSDRQC14	14	DTFRRQC	DRQC	1
DMASSTCC14	14	DCSTC	TCC	1
DMASSDTE14	14	DCEN	DTE	1
DMASSTC15	15	DCST	TC	1
DMASSTCC15	15	DCSTC	TCC	1

2 - CM200A_DmaCfgAndUse_PeripheralCfg

DMAC Peripheral Register Configuration (base Address 0xFFFF 8000h)
*DMA Channel*	*Configurable*	*Offset*	*Name*	*Update*	*Description*	*Bit #*	*Set/Clear*	*Comment*
-	-	*0030h*	*DM0CMV*	*Dynamic*	*DMAC0 register access protection violation register*	*31-0*	-	*protection violation register*
-	-	*0034h*	*DM1CMV*	*Dynamic*	*DMAC1 register access protection violation register*	*31-0*	-	*protection violation register*
-	-	*003Ch*	*CMVC*	*Static*	*Register access protection violation clear register*	*31-0*	7U	*Clear protection violation register*
*DMA00*	*MotAg0 Data Read : FromSPI Register (CSIH1) to Local RAM (Motor Control)*
DMA00	No	0100h + 4h *0	DM00CM	Static	DMAC0 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	3U	Channel Master SPID setting
						1	0U	Channel Master UM setting: Supervisor Mode
		0400h + 40h *0	DSA0	Static	DMAC0 Source Address	31-0	-	Address of (RegInpCSIH1RX0W)
		0404h + 40h *0	DDA0	Static	DMAC0 Destination Address	31-0	-	[Address of (MotCtrlMotAg0RawRes)]
		0408h + 40h *0	DTC0	Static	DMAC0 transfer Count	16-31	0	Address Reload Count
		0408h + 40h *0	DTC0	Static	DMAC0 transfer Count	0-15	3U	Transfer Count
		040Ch + 40h *0	DTCT0	Static	DMAC0 transfer control	27	0	DMA transfer when transfer errored
						26	1U	Hardware DMA transfer request
						18-20	0	No Chain
						16-17	0	No Chain
						15	0	Disable - Transfer count match interrupt
						14	1U	Enable - Transfer Completion interrupt
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	0	Increment -Destinable address count direction
						5-6	2U	Fixed - Source Address count direction
						2-4	2U	Transfer Data Size - 32 bits
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *0	DRSA0	Static	DMAC0 Reload Source Address	31-0	-	Addess of (RegInpCSIH1RX0W)
		0414h + 40h *0	DRDA0	Static	DMAC0 Reload Destination Address	31-0	-	[Address of (MotCtrlMotAg0RawRes)]
		0418h + 40h *0	DRTC0	Static	DMAC0 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *0	DRTC0	Static	DMAC0 Reload transfer Count	0-15	3U	Reload transfer count
		0430h + 40h *0	DTFR0	Static	DMAC0 DTFR Setting	1-7	75U	Hardware DMA transfer source = INTCSIH1IC1
		0430h + 40h *0	DTFR0	Static	DMAC0 DTFR Setting	0	1U	Enable - Hardware DMA transfer source
		0414h + 40h *0	DCEN0	Static	DMAC0 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA01*	Adc0 Results Read : FromADC Register (ADCD0) to Local RAM (Motor Control)
DMA01	No	0100h + 4h *1	DM01CM	Static	DMAC1 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	3U	Channel Master SPID setting
						1	0U	Channel Master UM setting: Supervisor Mode
		0400h + 40h *1	DSA1	Static	DMAC1 Source Address	31-0	-	Address of (RegInpADCD0DR00)
		0404h + 40h *1	DDA1	Static	DMAC1 Destination Address	31-0	-	[Address of (MotCtrlAdc0RawRes)]
		0408h + 40h *1	DTC1	Static	DMAC1 transfer Count	16-31	0	Address Reload Count
		0408h + 40h *1	DTC1	Static	DMAC1 transfer Count	0-15	3U	Transfer Count
		040Ch + 40h *1	DTCT1	Static	DMAC1 transfer control	27	0	DMA transfer when transfer errored
						26	1U	Hardware DMA transfer request
						18-20	0	No Chain
						16-17	0	No Chain
						15	0	Disable - Transfer count match interrupt
						14	1U	Disable - Transfer Completion interrupt
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	0	Increment -Destinable address count direction
						5-6	0	Increment - Source Address count direction
						2-4	4U	Transfer Data Size - 128 bit
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *1	DRSA1	Static	DMAC1 Reload Source Address	31-0	-	Address of (RegInpADCD0DR00)
		0414h + 40h *1	DRDA1	Static	DMAC1 Reload Destination Address	31-0	-	[Address of (MotCtrlAdc0RawRes)]
		0418h + 40h *1	DRTC1	Static	DMAC1 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *1	DRTC1	Static	DMAC1 Reload transfer Count	0-15	3U	Transfer Count
		0430h + 40h *1	DTFR1	Static	DMAC1 DTFR Setting	1-7	58U	Hardware DMA transfer source = INTADCD0I3
		0430h + 40h *1	DTFR1	Static	DMAC1 DTFR Setting	0	1U	Enable - Hardware DMA transfer source
		0414h + 40h *1	DCEN1	Static	DMAC1 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA02*	*MotAg1 Data Read : FromSPI Register (CSIH3) to Local RAM (Motor Control)*
DMA02	No	0100h + 4h *2	DM02CM	Static	DMAC2 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	3U	Channel Master SPID setting
						1	0U	Channel Master UM setting: Supervisor Mode
		0400h + 40h *2	DSA2	Static	DMAC2 Source Address	31-0	-	Address of (RegInpCSIH3RX0W)
		0404h + 40h *2	DDA2	Static	DMAC2 Destination Address	31-0	-	[Address of (MotCtrlMotAg1RawRes)]
		0408h + 40h *2	DTC2	Static	DMAC2 transfer Count	16	0	Address Reload Count
		0408h + 40h *2	DTC2	Static	DMAC2 transfer Count	0	3U	Transfer Count
		040Ch + 40h *2	DTCT2	Static	DMAC2 transfer control	27	0	DMA transfer when transfer errored
						26	1U	Hardware DMA transfer request
						18-20	0	No Chain
						16-17	0	No Chain
						15	0	Disable - Transfer count match interrupt
						14	1U	Enable - Transfer Completion interrupt
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	0	Increment -Destinable address count direction
						5-6	2U	Fixed - Source Address count direction
						2-4	2U	Transfer Data Size - 32 bits
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *2	DRSA2	Static	DMAC2 Reload Source Address	31-0	-	Addess of (RegInpCSIH3RX0W)
		0414h + 40h *2	DRDA2	Static	DMAC2 Reload Destination Address	31-0	-	[Address of (MotCtrlMotAg1RawRes)]
		0418h + 40h *2	DRTC2	Static	DMAC2 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *2	DRTC2	Static	DMAC2 Reload transfer Count	0-15	3U	Reload transfer count
		0430h + 40h *2	DTFR2	Static	DMAC2 DTFR Setting	1-7	83U	Hardware DMA transfer source = INTCSIH3IC0
		0430h + 40h *2	DTFR2	Static	DMAC2 DTFR Setting	0	1U	Enable - Hardware DMA transfer source
		0414h + 40h *2	DCEN2	Static	DMAC2 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA03*	*TSG Update Group 0 : FromLocal RAM (Motor Control) to TSG3 (TSG31)*
DMA03	No	0100h + 4h *3	DM03CM	Static	DMAC3 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	2U	Channel Master SPID setting
						1	0U	Channel Master UM setting: Supervisor Mode
		0400h + 40h *3	DSA3	Static	DMAC3 Source Address	31-0	-	Address of (MotCtrlTSG31DCMP0E)
		0404h + 40h *3	DDA3	Static	DMAC3 Destination Address	31-0	-	Address of (RegOutpTSG31DCMP0E)
		0408h + 40h *3	DTC3	Static	DMAC3 transfer Count	16-31	0	Address Reload Count
		0408h + 40h *3	DTC3	Static	DMAC3 transfer Count	0-15	3U	Transfer Count
		040Ch + 40h *3	DTCT3	Static	DMAC3 transfer control	27	0	DMA transfer when transfer errored
						26	1U	Hardware DMA transfer request
						18-20	4U	Chain DMAC 0 channel 4
						16-17	1U	Chain at last transfer
						15	0	Disable - Transfer count match interrupt
						14	0	Disable - Transfer Completion interrupt
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	0	Increment -Destinable address count direction
						5-6	0	Increment - Source Address count direction
						2-4	2U	Transfer Data Size - 32 bits
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *3	DRSA3	Static	DMAC3 Reload Source Address	31-0	-	Address of (MotCtrlTSG31DCMP0E)
		0414h + 40h *3	DRDA3	Static	DMAC3 Reload Destination Address	31-0	-	Address of (RegOutpTSG31DCMP0E)
		0418h + 40h *3	DRTC3	Static	DMAC3 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *3	DRTC3	Static	DMAC3 Reload transfer Count	0-15	3U	Transfer Count
		0430h + 40h *3	DTFR3	Static	DMAC3 DTFR Setting	1-7	103U	Hardware DMA transfer source = INTTSG31TI11
		0430h + 40h *3	DTFR3	Static	DMAC3 DTFR Setting	0	1U	Enable - Hardware DMA transfer source
		0414h + 40h *3	DCEN3	Static	DMAC3 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA04*	*TSG Update Group 1 : FromLocal RAM (Motor Control) to TSG3 (TSG31)*
DMA04	No	0100h + 4h *4	DM04CM	Static	DMAC4 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	2U	Channel Master SPID setting
						1	0U	Channel Master UM setting: Supervisor Mode
		0400h + 40h *4	DSA4	Static	DMAC4 Source Address	31-0	-	Address of (MotCtrlTSG31CMPWE)
		0404h + 40h *4	DDA4	Static	DMAC4 Destination Address	31-0	-	Address of (RegOutpTSG31CMPWE)
		0408h + 40h *4	DTC4	Static	DMAC4 transfer Count	16	0	Address Reload Count
		0408h + 40h *4	DTC4	Static	DMAC4 transfer Count	0	3U	Transfer Count
		040Ch + 40h *4	DTCT4	Static	DMAC4 transfer control	27	0	DMA transfer when transfer errored
						26	0	Software Request
						18-20	0	No chain
						16-17	0	No chain
						15	0	Disable - Transfer count match interrupt
						14	0	Disable - Transfer Completion interrupt
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	0	Increment -Destinable address count direction
						5-6	0	Increment - Source Address count direction
						2-4	2U	Size - 32 bit
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *4	DRSA4	Static	DMAC4 Reload Source Address	31-0	-	Address of (MotCtrlTSG31CMPWE)
		0414h + 40h *4	DRDA4	Static	DMAC4 Reload Destination Address	31-0	-	Address of (RegOutpTSG31CMPWE)
		0418h + 40h *4	DRTC4	Static	DMAC4 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *4	DRTC4	Static	DMAC4 Reload transfer Count	0-15	3U	Reload transfer count
		0430h + 40h *4	DTFR4	Static	DMAC4 DTFR Setting	1-7	0	Hardware DMA transfer source = N/A
		0430h + 40h *4	DTFR4	Static	DMAC4 DTFR Setting	0	0	Disable - Hardware DMA transfer source
		0414h + 40h *4	DCEN4	Static	DMAC4 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA05*	*Do not Configure this channel - Reserved for Future Use*
*DMA06*	*Do not Configure this channel - Reserved for Future Use*
*DMA07*	*Do not Configure this channel - Reserved for Future Use*
*DMA10*	*Do not Configure this channel - Reserved for Future Use*
*DMA11*	*2mSec to MotCtrl : FromLocal RAM (Motor Control) to Local RAM*
DMA11	No	0120h + 4h *1	DM11CM	Static	DMAC11 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	0U	Channel Master SPID setting
						1	1U	Channel Master UM setting
		0400h + 40h *9	DSA9	Static	DMAC9 Source Address	31-0	-	Address of (MotCtrlMgr_TwoMilliSecToMotCtrl_Rec)
		0404h + 40h *9	DDA9	Static	DMAC9 Destination Address	31-0	-	Address of (MotCtrlMgr_MotCtrlFromTwoMilliSec_Rec)
		0408h + 40h *9	DTC9	Static	DMAC9 transfer Count	16-31	0	Address Reload Count
		0408h + 40h *9	DTC9	Static	DMAC9 transfer Count	0-15	-	Size of "MotCtrlMgr_TwoMilliSecToMotCtrl_Rec" in bit /128
		040Ch + 40h *9	DTCT9	Static	DMAC9 transfer control	27	0	DMA transfer when transfer errored
						26	1U	Hardware DMA transfer request
						18-20	0	No chain
						16-17	0	No chain
						15	0	Disable - Transfer count match interrupt
						14	0	Disable - Transfer Completion interrupt
						13	0	Disable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	0	Increment -Destinable address count direction
						5-6	0	Increment - Source Address count direction
						2-4	4U	Size - 128 bits
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *9	DRSA9	Static	DMAC9 Reload Source Address	31-0	-	Address of (MotCtrlMgr_TwoMilliSecToMotCtrl_Rec)
		0414h + 40h *9	DRDA9	Static	DMAC9 Reload Destination Address	31-0	-	Address of (MotCtrlMgr_MotCtrlFromTwoMilliSec_Rec)
		0418h + 40h *9	DRTC9	Static	DMAC9 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *9	DRTC9	Static	DMAC9 Reload transfer Count	0-15	-	Size of "MotCtrlMgr_TwoMilliSecToMotCtrl_Rec" in bit /128
		0430h + 40h *9	DTFR9	Static	DMAC9 DTFR Setting	1-7	106U	Hardware DMA transfer source = INTTSG31VI
		0430h + 40h *9	DTFR9	Static	DMAC9 DTFR Setting	0	1U	Enable - Hardware DMA transfer source
		0414h + 40h *9	DCEN9	Static	DMAC9 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA12*	*MotAg1 Spi Start : FromLocal RAM (Motor Control) to SPI Register (CSIH3)*
DMA12	No	0120h + 4h *2	DM12CM	Static	DMAC12 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	2U	Channel Master SPID setting
						1	0U	Channel Master UM setting: Supervisor Mode
		0400h + 40h *10	DSA10	Static	DMAC10 Source Address	31-0	-	Address of (MotAg1TrsmStrt)
		0404h + 40h *10	DDA10	Static	DMAC10 Destination Address	31-0	-	Address of (RegOutpCSIH3MCTL2)
		0408h + 40h *10	DTC10	Static	DMAC10 transfer Count	16	0	Address Reload Count
		0408h + 40h *10	DTC10	Static	DMAC10 transfer Count	0	1U	Transfer Count
		040Ch + 40h *10	DTCT10	Static	DMAC10 transfer control	27	0	DMA transfer when transfer errored
						26	0	Software Request
						18-20	0	No chain
						16-17	0	No chain
						15	0	Disable - Transfer count match interrupt
						14	0	Disable - Transfer Completion interrupt
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	2U	Fixed -Destinable address count direction
						5-6	2U	Fixed - Source Address count direction
						2-4	2U	Size - 32 bit
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *10	DRSA10	Static	DMAC10 Reload Source Address	31-0	-	Address of (MotAg1TrsmStrt)
		0414h + 40h *10	DRDA10	Static	DMAC10 Reload Destination Address	31-0	-	Address of (RegOutpCSIH3CTL2)
		0418h + 40h *10	DRTC10	Static	DMAC10 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *10	DRTC10	Static	DMAC10 Reload transfer Count	0-15	1U	Reload transfer count
		0430h + 40h *10	DTFR10	Static	DMAC10 DTFR Setting	1-7	0	Hardware DMA transfer source = N/A
		0430h + 40h *10	DTFR10	Static	DMAC10 DTFR Setting	0	0	Disable - Hardware DMA transfer source
		0414h + 40h *10	DCEN10	Static	DMAC10 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA13*	*MotAg1 Reset Read Pointer: From Local RAM (Motor Control) to SPI Register (CSIH3)*
DMA13	No	0120h + 4h *3	DM13CM	Static	DMAC13 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	2U	Channel Master SPID setting
						1	0U	Channel Master UM setting: Supervisor Mode
		0400h + 40h *11	DSA11	Static	DMAC11 Source Address	31-0	-	Address of (MotAg1ReadPtrRst)
		0404h + 40h *11	DDA11	Static	DMAC11 Destination Address	31-0	-	Address of (RegOutpCSIH3MRWP0)
		0408h + 40h *11	DTC11	Static	DMAC11 transfer Count	16	0	Address Reload Count
		0408h + 40h *11	DTC11	Static	DMAC11 transfer Count	0	1U	Transfer Count
		040Ch + 40h *11	DTCT11	Static	DMAC11 transfer control	27	0	DMA transfer when transfer errored
						26	1U	Hardware Request
						18-20	2U	Chain DMAC 1 channel 2
						16-17	1U	Chain at last transfer
						15	0	Disable - Transfer count match interrupt
						14	0	Disable - Transfer Completion interrupt
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	2U	Fixed -Destinable address count direction
						5-6	2U	Fixed - Source Address count direction
						2-4	2U	Size - 32 bit
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *11	DRSA11	Static	DMAC11 Reload Source Address	31-0	-	Address of (MotAg1ReadPtrRst)
		0414h + 40h *11	DRDA11	Static	DMAC11 Reload Destination Address	31-0	-	Address of (RegOutpCSIH3MRWP0)
		0418h + 40h *11	DRTC11	Static	DMAC11 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *11	DRTC11	Static	DMAC11 Reload transfer Count	0-15	1U	Reload transfer count
		0430h + 40h *11	DTFR11	Static	DMAC11 DTFR Setting	1-7	106U	Hardware DMA transfer source = INTTSG31VI
		0430h + 40h *11	DTFR11	Static	DMAC11 DTFR Setting	0	1U	Disable - Hardware DMA transfer source
		0414h + 40h *11	DCEN11	Static	DMAC11 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA14*	*MotAg0 Spi Start : FromLocal RAM (Motor Control) to SPI Register (CSIH1)*
DMA14	No	0120h + 4h *4	DM14CM	Static	DMAC14 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	2U	Channel Master SPID setting
						1	0U	Channel Master UM setting: Supervisor Mode
		0400h + 40h *12	DSA12	Static	DMAC12 Source Address	31-0	-	Address of (MotAg0TrsmStrt)
		0404h + 40h *12	DDA12	Static	DMAC12 Destination Address	31-0	-	Address of (RegOutpCSIH1MCTL2)
		0408h + 40h *12	DTC12	Static	DMAC12 transfer Count	16	0	Address Reload Count
		0408h + 40h *12	DTC12	Static	DMAC12 transfer Count	0	1U	Transfer Count
		040Ch + 40h *12	DTCT12	Static	DMAC12 transfer control	27	0	DMA transfer when transfer errored
						26	0	Software Request
						18-20	0	No chain
						16-17	0	No chain
						15	0	Disable - Transfer count match interrupt
						14	0	Disable - Transfer Completion interrupt
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	2U	Fixed -Destinable address count direction
						5-6	2U	Fixed - Source Address count direction
						2-4	2U	Size - 32 bit
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *12	DRSA12	Static	DMAC12 Reload Source Address	31-0	-	Address of (MotAg0TrsmStrt)
		0414h + 40h *12	DRDA12	Static	DMAC12 Reload Destination Address	31-0	-	Address of (RegOutpCSIH1MCTL2)
		0418h + 40h *12	DRTC12	Static	DMAC12 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *12	DRTC12	Static	DMAC12 Reload transfer Count	0-15	1U	Reload transfer count
		0430h + 40h *12	DTFR12	Static	DMAC12 DTFR Setting	1-7	0	Hardware DMA transfer source = N/A
		0430h + 40h *12	DTFR12	Static	DMAC12 DTFR Setting	0	0	Disable - Hardware DMA transfer source
		0414h + 40h *12	DCEN12	Static	DMAC12 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA15*	*MotAg0 Reset Read Pointer: From Local RAM (Motor Control) to SPI Register (CSIH1)*
DMA15	No	0120h + 4h *5	DM15CM	Static	DMAC15 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	2U	Channel Master SPID setting
						1	0U	Channel Master UM setting: Supervisor Mode
		0400h + 40h *13	DSA13	Static	DMAC13 Source Address	31-0	-	Address of (MotAg0ReadPtrRst)
		0404h + 40h *13	DDA13	Static	DMAC13 Destination Address	31-0	-	Address of (RegOutpCSIH1MRWP0)
		0408h + 40h *13	DTC13	Static	DMAC13 transfer Count	16	0	Address Reload Count
		0408h + 40h *13	DTC13	Static	DMAC13 transfer Count	0	1U	Transfer Count
		040Ch + 40h *13	DTCT13	Static	DMAC13 transfer control	27	0	DMA transfer when transfer errored
						26	1U	Hardware Request
						18-20	4U	Chain DMAC 1 channel 4
						16-17	1U	Chain at last transfer
						15	0	Disable - Transfer count match interrupt
						14	0	Disable - Transfer Completion interrupt
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	2U	Fixed -Destinable address count direction
						5-6	2U	Fixed - Source Address count direction
						2-4	2U	Size - 32 bit
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *13	DRSA13	Static	DMAC13 Reload Source Address	31-0	-	Address of (MotAg0ReadPtrRst)
		0414h + 40h *13	DRDA13	Static	DMAC13 Reload Destination Address	31-0	-	Address of (RegOutpCSIH1MRWP0)
		0418h + 40h *13	DRTC13	Static	DMAC13 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *13	DRTC13	Static	DMAC13 Reload transfer Count	0-15	1U	Reload transfer count
		0430h + 40h *13	DTFR13	Static	DMAC13 DTFR Setting	1-7	104U	Hardware DMA transfer source = INTTSG31TI12
		0430h + 40h *13	DTFR13	Static	DMAC13 DTFR Setting	0	1U	Disable - Hardware DMA transfer source
		0414h + 40h *13	DCEN13	Static	DMAC13 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA16*	*Adc1 Results : FromADC Register (ADCD1) to Local RAM (Motor Control)*
DMA16	No	0120h + 4h *6	DM16CM	Static	DMAC16 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	3U	Channel Master SPID setting
						1	1U	Channel Master UM setting
		0400h + 40h *14	DSA14	Static	DMAC14 Source Address	31-0	-	Address of (RegInpADCD1DR00)
		0404h + 40h *14	DDA14	Static	DMAC14 Destination Address	31-0	-	Address of (MotCtrlAdc1RawRes)
		0408h + 40h *14	DTC14	Static	DMAC14 transfer Count	16	0	Address Reload Count
		0408h + 40h *14	DTC14	Static	DMAC14 transfer Count	0	3U	Transfer Count
		040Ch + 40h *14	DTCT14	Static	DMAC14 transfer control	27	0	DMA transfer when transfer errored
						26	1U	Hardware Request
						18-20	7U	Chain DMAC 1 Channel 7
						16-17	1U	Chain at last transfer
						15	0	Disable - Transfer count match interrupt
						14	0	Disable - Transfer Completion interrupt
						13	0	Disable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	0	Increment -Destinable address count direction
						5-6	0	Increment - Source Address count direction
						2-4	4U	Transfer Data Size - 128 bit
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *14	DRSA14	Static	DMAC14 Reload Source Address	31-0	-	Address of (RegInpADCD1DR00)
		0414h + 40h *14	DRDA14	Static	DMAC14 Reload Destination Address	31-0	-	Address of (MotCtrlAdc1RawRes)
		0418h + 40h *14	DRTC14	Static	DMAC14 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *14	DRTC14	Static	DMAC14 Reload transfer Count	0-15	3U	Transfer Count
		0430h + 40h *14	DTFR14	Static	DMAC14 DTFR Setting	1-7	61U	Hardware DMA transfer source = INTADCD1I1
		0430h + 40h *14	DTFR14	Static	DMAC14 DTFR Setting	0	1U	Enable - Hardware DMA transfer source
		0414h + 40h *14	DCEN14	Static	DMAC14 Channel operation enable setting	0	1U	Enable - Channel Operation
*DMA17*	*MotCtrl to 2mSec : FromLocal RAM (Motor Control) to Local RAM (Motor Control)*
DMA17	No	0120h + 4h *7	DM17CM	Static	DMAC17 Channel Master Setting	6-4	1U	Channel Master PEID Setting
						3-2	0U	Channel Master SPID setting
						1	1U	Channel Master UM setting
		0400h + 40h *15	DSA15	Static	DMAC15 Source Address	31-0	-	Address of (MotCtrlMgr_MotCtrlToTwoMilliSec_Rec)
		0404h + 40h *15	DDA15	Static	DMAC15 Destination Address	31-0	-	Address of (MotCtrlMgr_TwoMilliSecFromMotCtrl_Rec)
		0408h + 40h *15	DTC15	Static	DMAC15 transfer Count	16-31	0	Address Reload Count
		0408h + 40h *15	DTC15	Static	DMAC15 transfer Count	0-15	-	Size of "MotCtrlMgr_MotCtrlToTwoMilliSec_Rec" in bit /128
		040Ch + 40h *15	DTCT15	Static	DMAC15 transfer control	27	0	DMA transfer when transfer errored
						26	0	Software DMA Request
						18-20	0	No chain
						16-17	0	No chain
						15	0	Disable - Transfer count match interrupt
						14	0	Disable - Transfer Completion interrupt
						13	1U	Enable - Continuous transfer
						11-12	0	Disable -Reload function 2
						9-10	3U	Enable - Reload function 1(SA, DA, TC reloaded)
						7-8	0	Increment -Destinable address count direction
						5-6	0	Increment - Source Address count direction
						2-4	4U	Size - 128 bit
						0-1	1U	Block transfer 1 by transfer count
		0410h + 40h *15	DRSA15	Static	DMAC15 Reload Source Address	31-0	-	Address of (MotCtrlMgr_MotCtrlToTwoMilliSec_Rec)
		0414h + 40h *15	DRDA15	Static	DMAC15 Reload Destination Address	31-0	-	Address of (MotCtrlMgr_TwoMilliSecFromMotCtrl_Rec)
		0418h + 40h *15	DRTC15	Static	DMAC15 Reload transfer Count	16-31	0	Reload Address reload count
		0418h + 40h *15	DRTC15	Static	DMAC15 Reload transfer Count	0-15	-	Size of "MotCtrlMgr_MotCtrlToTwoMilliSec_Rec" in bit /128
		0430h + 40h *15	DTFR15	Static	DMAC15 DTFR Setting	1-7	0	Hardware DMA transfer source = N/A
		0430h + 40h *15	DTFR15	Static	DMAC15 DTFR Setting	0	0	Disable - Hardware DMA transfer source
		0414h + 40h *15	DCEN15	Static	DMAC15 Channel operation enable setting	0	1U	Enable - Channel Operation

Note 1:		ZZZ= Dynamic change value, X = Don’t Care, 1=Set, 0=Clear, -=Loaded Data/Configurable Data, unspecified register bits shall have safe default value
Note 2:		RSENTn, where n = 0

3 - CM200A_DmaCfgAndUse_FDD_CheckList

Nexteer_Template_V1.0

Overview

Peer Review Instructions
Technical Review Checklist
Template Change Log

Sheet 1: Peer Review Instructions

Instructions for Functional Design Package Peer Review

PRE-MEETING
	Function Owner	Confirm that requirements are reviewed and approved PRIOR to the FDP peer review
	Function Owner	Start with latest version of the template for any "first reviews" - Continue to use existing temmplate for re-reviews
	Function Owner	Provide the functional design package (changed documents) to the invited attendees 1-2 working days in advance of review
	Function Owner	Notify the assigned peer reviewer and make sure they are prepared to do their function in the meeting
	Function Owner	Identify necessary attendance and invite to meeting
	Function Owner	Complete the "Author" column information for sections 1 through 3 prior to the review
	Function Owner	Complete the attendance invitation list in section 5
	Function Owner	For Re-reviews only: Complete the column "remarks by author" to identify actions taken to address items found in earlier reviews.

DURING MEETING
	Function Owner	Present document changes to the review team
	Peer Reviewer	Capture attendance of the review
	Peer Reviewer	Capture actions and issues in section 4. Identify issue summary, Document type, Reference (Requirement ID, section number, etc), Defect Type and indicate status as "OPEN"

POST MEETING
	Function Owner	Follow up on all "open" items. Update "Summary of Resolution" to indicate what was done or decided.
	Function Owner	Schedule follow up review OR review open items with peer reviewer and obtain agreement to close
	Peer Reviewer	Close change request in system and confirm all associated tasks are complete. Upload peer review checklist (this document) with any FDP updates

Sheet 2: Technical Review Checklist

Technical Review Checklist - Template Version 01.00.06
Product Name	Electric Power Steering	Electrical Arch.	4	Review Scope		Defect Type	Numbers
Function Name	CM200A DmaCfgAndUse	Revision	2.1.0	WCR# :EA4#6083 - 2ms ADC Dma Transfer wait time change from 100 to 400 - Capture Max wait time.		Requirement	0
Author	Keyur Patel					Interface	0
		Effort				Design	0
		Review Effort(Hrs.)	1.00			Standards	0
		Corr+Verf effort(Hrs.)				Documentation	0
		Total Effort (Hrs.)	1.00			Others	0
						Total	0
Checklist No.	Description of Check	Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author	Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer	Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer	Author: Defect type to be selected. Defect Type	Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author	Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status
1	Section 1: TECHNICAL CHECK
1.1	Confirm that all signal inputs into the FDP (Functional Design Package) are contained within and exactly named as the "Available_Nexteer_Signals.m" states.	NA	NA
1.2	Confirm any removed signal inputs from the design have been removed from the "Available_Nexteer_Signals.m" file.	NA	NA
1.3	Confirm all signals and parameters (outputs, calibrations, constants, non-volatile memory) used in the *.m file and the design conform to the AutoSAR naming convention documentation.	NA	NA
1.4	Confirm *.m file has been provided to the "Available_Signal_Names" Author.	NA	NA
1.5	Confirm Electrical Systems interface map is updated to reflect the FDP (signal IO)	No	No
2	Section 2: Safety CHECK	Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author	Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer	Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer	Author: Defect type to be selected. Defect Type	Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author	Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status
2.1	Confirm that the functional DFMEA is up to date based on the design in the current package.	NA	NA
2.2	Confirm that Safety requirements (ASIL A - D) are referenced in the design documents.	NA	NA
3	Section 3: Lessons Learned	Author: This column is for Self review. Author shall fill Yes/No/NA against each point in checklist. Author	Author: This column is for reviewer. Reviewer shall fill Yes/No/NA against each point in checklist. Reviewer	Author: Detailed Description of the finding shall be provided by the reviewer. Description of finding by reviewer	Author: Defect type to be selected. Defect Type	Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author	Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status
3.1	Have functions depending upon system state been reviewed for need to be executed at the 2ms rate to avoid system lag issues?	Yes	Yes
3.2	Have all diagnostics (NTCs) been confirmed to show logic to invoke a diagnostic "PASS" for control of the status byte at the customer level.	NA	NA
3.3	Has the requirements traceability steps used the RMI steps as defined in the FDD authoring spec to generate the traceability report?	NA	NA
3.4	Has the requirements traceability report been verified to only contain ONLY requirements from the FR.	NA	NA
3.5	Confirm that all PIM that does NOT have an initialization value of zero is initialized in an INIT function.	Yes	Yes
3.6	Confirm if NVM is used, the NVM is defined in structures	NA	NA
3.7	If the function uses NVM, confirm that the m file identifies the "write" event	NA	NA


4	Section 4: Issues / Actions Identified	Document	Reference	Summary of resolution	Author: Defect type to be selected. Defect Type	Author: What action is taken to fix the comment & other remarks need to be filled by author. Remarks By Author	Author: Data in this column shall be filled by reviewer after checking whether the rework is completed. Status
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
4.22
4.23
4.24
4.25
5	Section 5: APPROVALS
Role	First Review	Date	Attendance	Approval?
Function Owner*	Keyur Patel	6/8/2016	Yes	Yes
Peer Reviewer*	Gerald McCann		Yes
EPDT Engineer
ES Engineer
Software Lead	Avinash		Yes
Hardware Lead
Test Lead
Safety Lead
Role	Second Review (if required)	Date	Attendance	Approval?
Function Owner*
Peer Reviewer*
EPDT Engineer
ES Engineer
Software Lead
Hardware Lead
Test Lead
Safety Lead
Role	Third Review (if required)	Date	Attendance	Approval?
Function Owner*
Peer Reviewer*
EPDT Engineer
ES Engineer
Software Lead
Hardware Lead
Test Lead
Safety Lead
Role	Fourth Review (if required)	Date	Attendance	Approval?
Function Owner*
Peer Reviewer*
EPDT Engineer
ES Engineer
Software Lead
Hardware Lead
Test Lead
Safety Lead
Role	Add more if necessary	Date	Attendance	Approval?


P.S.:	Yes indicates adherence
	No indicates non-adherence, reviewer shall provide suitable comments at the end of this document for each point.
	NA indicates not applicable

Sheet 3: Template Change Log

Rev	Change	Author
01.00.05	Added lesson learned #3.5	MDK
01.00.06	Added lesson learned #3.6, 3.7 - Structure and writing of NVM in mfiles and models.	MDK