Component Implementation

• 1: requirements
• 2: TSG31CfgAndUse Integration Manual
• 3: TSG31CfgAndUse_MDD
• 4: TSG31CfgAndUse_Peer_Review

1 - requirements

2 - TSG31CfgAndUse Integration Manual

TSG31CfgAndUse

Integration Manual

VERSION: 1.0

DATE: 28-Apr-2015

Revision History

Table of Contents

1 Abbrevations And Acronyms 4

2 References 5

3 Dependencies 6

3.1 SWCs 6

3.2 Global Functions(Non RTE) to be provided to Integration Project 6

4 Configuration REQUIREMeNTS 7

4.1 Build Time Config 7

4.2 Configuration Files to be provided by Integration Project 7

4.3 Da Vinci Parameter Configuration Changes 7

4.4 DaVinci Interrupt Configuration Changes 7

4.5 Manual Configuration Changes 7

5 Integration DATAFLOW REQUIREMENTS 8

5.1 Required Global Data Inputs 8

5.2 Required Global Data Outputs 8

5.3 Specific Include Path present 8

6 Runnable Scheduling 9

7 Memory Map REQUIREMENTS 10

7.1 Mapping 10

7.2 Usage 10

7.3 Non RTE NvM Blocks 10

7.4 RTE NvM Blocks 10

8 Compiler Settings 11

8.1 Preprocessor MACRO 11

8.2 Optimization Settings 11

9 Appendix 12

Abbrevations And Acronyms

References

This section lists the title & version of all the documents that are referred for development of this document

Dependencies

SWCs

Note : Referencing the external components should be avoided in most cases. Only in unavoidable circumstance external components should be referred. Developer should track the references.

Global Functions(Non RTE) to be provided to Integration Project

See FDD – CM475A_TSG31CfgAndUse_DataDict.m file

Configuration REQUIREMeNTS

Build Time Config

Configuration Files to be provided by Integration Project

<Configuration file that will generated from this components that will require Da Vinci Config generation or manual generation. Describe each parameter >

Da Vinci Parameter Configuration Changes

DaVinci Interrupt Configuration Changes

Manual Configuration Changes

Integration DATAFLOW REQUIREMENTS

Required Global Data Inputs

See FDD – CM475A_TSG31CfgAndUse_DataDict.m file

Required Global Data Outputs

See FDD – CM475A_TSG31CfgAndUse_DataDict.m file

Specific Include Path present

Yes

Runnable Scheduling

This section specifies the required runnable scheduling.

.

Memory Map REQUIREMENTS

Mapping

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Table 1: ARM Cortex R4 Memory Usage

Non RTE NvM Blocks

Note : Size of the NVM block if configured in developer

RTE NvM Blocks

Note : Size of the NVM block if configured in developer

Compiler Settings

Preprocessor MACRO

<Define all the preprocessor Macros needed and conditions when needed>.

Optimization Settings

<Define Optimization levels that are needed and conditions when needed>.

Appendix

<This section is for appendix>

3 - TSG31CfgAndUse_MDD

TSG31 Timer Subsystem Configuration and Use

Module Design Document

VERSION: 2.0

DATE: 20-Jun-2015

Revision History

Table of Contents

1 Abbrevations And Acronyms 5

2 References 6

3 TSG31CfgAndUse High-Level Description 7

3.1 Design details of software module 7

3.2 Graphical representation of CDD_TSG31CfgAndUse 7

3.3 Data Flow Diagram 7

3.3.1 Module level DFD 8

3.3.2 Sub-Module level DFD 8

3.4 COMPONENT FLOW DIAGRAM 8

4 Variable Data Dictionary 9

4.1 User defined typedef definition/declaration 9

4.2 Variable definition for enumerated types 9

5 Constant Data Dictionary 10

5.1 Program(fixed) Constants 10

5.1.1 Embedded Constants 10

5.1.1.1 Local 10

5.1.1.2 Global 10

5.1.2 Module specific Lookup Tables Constants 10

6 Software Module Implementation 11

6.1 Sub-Module Functions 11

6.1.1 Motor Control Periodic: TSG31CfgAndUsePer1 11

6.1.1.1 Design Rationale 11

6.2 Initialization Functions 11

6.2.1 Init: TSG31CfgAndUseInit1 11

6.2.1.1 Design Rationale 11

6.2.1.2 Module Outputs 11

6.2.1.3 Module Internal 11

6.3 PERIODIC FUNCTIONS 11

6.3.1 Per: TSG31CfgAndUsePer2 11

6.3.1.1 Design Rationale 11

6.3.1.2 Store Module Inputs to Local copies 11

6.3.1.3 (Processing of function)……… 11

6.3.1.4 Store Local copy of outputs into Module Outputs 11

6.4 Interrupt Functions 12

6.5 Serial Communication Functions 12

6.6 Local Function/Macro Definitions 12

6.6.1 Local Function #1 12

6.6.1.1 Description 12

6.6.2 Local Function #2 12

6.6.2.1 Description 12

6.6.3 Local Function #3 12

6.6.3.1 Description 12

6.6.4 Local Function #4 12

6.6.4.1 Description 13

6.6.5 Local Function #5 13

6.6.5.1 Description 13

6.6.6 Local Function #6 13

6.6.6.1 Description 13

6.6.7 Local Function #7 13

6.6.7.1 Description 13

6.6.7.2 Design Rationale 13

6.6.8 Local Function #8 14

6.6.8.1 Description 14

6.6.8.2 Design Rationale 14

6.7 GLObAL Function/Macro Definitions 14

6.8 TRANSIENT FUNCTIONS 14

7 Known Limitations With Design 15

8 UNIT TEST CONSIDERATION 16

9 Appendix 17

Abbrevations And Acronyms

References

This section lists the title & version of all the documents that are referred for development of this document

TSG31CfgAndUse High-Level Description

The CDD_TSG31CfgAndUse component is the complex driver for the TSG31 timer subsystem. The timer subsystem is used to trigger DMA transfers and SPI transfers, and to set the GPIO pins for the three phase PWM outputs. The component contains two .c source files, both described in this MDD: CDD_TSG31CfgAndUse.c contains the RTE runnables; CDD_TSG31CfgAndUse_MotCtrl.c contains the motor control runnable.

Design details of software module

See FDD.

Graphical representation of CDD_TSG31CfgAndUse

Data Flow Diagram

See FDD.

Module level DFD

See FDD.

Sub-Module level DFD

See FDD.

COMPONENT FLOW DIAGRAM

See FDD.

Variable Data Dictionary

User defined typedef definition/declaration

<This section documents any user types uniquely used for the module.>

Variable definition for enumerated types

Constant Data Dictionary

Program(fixed) Constants

Embedded Constants

< All program specific constants will be defined in detail >

Local

Global

<This section lists the global constants used by the module. For details on global constants, refer to the Data Dictionary for the application>

Module specific Lookup Tables Constants

<(This is for lookup tables (arrays) with fixed values, same name as other tables)>

Software Module Implementation

Note: All the non RTE signals defined in m file are implemented as global varibles managed by motor control manager. RTE can not manage motor control runnables inputs and outputs.

Sub-Module Functions

Motor Control Periodic: TSG31CfgAndUsePer1

See FDD TSG31CfgAndUsePer1 model block.

Design Rationale

The truth table in the TSG31CfgAndUsePer1 model block is just selecting between four sets of statements based on the value of a single variable. This was implemented as an if/else if. For run-time efficiency, since this is a motor control runnable, the “normal operation” case was checked first; since the normal operation and default cases are the same, the statements in this row of the truth table action table are repeated in the trailing else of the if/else.

Initialization Functions

Init: TSG31CfgAndUseInit1

Design Rationale

All register initialization that is allowed at the register level (see FieldNames tab of the CM475A_TSG31RegisterConfiguration.xlms spreadsheet in the FDD) is done at the register level to save execution time as compared to the read/modify/writes that would be needed to initialize at the field level. Field level initialization done only where required by the spreadsheet.

Module Outputs

See FDD: TSG31CfgAndUseInit1 model block and the FieldNames tab of the CM475A_TSG31RegisterConfiguration.xlms spreadsheet.

Module Internal

See FDD: TSG31CfgAndUseInit1 model block for Per Instance Memory initialization.

PERIODIC FUNCTIONS

Per: TSG31CfgAndUsePer2

Design Rationale

Each action block of the switch/case was implemented as a local function. To minimize complexity, the “Out1” truth table output and the switch case block were combined in the implementation with nested “if”s which directly call the switch/case action functions

Store Module Inputs to Local copies

See FDD: TSG31CfgAndUsePer2 model block.

(Processing of function)………

See FDD: TSG31CfgAndUsePer2 model block.

Store Local copy of outputs into Module Outputs

See FDD: TSG31CfgAndUsePer2 model block

Interrupt Functions

None

Serial Communication Functions

None

Local Function/Macro Definitions

Local Function #1

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/No Transition SysState = Enable

Local Function #2

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/Transition from Enable

Local Function #3

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/Transition to Enable

Local Function #4

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/No Transition SysState != Enable

Local Function #5

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/Transition from Enable/Map FET Ctrl Signals to GPIO and Set Low (also same block name in other model layers)

Local Function #6

Description

See FDD model block: CM475A_TSG31CfgAndUse/TSG31CfgAndUse/TSG31CfgAndUsePer2/Transition from Enable/Map FET Ctrl Signals to GPIO and Set Low/Map Pins to GPIO (also same block name in other model layers)

Local Function #7

Description

See FDD model block: CM475A_TSG31CfgAndUse_ModelLibrary_Rev001/RawTime_NanoSec to RawTimerCount_Cnt Conversion Block

Design Rationale

Because this function is called by a motor control runnable, it is coded as an inline function to maximize the chance that the compiler will inline it, in order to improve runtime efficiency of the motor control loop.

GLObAL Function/Macro Definitions

None

TRANSIENT FUNCTIONS

None

Known Limitations With Design

1. Expected input ranges of the nanosecond to timer count conversion functions are based on FDD assumptions about the minimum PWM period that may ever be used, as stated in comments in the FDD model.

UNIT TEST CONSIDERATION

None

Appendix

<This section is for appendix>

4 - TSG31CfgAndUse_Peer_Review

Rev 7.1

8-Jun-15

Peer Review Summary Sheet

Synergy Project Name:

kzshz2: Intended Use: Identify which component is being reviewed. This should be the Module Short Name from Synergy Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. CM475A_TSG31CfgAndUse_Impl

Revision / Baseline:

kzshz2: Intended Use: Identify which Synergy revision of this component is being reviewed Rationale: Required for traceability. It will help to ensure this form is not attaced to the the wrong change request. 1.3.1

Change Owner:

kzshz2: Intended Use: Identify the developer who made the change(s) Rationale: A change request may have more than one resolver, this will help identify who made what change. Change owner identification may be required by indusrty standards. Nick Saxton

Work CR ID:

EA4#7743

kzshz2: Intended Use: Intended to identify at a high level to the reviewers which areas of the component have been changed. Rationale: This will be good information to know when ensuring appropriate reviews have been completed. Modified File Types:

kzshz2: Intended Use: Identify who where the reviewers, what they reviewed, and if the reviewed changes have been approved to release the code for testing. Comments here should be at a highlevel, the specific comments should be present on the specific review form sheet. Rationale: Since this Form will be attached to the Change Request it will confirm the approval and provides feedback in case of audits. ADD DR Level Move reviewer and approval to individual checklist form Review Checklist Summary:

Reviewed:

MDD

Source Code

PolySpace

Integration Manual

Davinci Files

Comments:

Range changes to PIMs and unused physical output ports removed from data dictionary - no functional changes

General Guidelines: - The reviews shall be performed over the portions of the component that were modified as a result of the Change Request. (Note: If this peer review form was not completed for pervious versions of this component, the Change Owner should review the entire component and complete the checklist in its entirety prior and check the form into Syngery. This may be done prior to reviewing the modifications for this Change Result) - The Change Owner shall responsible for completing the entire checklist (Pre and Group review items) prior holding the initial group review. - New components should include FDD Owner and Intergator as apart of the Group Review Board (Source Code, Integration Manual, and Davinci Files) - Select "Yes" and add "N/A" to the comments for checklist items that are not applicable for this change - Enter any rework required into the comment field and select No. When the rework is complete, review again using this same review sheet and select Yes. Add date and additional comment stating that the rework is completed. - To review a component with multiple source code files create a Source code tab for each source file. - .h file should be reviewed with the source file as part of the source file.