SVDiag_Integration_Manual

1 Dependencies 2

1.1 SWCs 2

1.2 Functions to be provided to Integration Project 2

2 Configuration 3

2.1 Build Time Config 3

2.2 Configuration Files to be provided by Integration Project 3

2.2.1 Da Vinci Config generation 3

2.2.2 Manual Configuration Changes 3

3 Integration 4

3.1 Required Global Data Inputs 4

3.2 Optional Global Data Inputs 4

3.3 Specific Include Path present 4

4 Runnable Scheduling 5

5 Memory Mapping 6

5.1 Mapping 6

5.2 Usage 6

5.3 NvM Blocks 6

6 Compiler Settings 6

6.1 Preprocessor MACRO 6

6.2 Optimization Settings 6

7 Revision Control Log 7

Dependencies

SWCs

ModuleRequired Feature
None

Global Functions(Non RTE) to be provided to Integration Project

< Global function (except the ones that are defined in RTE modules) that is defined in this component but used by other function>

Configuration

Build Time Config

ModulesNotes
None

Configuration Files to be provided by Integration Project

<Configuration file that will generated from this components that will require Da Vinci Config generation or manual generation. Describe each parameter >

Da Vinci Parameter Configuration Changes

ParameterNotesSWC
None

DaVinci Interrupt Configuration Changes

ISR NameVIM #Priority DependencyNotes
None

Manual Configuration Changes

ConstantNotesSWC
None

Integration

Required Global Data Inputs

ExpectedOnTimeA_Cnt_u32

ExpectedOnTimeB_Cnt_u32

ExpectedOnTimeC_Cnt_u32

LRPRCorrectedMtrPosCaptured_Rev_f32

LRPRModulationIndexCaptured_Uls_f32

LRPRPhaseadvanceCaptured_Cnt_s16

MeasuredOnTimeA_Cnt_u32

MeasuredOnTimeB_Cnt_u32

MeasuredOnTimeC_Cnt_u32

MotorVelMRFUnfiltered_MtrRadpS_f32

MtrElecMechPolarity_Cnt_s08

PDActivateTest_Cnt_lgc

MtrDrvrInitStart_Cnt_lgc

VswitchClosed_Cnt_lgc

Required Global Data Outputs

SVDiag_LowPhReasErrorAcc_Cnt_u16

SVDiag_HighResPhsReasDisable_u8

SVDiag_LowResPhsReasDisable_u8

SVDiag_MtrDrvInitComp_Cnt_lgc

SVDiag_GateDriveFltAcc_Cnt_u16

SVDiag_GenGateDriveFltAcc_Cnt_u16

SVDiag_OnStateFltAcc_Cnt_u16

Specific Include Path present

None

Runnable Scheduling

This section specifies the required runnable scheduling.

InitScheduling RequirementsTrigger
DigPhsReasDiag_InitExecuted once after the RTE is started before first call of MtrDrvDiag_Per1RTE (at Startup)
RunnableScheduling RequirementsTrigger
DigPhsReasDiag_Per1Not in OFF, DISABLE, or WARMINIT modesRte 2ms task
DigPhsReasDiag_Trans1In OPERATE modeOn entering mode
MtrDrvDiag_Per1Not in DISABLE or OFF modesRte 2ms task
MtrDrvDiag_Per2Not in OPERATE or WARMINIT modesRte 2ms task
MtrDrvDiag_Trns1In WARMINIT modeOn entering mode

Memory Mapping

Mapping

Memory SectionContentsNotes
< Memory mapping Info>
DIGPHSREASDIAG_START_SEC_VAR_CLEARED_32
DIGPHSREASDIAG_START_SEC_VAR_CLEARED_BOOLEAN
DIGPHSREASDIAG_START_SEC_VAR_CLEARED_16
DIGPHSREASDIAG_START_SEC_VAR_CLEARED_8
MTRDRVDIAG_START_SEC_VAR_CLEARED_32
MTRDRVDIAG_START_SEC_VAR_CLEARED_16
MTRDRVDIAG_START_SEC_VAR_CLEARED_BOOLEAN
MTRDRVDIAG_START_SEC_VAR_CLEARED_UNSPECIFIED

* Each …START_SEC… constant is terminated by a …STOP_SEC… constant as specified in the AUTOSAR Memory Mapping requirements.

Usage

Table 1: ARM Cortex R4 Memory Usage

FeatureRAMROM
Full

Non RTE NvM Blocks

Block Name
None

Note : Size of the NVM block if configured in developer

RTE NvM Blocks

Block Name
None

Note : Size of the NVM block if configured in developer

Compiler Settings

Preprocessor MACRO

<Define all the preprocessor Macros needed and conditions when needed>.

Optimization Settings

<Define Optimization levels that are needed and conditions when needed>.

Revision Control Log

Rev #Change DescriptionDateAuthor
1Initial version3-Oct-13VT
Last modified October 12, 2025: Initial commit (0347a62)