Os
Module -- OS
5 Applications Configuration 7
6 Assist Primary Control Task Scheduling 7
7 Known Issues / Limitations With Configuration 8
11
References
MICROSAR OS OSEK/Autosar Realtime Operating System Technical Reference (TechnicalReference_osCAN4.pdf)
AUTOSAR realtime operating system MICROSAR OS TMS570 User’s Manual (MicrosarOS_TMS570.pdf)
TMS570LS3137PGE 16/32-Bit RISC Flash Microcontroller (SPNS166_TMS570LS3137SPGE Prelim.pdf)
Cortex-R4 and Cortex-R4F Technical Reference Manual (DDIO363E_cortexr4_r1p3_trm.pdf)
ISR Configuration
Gpt_IsrInt0
| Attribute Name | Value | Rationale |
| General Settings | ||
| OsIsrCategory | Category_2 | Category 2 configured to allow preemption concerns to be handled by the Os, |
| OsIsrEnableNesting | TRUE | Allow the Motor control ISR to preempt. |
| OsIsrAnalysisPriority | 0 | Default value same as other Demo project ISR’s, this value is used for correctly configuring the osCAN external timing analysis tool. At some point in the future, a correct value should be determined for this. |
| OsIsrComputationTime | 0 | See above rationale |
| OsIsrPeriod | 0 | See above rationale |
| OsIsrDeadline | 0 | See above rationale |
| OsIsrInterruptTarget | IRQ | Cat2 requires IRQ. FIQ not required to meet the ISR execution deadline. |
| OsIsrInterruptSource | INTR2 | “RTI compare interrupt 0” is default VIM interrupt request 2 per [3] |
| OsIsrResourceRef | <Empty> | TBD |
| OsIsrMESSAGE | <Empty> | TBD |
| OsIsrInterruptPriority | 4 | In order to ensure that this Isr does not interfere with the Motor control its priority is being placed below the MtrCtrl interrupt. |
| OsIsrUseSpecialFunctionName | FALSE | |
Isr_ESMH
| Attribute Name | Value | Rationale |
| General Settings | ||
| OsIsrCategory | Category_1 | Fast ISR service desired, OS services not required |
| OsIsrEnableNesting | FALSE | Prevent Interrupt preemption while serving ESM interrupt. Although it seems that this parameter does not apply to a Category 1 interrupt since the OS is not involved with the assertion of the ISR. So the value of this parameter should have no effect. |
| OsIsrAnalysisPriority | 0 | Default value same as other Demo project ISR’s, this value is used for correctly configuring the osCAN external timing analysis tool. At some point in the future, a correct value should be determined for this. |
| OsIsrComputationTime | 0 | See above rationale |
| OsIsrPeriod | 0 | See above rationale |
| OsIsrDeadline | 0 | See above rationale |
| OsIsrInterruptTarget | FIQ | ESMH interrupt is by nature a Non Maskable Interrupt and is service through FIQ. |
| OsIsrInterruptSource | INTR0 | Trigger is the ESM High Level Interrupt |
| OsIsrResourceRef | <Empty> | TBD |
| OsIsrMESSAGE | <Empty> | TBD |
| OsIsrInterruptPriority | 0 | VIM priority “0” is reserved for ESM module. Default value is desired. |
| OsIsrUseSpecialFunctionName | FALSE | Single interrupt source for the ESM ISR, so using the name of this ISR container is fine. |
Isr_MtrCtrl
| Attribute Name | Value | Rationale |
| General Settings | ||
| OsIsrCategory | Category_1 | Fast ISR service desired, OS services not required |
| OsIsrEnableNesting | FALSE | Prevent Interrupt preemption while serving motor control. Although it seems that this parameter does not apply to a Category 1 interrupt since the OS is not involved with the assertion of the ISR. So the value of this parameter should have no effect. |
| OsIsrAnalysisPriority | 0 | Default value same as other Demo project ISR’s, this value is used for correctly configuring the osCAN external timing analysis tool. At some point in the future, a correct value should be determined for this. |
| OsIsrComputationTime | 0 | See above rationale |
| OsIsrPeriod | 0 | See above rationale |
| OsIsrDeadline | 0 | See above rationale |
| OsIsrInterruptTarget | IRQ | FIQ desired since this ISR is high priority and is not to be preempted by any other source. Due to unexplained missed FlexRay interrupts when an FIQ is configured, this is being configured as an IRQ as a workaround. |
| OsIsrInterruptSource | INTR50 | Trigger for motor control ISR is the completion of the ADC2 group 1 conversion triggered by the NHET. |
| OsIsrResourceRef | <Empty> | TBD |
| OsIsrMESSAGE | <Empty> | TBD |
| OsIsrInterruptPriority | 2 | This is the highest priority interrupt in the system. VIM priority scheme reserves priorities 0 and 1. 2 is the highest priority assignment available. |
| OsIsrUseSpecialFunctionName | FALSE | Single interrupt source for the motor control ISR, so using the name of this ISR container is fine. |
Spi_IrqUnit0TxRx
| Attribute Name | Value | Rationale |
| General Settings | ||
| OsIsrCategory | Category_2 | Category 2 configured to allow preemption concerns to be handled by the Os, |
| OsIsrEnableNesting | TRUE | The SPI communication is only used for EEPROM servicing and is low priority. Allow the CAN interrupt, System Tick, and Motor Control to preempt. TBD if Category_1 interrupts can always preempt Category_2.. |
| OsIsrAnalysisPriority | 0 | Default value same as other Demo project ISR’s, this value is used for correctly configuring the osCAN external timing analysis tool. At some point in the future, a correct value should be determined for this. |
| OsIsrComputationTime | 0 | See above rationale |
| OsIsrPeriod | 0 | See above rationale |
| OsIsrDeadline | 0 | See above rationale |
| OsIsrInterruptTarget | IRQ | Cat2 requires IRQ. FIQ not required to meet the ISR execution deadline. |
| OsIsrInterruptSource | INTR26 | Trigger for EEPROM SPI MIBSPI1 per CCA schematic. |
| OsIsrResourceRef | <Empty> | TBD |
| OsIsrMESSAGE | <Empty> | TBD |
| OsIsrInterruptPriority | 26 | TBD |
| OsIsrUseSpecialFunctionName | FALSE | TBD |
Spi_IrqUnit0TxRxERR
| Attribute Name | Value | Rationale |
| General Settings | ||
| OsIsrCategory | Category_2 | Category 2 configured to allow preemption concerns to be handled by the Os, |
| OsIsrEnableNesting | TRUE | The SPI communication is only used for EEPROM servicing and is low priority. Allow the CAN interrupt, System Tick, and Motor Control to preempt. TBD if Category_1 interrupts can always preempt Category_2.. |
| OsIsrAnalysisPriority | 0 | Default value same as other Demo project ISR’s, this value is used for correctly configuring the osCAN external timing analysis tool. At some point in the future, a correct value should be determined for this. |
| OsIsrComputationTime | 0 | See above rationale |
| OsIsrPeriod | 0 | See above rationale |
| OsIsrDeadline | 0 | See above rationale |
| OsIsrInterruptTarget | IRQ | Cat2 requires IRQ. FIQ not required to meet the ISR execution deadline. |
| OsIsrInterruptSource | INTR12 | Trigger for EEPROM SPI MIBSPI1 per CCA schematic. |
| OsIsrResourceRef | <Empty> | TBD |
| OsIsrMESSAGE | <Empty> | TBD |
| OsIsrInterruptPriority | 12 | TBD |
| OsIsrUseSpecialFunctionName | FALSE | TBD |
Task Configuration
Os Configuration
OsOSAPIOptimization
Applications Configuration
Assist Primary Control Task Scheduling
The assist primary control task scheduling requires both low execution period jitter and low latency relative to the ADC measurements on the signals required for the control computations.
TO BE COMPLETED
Known Issues / Limitations With Configuration
Configuration has not been fully reviewed and is based on the Vector Demo project delivered with the SIP.
Code Alterations
Generated Code
The generated configuration requires modifications to be suitable for the Nexteer project. The following table lists the changes required and the rationale.
Included in the GenDataOs folder are a set of scripts and unified diff files to assist in automatically performing the modifications to the generated files. At this time, execution of the Os_Patch.bat script has not been added to the Vector Configurator Os generation step. The user generating the new Os configuration is responsible for launching the Os_Patch.bat script after Os generation and ensuring that the modifications are performed correctly. A future improvement is to further automate the process of applying the modifications.
| File(line) | Change description | Os_Patch.bat Automation |
| intvect.asm | Removal of the generated assembler error directive. The error directive is unconditionally inserted by the Vector generator to ensure the output from the generator is reviewed prior to being built into a system. During Os configuration development at Nexteer it is necessary for the developer to build and test the generated configurations many times while implementing a change request. Nexteer’s process of reviewing the Os generated configuration does not rely on a generated error directive and thus it is removed. | GNU patch utility invoked with invect.diff input. |
| Os_MemMap.h | Inclusion of #undef MEMMAP_ERROR in each memory mapping block to meet the AUTOSAR MemMap requirements | GNU sed utility invoked with find and replace |
* Os_Diff.bat can be invoked to update the *.diff files. It generates the *.diff based on the differences it detects between the primary file in the directory and the *.bak version of the file in the directory.
Static Code
This section describes alterations to the delivered static code files provided by the software supplier. The pertinent source file should be inspected to see the exact change. Line numbers are relative to the altered file line numbering and not the originally delivered file.
| File(line) | Change description |
| osekasm.asm(1374) | Per Error: Reference source not found Sec. 4.1.3.3 an application Prefetch Abort handler is required. Affected Function: osPrefetchAbort The branch instruction is changed to branch to the Nexteer handler in place of the “osUnhandledException” handler. External declaration of function added at line 134. |
| osekasm.asm(1402) | Per Error: Reference source not found Sec. 4.1.3.3 an application Data Abort handler is required. Affected Function: osDataAbort The branch instruction is changed to branch to the Nexteer handler in place of the “osUnhandledException” handler. External declaration of function added at line 135. |
Revision Control Log
| Item # | Rev # | Change Description | Date | Author Initials |
| 1 | 1.0 | Initial Creation | 01MAR13 | JJW |